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[/] [can/] [trunk/] [rtl/] [verilog/] [can_top.v] - Blame information for rev 161

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1 66 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  can_top.v                                                   ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the CAN Protocol Controller            ////
7
////  http://www.opencores.org/projects/can/                      ////
8
////                                                              ////
9
////                                                              ////
10
////  Author(s):                                                  ////
11
////       Igor Mohor                                             ////
12
////       igorm@opencores.org                                    ////
13
////                                                              ////
14
////                                                              ////
15
////  All additional information is available in the README.txt   ////
16
////  file.                                                       ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20 138 mohor
//// Copyright (C) 2002, 2003, 2004 Authors                       ////
21 66 mohor
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
44
//// protected by patents. Anybody who wants to implement this    ////
45
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
46
//// from Bosch.                                                  ////
47
////                                                              ////
48
//////////////////////////////////////////////////////////////////////
49
//
50
// CVS Revision History
51
//
52
// $Log: not supported by cvs2svn $
53 147 igorm
// Revision 1.47  2004/02/08 14:53:54  mohor
54
// Header changed. Address latched to posedge. bus_off_on signal added.
55
//
56 138 mohor
// Revision 1.46  2003/10/17 05:55:20  markom
57
// mbist signals updated according to newest convention
58
//
59 130 markom
// Revision 1.45  2003/09/30 00:55:13  mohor
60
// Error counters fixed to be compatible with Bosch VHDL reference model.
61
// Small synchronization changes.
62
//
63 126 mohor
// Revision 1.44  2003/09/25 18:55:49  mohor
64
// Synchronization changed, error counters fixed.
65
//
66 125 mohor
// Revision 1.43  2003/08/20 09:57:39  mohor
67
// Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
68
// to be joined together on higher level.
69
//
70 117 mohor
// Revision 1.42  2003/07/16 15:11:28  mohor
71
// Fixed according to the linter.
72
//
73 110 mohor
// Revision 1.41  2003/07/10 15:32:27  mohor
74
// Unused signal removed.
75
//
76 106 mohor
// Revision 1.40  2003/07/10 01:59:04  tadejm
77
// Synchronization fixed. In some strange cases it didn't work according to
78
// the VHDL reference model.
79
//
80 104 tadejm
// Revision 1.39  2003/07/07 11:21:37  mohor
81
// Little fixes (to fix warnings).
82
//
83 102 mohor
// Revision 1.38  2003/07/03 09:32:20  mohor
84
// Synchronization changed.
85
//
86 100 mohor
// Revision 1.37  2003/06/27 20:56:15  simons
87
// Virtual silicon ram instances added.
88
//
89 95 simons
// Revision 1.36  2003/06/17 14:30:30  mohor
90
// "chip select" signal cs_can_i is used only when not using WISHBONE
91
// interface.
92
//
93 81 mohor
// Revision 1.35  2003/06/16 13:57:58  mohor
94
// tx_point generated one clk earlier. rx_i registered. Data corrected when
95
// using extended mode.
96
//
97 78 mohor
// Revision 1.34  2003/06/13 15:02:24  mohor
98
// Synchronization is also needed when transmitting a message.
99
//
100 77 mohor
// Revision 1.33  2003/06/11 14:21:35  mohor
101
// When switching to tx, sync stage is overjumped.
102
//
103 75 mohor
// Revision 1.32  2003/06/09 11:32:36  mohor
104
// Ports added for the CAN_BIST.
105
//
106 71 mohor
// Revision 1.31  2003/03/26 11:19:46  mohor
107
// CAN interrupt is active low.
108
//
109 67 mohor
// Revision 1.30  2003/03/20 17:01:17  mohor
110
// unix.
111
//
112 66 mohor
// Revision 1.28  2003/03/14 19:36:48  mohor
113
// can_cs signal used for generation of the cs.
114
//
115
// Revision 1.27  2003/03/12 05:56:33  mohor
116
// Bidirectional port_0_i changed to port_0_io.
117
// input cs_can changed to cs_can_i.
118
//
119
// Revision 1.26  2003/03/12 04:39:40  mohor
120
// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
121
// need to be negated one level higher.
122
//
123
// Revision 1.25  2003/03/12 04:17:36  mohor
124
// 8051 interface added (besides WISHBONE interface). Selection is made in
125
// can_defines.v file.
126
//
127
// Revision 1.24  2003/03/10 17:24:40  mohor
128
// wire declaration added.
129
//
130
// Revision 1.23  2003/03/05 15:33:13  mohor
131
// tx_o is now tristated signal. tx_oen and tx_o combined together.
132
//
133
// Revision 1.22  2003/03/05 15:01:56  mohor
134
// Top level signal names changed.
135
//
136
// Revision 1.21  2003/03/01 22:53:33  mohor
137
// Actel APA ram supported.
138
//
139
// Revision 1.20  2003/02/19 15:09:02  mohor
140
// Incomplete sensitivity list fixed.
141
//
142
// Revision 1.19  2003/02/19 15:04:14  mohor
143
// Typo fixed.
144
//
145
// Revision 1.18  2003/02/19 14:44:03  mohor
146
// CAN core finished. Host interface added. Registers finished.
147
// Synchronization to the wishbone finished.
148
//
149
// Revision 1.17  2003/02/18 00:10:15  mohor
150
// Most of the registers added. Registers "arbitration lost capture", "error code
151
// capture" + few more still need to be added.
152
//
153
// Revision 1.16  2003/02/14 20:17:01  mohor
154
// Several registers added. Not finished, yet.
155
//
156
// Revision 1.15  2003/02/12 14:25:30  mohor
157
// abort_tx added.
158
//
159
// Revision 1.14  2003/02/11 00:56:06  mohor
160
// Wishbone interface added.
161
//
162
// Revision 1.13  2003/02/09 18:40:29  mohor
163
// Overload fixed. Hard synchronization also enabled at the last bit of
164
// interframe.
165
//
166
// Revision 1.12  2003/02/09 02:24:33  mohor
167
// Bosch license warning added. Error counters finished. Overload frames
168
// still need to be fixed.
169
//
170
// Revision 1.11  2003/02/04 14:34:52  mohor
171
// *** empty log message ***
172
//
173
// Revision 1.10  2003/01/31 01:13:38  mohor
174
// backup.
175
//
176
// Revision 1.9  2003/01/15 13:16:48  mohor
177
// When a frame with "remote request" is received, no data is stored to
178
// fifo, just the frame information (identifier, ...). Data length that
179
// is stored is the received data length and not the actual data length
180
// that is stored to fifo.
181
//
182
// Revision 1.8  2003/01/14 17:25:09  mohor
183
// Addresses corrected to decimal values (previously hex).
184
//
185
// Revision 1.7  2003/01/10 17:51:34  mohor
186
// Temporary version (backup).
187
//
188
// Revision 1.6  2003/01/09 21:54:45  mohor
189
// rx fifo added. Not 100 % verified, yet.
190
//
191
// Revision 1.5  2003/01/08 02:10:56  mohor
192
// Acceptance filter added.
193
//
194
// Revision 1.4  2002/12/28 04:13:23  mohor
195
// Backup version.
196
//
197
// Revision 1.3  2002/12/27 00:12:52  mohor
198
// Header changed, testbench improved to send a frame (crc still missing).
199
//
200
// Revision 1.2  2002/12/26 16:00:34  mohor
201
// Testbench define file added. Clock divider register added.
202
//
203
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
204
// Initial
205
//
206
//
207
//
208
 
209
// synopsys translate_off
210
`include "timescale.v"
211
// synopsys translate_on
212
`include "can_defines.v"
213
 
214
module can_top
215
(
216
  `ifdef CAN_WISHBONE_IF
217
    wb_clk_i,
218
    wb_rst_i,
219
    wb_dat_i,
220
    wb_dat_o,
221
    wb_cyc_i,
222
    wb_stb_i,
223
    wb_we_i,
224
    wb_adr_i,
225
    wb_ack_o,
226
  `else
227
    rst_i,
228
    ale_i,
229
    rd_i,
230
    wr_i,
231
    port_0_io,
232 81 mohor
    cs_can_i,
233 66 mohor
  `endif
234
  clk_i,
235
  rx_i,
236
  tx_o,
237 138 mohor
  bus_off_on,
238 67 mohor
  irq_on,
239 66 mohor
  clkout_o
240 117 mohor
 
241 71 mohor
  // Bist
242
`ifdef CAN_BIST
243
  ,
244
  // debug chain signals
245 130 markom
  mbist_si_i,       // bist scan serial in
246
  mbist_so_o,       // bist scan serial out
247
  mbist_ctrl_i        // bist chain shift control
248 71 mohor
`endif
249 66 mohor
);
250
 
251
parameter Tp = 1;
252
 
253 81 mohor
 
254 66 mohor
`ifdef CAN_WISHBONE_IF
255
  input        wb_clk_i;
256
  input        wb_rst_i;
257
  input  [7:0] wb_dat_i;
258
  output [7:0] wb_dat_o;
259
  input        wb_cyc_i;
260
  input        wb_stb_i;
261
  input        wb_we_i;
262
  input  [7:0] wb_adr_i;
263
  output       wb_ack_o;
264
 
265
  reg          wb_ack_o;
266
  reg          cs_sync1;
267
  reg          cs_sync2;
268
  reg          cs_sync3;
269
 
270
  reg          cs_ack1;
271
  reg          cs_ack2;
272
  reg          cs_ack3;
273
  reg          cs_sync_rst1;
274
  reg          cs_sync_rst2;
275 81 mohor
  wire         cs_can_i;
276 66 mohor
`else
277
  input        rst_i;
278
  input        ale_i;
279
  input        rd_i;
280
  input        wr_i;
281
  inout  [7:0] port_0_io;
282 81 mohor
  input        cs_can_i;
283 66 mohor
 
284
  reg    [7:0] addr_latched;
285
  reg          wr_i_q;
286
  reg          rd_i_q;
287
`endif
288
 
289
input        clk_i;
290
input        rx_i;
291
output       tx_o;
292 138 mohor
output       bus_off_on;
293 67 mohor
output       irq_on;
294 66 mohor
output       clkout_o;
295
 
296 71 mohor
// Bist
297
`ifdef CAN_BIST
298 130 markom
input   mbist_si_i;       // bist scan serial in
299
output  mbist_so_o;       // bist scan serial out
300
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
301 71 mohor
`endif
302
 
303 66 mohor
reg          data_out_fifo_selected;
304
 
305
 
306
wire   [7:0] data_out_fifo;
307
wire   [7:0] data_out_regs;
308
 
309
 
310
/* Mode register */
311
wire         reset_mode;
312
wire         listen_only_mode;
313
wire         acceptance_filter_mode;
314
wire         self_test_mode;
315
 
316
/* Command register */
317
wire         release_buffer;
318
wire         tx_request;
319
wire         abort_tx;
320
wire         self_rx_request;
321
wire         single_shot_transmission;
322 104 tadejm
wire         tx_state;
323
wire         tx_state_q;
324 125 mohor
wire         overload_request;
325
wire         overload_frame;
326 66 mohor
 
327 125 mohor
 
328 66 mohor
/* Arbitration Lost Capture Register */
329
wire         read_arbitration_lost_capture_reg;
330
 
331
/* Error Code Capture Register */
332
wire         read_error_code_capture_reg;
333
wire   [7:0] error_capture_code;
334
 
335
/* Bus Timing 0 register */
336
wire   [5:0] baud_r_presc;
337
wire   [1:0] sync_jump_width;
338
 
339
/* Bus Timing 1 register */
340
wire   [3:0] time_segment1;
341
wire   [2:0] time_segment2;
342
wire         triple_sampling;
343
 
344
/* Error Warning Limit register */
345
wire   [7:0] error_warning_limit;
346
 
347
/* Rx Error Counter register */
348
wire         we_rx_err_cnt;
349
 
350
/* Tx Error Counter register */
351
wire         we_tx_err_cnt;
352
 
353
/* Clock Divider register */
354
wire         extended_mode;
355
 
356
/* This section is for BASIC and EXTENDED mode */
357
/* Acceptance code register */
358
wire   [7:0] acceptance_code_0;
359
 
360
/* Acceptance mask register */
361
wire   [7:0] acceptance_mask_0;
362
/* End: This section is for BASIC and EXTENDED mode */
363
 
364
 
365
/* This section is for EXTENDED mode */
366
/* Acceptance code register */
367
wire   [7:0] acceptance_code_1;
368
wire   [7:0] acceptance_code_2;
369
wire   [7:0] acceptance_code_3;
370
 
371
/* Acceptance mask register */
372
wire   [7:0] acceptance_mask_1;
373
wire   [7:0] acceptance_mask_2;
374
wire   [7:0] acceptance_mask_3;
375
/* End: This section is for EXTENDED mode */
376
 
377
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
378
wire   [7:0] tx_data_0;
379
wire   [7:0] tx_data_1;
380
wire   [7:0] tx_data_2;
381
wire   [7:0] tx_data_3;
382
wire   [7:0] tx_data_4;
383
wire   [7:0] tx_data_5;
384
wire   [7:0] tx_data_6;
385
wire   [7:0] tx_data_7;
386
wire   [7:0] tx_data_8;
387
wire   [7:0] tx_data_9;
388
wire   [7:0] tx_data_10;
389
wire   [7:0] tx_data_11;
390
wire   [7:0] tx_data_12;
391
/* End: Tx data registers */
392
 
393
wire         cs;
394
 
395
/* Output signals from can_btl module */
396
wire         sample_point;
397
wire         sampled_bit;
398
wire         sampled_bit_q;
399
wire         tx_point;
400
wire         hard_sync;
401
 
402
/* output from can_bsp module */
403
wire         rx_idle;
404
wire         transmitting;
405 125 mohor
wire         transmitter;
406
wire         go_rx_inter;
407 104 tadejm
wire         not_first_bit_of_inter;
408 66 mohor
wire         set_reset_mode;
409
wire         node_bus_off;
410
wire         error_status;
411
wire   [7:0] rx_err_cnt;
412
wire   [7:0] tx_err_cnt;
413
wire         rx_err_cnt_dummy;  // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
414
wire         tx_err_cnt_dummy;  // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
415
wire         transmit_status;
416
wire         receive_status;
417
wire         tx_successful;
418
wire         need_to_tx;
419
wire         overrun;
420
wire         info_empty;
421
wire         set_bus_error_irq;
422
wire         set_arbitration_lost_irq;
423
wire   [4:0] arbitration_lost_capture;
424
wire         node_error_passive;
425
wire         node_error_active;
426
wire   [6:0] rx_message_counter;
427 125 mohor
wire         tx_next;
428 66 mohor
 
429 125 mohor
wire         go_overload_frame;
430
wire         go_error_frame;
431
wire         go_tx;
432
wire         send_ack;
433
 
434 66 mohor
wire         rst;
435
wire         we;
436
wire   [7:0] addr;
437
wire   [7:0] data_in;
438
reg    [7:0] data_out;
439 125 mohor
reg          rx_sync_tmp;
440
reg          rx_sync;
441 66 mohor
 
442
/* Connecting can_registers module */
443
can_registers i_can_registers
444
(
445
  .clk(clk_i),
446
  .rst(rst),
447
  .cs(cs),
448
  .we(we),
449
  .addr(addr),
450
  .data_in(data_in),
451
  .data_out(data_out_regs),
452 147 igorm
  .irq_n(irq_on),
453 66 mohor
 
454
  .sample_point(sample_point),
455
  .transmitting(transmitting),
456
  .set_reset_mode(set_reset_mode),
457
  .node_bus_off(node_bus_off),
458
  .error_status(error_status),
459
  .rx_err_cnt(rx_err_cnt),
460
  .tx_err_cnt(tx_err_cnt),
461
  .transmit_status(transmit_status),
462
  .receive_status(receive_status),
463
  .tx_successful(tx_successful),
464
  .need_to_tx(need_to_tx),
465
  .overrun(overrun),
466
  .info_empty(info_empty),
467
  .set_bus_error_irq(set_bus_error_irq),
468
  .set_arbitration_lost_irq(set_arbitration_lost_irq),
469
  .arbitration_lost_capture(arbitration_lost_capture),
470
  .node_error_passive(node_error_passive),
471
  .node_error_active(node_error_active),
472
  .rx_message_counter(rx_message_counter),
473
 
474
 
475
  /* Mode register */
476
  .reset_mode(reset_mode),
477
  .listen_only_mode(listen_only_mode),
478
  .acceptance_filter_mode(acceptance_filter_mode),
479
  .self_test_mode(self_test_mode),
480
 
481
  /* Command register */
482
  .clear_data_overrun(),
483
  .release_buffer(release_buffer),
484
  .abort_tx(abort_tx),
485
  .tx_request(tx_request),
486
  .self_rx_request(self_rx_request),
487
  .single_shot_transmission(single_shot_transmission),
488 104 tadejm
  .tx_state(tx_state),
489
  .tx_state_q(tx_state_q),
490 125 mohor
  .overload_request(overload_request),
491
  .overload_frame(overload_frame),
492 66 mohor
 
493
  /* Arbitration Lost Capture Register */
494
  .read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
495
 
496
  /* Error Code Capture Register */
497
  .read_error_code_capture_reg(read_error_code_capture_reg),
498
  .error_capture_code(error_capture_code),
499
 
500
  /* Bus Timing 0 register */
501
  .baud_r_presc(baud_r_presc),
502
  .sync_jump_width(sync_jump_width),
503
 
504
  /* Bus Timing 1 register */
505
  .time_segment1(time_segment1),
506
  .time_segment2(time_segment2),
507
  .triple_sampling(triple_sampling),
508
 
509
  /* Error Warning Limit register */
510
  .error_warning_limit(error_warning_limit),
511
 
512
  /* Rx Error Counter register */
513
  .we_rx_err_cnt(we_rx_err_cnt),
514
 
515
  /* Tx Error Counter register */
516
  .we_tx_err_cnt(we_tx_err_cnt),
517
 
518
  /* Clock Divider register */
519
  .extended_mode(extended_mode),
520
  .clkout(clkout_o),
521
 
522
  /* This section is for BASIC and EXTENDED mode */
523
  /* Acceptance code register */
524
  .acceptance_code_0(acceptance_code_0),
525
 
526
  /* Acceptance mask register */
527
  .acceptance_mask_0(acceptance_mask_0),
528
  /* End: This section is for BASIC and EXTENDED mode */
529
 
530
  /* This section is for EXTENDED mode */
531
  /* Acceptance code register */
532
  .acceptance_code_1(acceptance_code_1),
533
  .acceptance_code_2(acceptance_code_2),
534
  .acceptance_code_3(acceptance_code_3),
535
 
536
  /* Acceptance mask register */
537
  .acceptance_mask_1(acceptance_mask_1),
538
  .acceptance_mask_2(acceptance_mask_2),
539
  .acceptance_mask_3(acceptance_mask_3),
540
  /* End: This section is for EXTENDED mode */
541
 
542
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
543
  .tx_data_0(tx_data_0),
544
  .tx_data_1(tx_data_1),
545
  .tx_data_2(tx_data_2),
546
  .tx_data_3(tx_data_3),
547
  .tx_data_4(tx_data_4),
548
  .tx_data_5(tx_data_5),
549
  .tx_data_6(tx_data_6),
550
  .tx_data_7(tx_data_7),
551
  .tx_data_8(tx_data_8),
552
  .tx_data_9(tx_data_9),
553
  .tx_data_10(tx_data_10),
554
  .tx_data_11(tx_data_11),
555
  .tx_data_12(tx_data_12)
556
  /* End: Tx data registers */
557
);
558
 
559
 
560
 
561
 
562
/* Connecting can_btl module */
563
can_btl i_can_btl
564
(
565
  .clk(clk_i),
566
  .rst(rst),
567 125 mohor
  .rx(rx_sync),
568
  .tx(tx_o),
569 66 mohor
 
570
  /* Bus Timing 0 register */
571
  .baud_r_presc(baud_r_presc),
572
  .sync_jump_width(sync_jump_width),
573
 
574
  /* Bus Timing 1 register */
575
  .time_segment1(time_segment1),
576
  .time_segment2(time_segment2),
577
  .triple_sampling(triple_sampling),
578
 
579
  /* Output signals from this module */
580
  .sample_point(sample_point),
581
  .sampled_bit(sampled_bit),
582
  .sampled_bit_q(sampled_bit_q),
583
  .tx_point(tx_point),
584
  .hard_sync(hard_sync),
585
 
586
 
587
  /* output from can_bsp module */
588
  .rx_idle(rx_idle),
589 126 mohor
  .rx_inter(rx_inter),
590 125 mohor
  .transmitting(transmitting),
591
  .transmitter(transmitter),
592
  .go_rx_inter(go_rx_inter),
593
  .tx_next(tx_next),
594
 
595
  .go_overload_frame(go_overload_frame),
596
  .go_error_frame(go_error_frame),
597
  .go_tx(go_tx),
598
  .send_ack(send_ack),
599
  .node_error_passive(node_error_passive)
600 66 mohor
 
601
 
602
 
603
);
604
 
605
 
606
 
607
can_bsp i_can_bsp
608
(
609
  .clk(clk_i),
610
  .rst(rst),
611
 
612
  /* From btl module */
613
  .sample_point(sample_point),
614
  .sampled_bit(sampled_bit),
615
  .sampled_bit_q(sampled_bit_q),
616
  .tx_point(tx_point),
617
  .hard_sync(hard_sync),
618
 
619
  .addr(addr),
620
  .data_in(data_in),
621
  .data_out(data_out_fifo),
622
  .fifo_selected(data_out_fifo_selected),
623
 
624
  /* Mode register */
625
  .reset_mode(reset_mode),
626
  .listen_only_mode(listen_only_mode),
627
  .acceptance_filter_mode(acceptance_filter_mode),
628
  .self_test_mode(self_test_mode),
629
 
630
  /* Command register */
631
  .release_buffer(release_buffer),
632
  .tx_request(tx_request),
633
  .abort_tx(abort_tx),
634
  .self_rx_request(self_rx_request),
635
  .single_shot_transmission(single_shot_transmission),
636 104 tadejm
  .tx_state(tx_state),
637
  .tx_state_q(tx_state_q),
638 125 mohor
  .overload_request(overload_request),
639
  .overload_frame(overload_frame),
640 66 mohor
 
641
  /* Arbitration Lost Capture Register */
642
  .read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
643
 
644
  /* Error Code Capture Register */
645
  .read_error_code_capture_reg(read_error_code_capture_reg),
646
  .error_capture_code(error_capture_code),
647
 
648
  /* Error Warning Limit register */
649
  .error_warning_limit(error_warning_limit),
650
 
651
  /* Rx Error Counter register */
652
  .we_rx_err_cnt(we_rx_err_cnt),
653
 
654
  /* Tx Error Counter register */
655
  .we_tx_err_cnt(we_tx_err_cnt),
656
 
657
  /* Clock Divider register */
658
  .extended_mode(extended_mode),
659
 
660
  /* output from can_bsp module */
661
  .rx_idle(rx_idle),
662
  .transmitting(transmitting),
663 125 mohor
  .transmitter(transmitter),
664 100 mohor
  .go_rx_inter(go_rx_inter),
665 104 tadejm
  .not_first_bit_of_inter(not_first_bit_of_inter),
666 126 mohor
  .rx_inter(rx_inter),
667 66 mohor
  .set_reset_mode(set_reset_mode),
668
  .node_bus_off(node_bus_off),
669
  .error_status(error_status),
670
  .rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}),   // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
671
  .tx_err_cnt({tx_err_cnt_dummy, tx_err_cnt[7:0]}),   // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
672
  .transmit_status(transmit_status),
673
  .receive_status(receive_status),
674
  .tx_successful(tx_successful),
675
  .need_to_tx(need_to_tx),
676
  .overrun(overrun),
677
  .info_empty(info_empty),
678
  .set_bus_error_irq(set_bus_error_irq),
679
  .set_arbitration_lost_irq(set_arbitration_lost_irq),
680
  .arbitration_lost_capture(arbitration_lost_capture),
681
  .node_error_passive(node_error_passive),
682
  .node_error_active(node_error_active),
683
  .rx_message_counter(rx_message_counter),
684
 
685
  /* This section is for BASIC and EXTENDED mode */
686
  /* Acceptance code register */
687
  .acceptance_code_0(acceptance_code_0),
688
 
689
  /* Acceptance mask register */
690
  .acceptance_mask_0(acceptance_mask_0),
691
  /* End: This section is for BASIC and EXTENDED mode */
692
 
693
  /* This section is for EXTENDED mode */
694
  /* Acceptance code register */
695
  .acceptance_code_1(acceptance_code_1),
696
  .acceptance_code_2(acceptance_code_2),
697
  .acceptance_code_3(acceptance_code_3),
698
 
699
  /* Acceptance mask register */
700
  .acceptance_mask_1(acceptance_mask_1),
701
  .acceptance_mask_2(acceptance_mask_2),
702
  .acceptance_mask_3(acceptance_mask_3),
703
  /* End: This section is for EXTENDED mode */
704
 
705
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
706
  .tx_data_0(tx_data_0),
707
  .tx_data_1(tx_data_1),
708
  .tx_data_2(tx_data_2),
709
  .tx_data_3(tx_data_3),
710
  .tx_data_4(tx_data_4),
711
  .tx_data_5(tx_data_5),
712
  .tx_data_6(tx_data_6),
713
  .tx_data_7(tx_data_7),
714
  .tx_data_8(tx_data_8),
715
  .tx_data_9(tx_data_9),
716
  .tx_data_10(tx_data_10),
717
  .tx_data_11(tx_data_11),
718
  .tx_data_12(tx_data_12),
719
  /* End: Tx data registers */
720
 
721
  /* Tx signal */
722 117 mohor
  .tx(tx_o),
723 125 mohor
  .tx_next(tx_next),
724 138 mohor
  .bus_off_on(bus_off_on),
725 95 simons
 
726 125 mohor
  .go_overload_frame(go_overload_frame),
727
  .go_error_frame(go_error_frame),
728
  .go_tx(go_tx),
729
  .send_ack(send_ack)
730
 
731
 
732 95 simons
`ifdef CAN_BIST
733
  ,
734
  /* BIST signals */
735 130 markom
  .mbist_si_i(mbist_si_i),
736
  .mbist_so_o(mbist_so_o),
737
  .mbist_ctrl_i(mbist_ctrl_i)
738 95 simons
`endif
739 66 mohor
);
740
 
741
 
742
 
743
// Multiplexing wb_dat_o from registers and rx fifo
744
always @ (extended_mode or addr or reset_mode)
745
begin
746
  if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
747 110 mohor
    data_out_fifo_selected = 1'b1;
748 66 mohor
  else
749 110 mohor
    data_out_fifo_selected = 1'b0;
750 66 mohor
end
751
 
752
 
753
always @ (posedge clk_i)
754
begin
755
  if (cs & (~we))
756
    begin
757
      if (data_out_fifo_selected)
758
        data_out <=#Tp data_out_fifo;
759
      else
760
        data_out <=#Tp data_out_regs;
761
    end
762
end
763
 
764
 
765
 
766 78 mohor
always @ (posedge clk_i or posedge rst)
767
begin
768
  if (rst)
769 125 mohor
    begin
770
      rx_sync_tmp <= 1'b1;
771
      rx_sync     <= 1'b1;
772
    end
773 78 mohor
  else
774 125 mohor
    begin
775
      rx_sync_tmp <=#Tp rx_i;
776
      rx_sync     <=#Tp rx_sync_tmp;
777
    end
778 78 mohor
end
779
 
780
 
781
 
782 66 mohor
`ifdef CAN_WISHBONE_IF
783 81 mohor
 
784
  assign cs_can_i = 1'b1;
785
 
786 66 mohor
  // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain. 
787
  always @ (posedge clk_i or posedge rst)
788
  begin
789
    if (rst)
790
      begin
791
        cs_sync1     <= 1'b0;
792
        cs_sync2     <= 1'b0;
793
        cs_sync3     <= 1'b0;
794
        cs_sync_rst1 <= 1'b0;
795
        cs_sync_rst2 <= 1'b0;
796
      end
797
    else
798
      begin
799
        cs_sync1     <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
800
        cs_sync2     <=#Tp cs_sync1            & (~cs_sync_rst2);
801
        cs_sync3     <=#Tp cs_sync2            & (~cs_sync_rst2);
802
        cs_sync_rst1 <=#Tp cs_ack3;
803
        cs_sync_rst2 <=#Tp cs_sync_rst1;
804
      end
805
  end
806
 
807
 
808
  assign cs = cs_sync2 & (~cs_sync3);
809
 
810
 
811
  always @ (posedge wb_clk_i)
812
  begin
813
    cs_ack1 <=#Tp cs_sync3;
814
    cs_ack2 <=#Tp cs_ack1;
815
    cs_ack3 <=#Tp cs_ack2;
816
  end
817
 
818
 
819
 
820
  // Generating acknowledge signal
821
  always @ (posedge wb_clk_i)
822
  begin
823
    wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
824
  end
825
 
826
 
827
  assign rst      = wb_rst_i;
828
  assign we       = wb_we_i;
829
  assign addr     = wb_adr_i;
830
  assign data_in  = wb_dat_i;
831
  assign wb_dat_o = data_out;
832
 
833
 
834
`else
835
 
836
  // Latching address
837 138 mohor
  always @ (posedge clk_i or posedge rst)
838 66 mohor
  begin
839
    if (rst)
840
      addr_latched <= 8'h0;
841
    else if (ale_i)
842
      addr_latched <=#Tp port_0_io;
843
  end
844
 
845
 
846
  // Generating delayed wr_i and rd_i signals
847
  always @ (posedge clk_i or posedge rst)
848
  begin
849
    if (rst)
850
      begin
851
        wr_i_q <= 1'b0;
852
        rd_i_q <= 1'b0;
853
      end
854
    else
855
      begin
856
        wr_i_q <=#Tp wr_i;
857
        rd_i_q <=#Tp rd_i;
858
      end
859
  end
860
 
861
 
862
  assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;
863
 
864
 
865
  assign rst       = rst_i;
866
  assign we        = wr_i;
867
  assign addr      = addr_latched;
868
  assign data_in   = port_0_io;
869
  assign port_0_io = (cs_can_i & rd_i)? data_out : 8'hz;
870
 
871
`endif
872
 
873 78 mohor
 
874 66 mohor
endmodule

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