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[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [kernel.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.math_real."log2";
 
entity filterH is
  generic (
        DATA_WIDTH : integer := 8;
        GRAD_WIDTH : integer := 16
        );
  port (
        clk  : in std_logic;
        fsync   : in std_logic;
        pData1  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData2  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData3  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData4  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData5  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData6  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData7  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData8  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        pData9  : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        --fsync_o : out std_logic;
        Xdata_o : out std_logic_vector(GRAD_WIDTH-1 downto 0); -- X gradient
        Ydata_o : out std_logic_vector(GRAD_WIDTH-1 downto 0) -- Y gradient
        );
  end entity filterH;
 
architecture Behavioral of filterH is
 
signal p1x,p2x,p3x,p4x,p5x,p6x,p7x,p8x,p9x : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1xa,p2xa,p3xa,p4xa,p5xa,p6xa,p7xa,p8xa,p9xa : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1xb,p2xb,p3xb,p4xb,p5xb,p6xb,p7xb,p8xb,p9xb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
signal p1y,p2y,p3y,p4y,p5y,p6y,p7y,p8y,p9y : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1ya,p2ya,p3ya,p4ya,p5ya,p6ya,p7ya,p8ya,p9ya : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1yb,p2yb,p3yb,p4yb,p5yb,p6yb,p7yb,p8yb,p9yb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
signal sX1,sX2,sY1,sY2     : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal SX1c, sX2c, sYc     : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal sX1a,sX1b,sX2a,sX2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal sY1a,sY1b,sY2a,sY2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
begin
 
--1----------------------------------------
  prod1 : process (clk) -- for the frame sync signal
  begin
        if rising_edge(clk) then
          if fsync ='1' then
 
-------------------------------------------------------------------GRAD_X_hardwired multipliers
 
          p1xa <=((GRAD_WIDTH-1 downto (8+7) => '0') & pData1 & (7-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+4) => '0') & pData1 & (4-1 downto 0 => '0'));
          p1xb <=((GRAD_WIDTH-1 downto (8+0) => '0') & pData1);
 
          p2xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData2 & (8-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+7) => '0') & pData2 & (7-1 downto 0 => '0'));
          p2xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData2 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+4) => '0') & pData2 & (4-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+2) => '0') & pData2 & (2-1 downto 0 => '0'));
 
          p3xa <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData3 & (9-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+7) => '0') & pData3 & (7-1 downto 0 => '0'));
          p3xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData3 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+3) => '0') & pData3 & (3-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+1) => '0') & pData3 & (1-1 downto 0 => '0'));
 
          p4xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData4 & (8-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+6) => '0') & pData4 & (6-1 downto 0 => '0'));
          p4xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData4 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+4) => '0') & pData4 & (4-1 downto 0 => '0'));
 
 
          p5xb <= (others => '0');
          p5xa <= (others => '0');
          --p5xa <= x"000000" & pData5;--------DEBUG-------------
 
          p6xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData6 & (8-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+6) => '0') & pData6 & (6-1 downto 0 => '0'));
          p6xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData6 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+4) => '0') & pData6 & (4-1 downto 0 => '0'));
 
          p7xa <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData7 & (9-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+7) => '0') & pData7 & (7-1 downto 0 => '0'));
          p7xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData7 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+3) => '0') & pData7 & (3-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+1) => '0') & pData7 & (1-1 downto 0 => '0'));
 
          p8xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData8 & (8-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+7) => '0') & pData8 & (7-1 downto 0 => '0'));
          p8xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData8 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+4) => '0') & pData8 & (4-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+2) => '0') & pData8 & (2-1 downto 0 => '0'));
 
          p9xa <=((GRAD_WIDTH-1 downto (8+7) => '0') & pData9 & (7-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+4) => '0') & pData9 & (4-1 downto 0 => '0'));
          p9xb <=((GRAD_WIDTH-1 downto (8+0) => '0') & pData9);
 
-------------------------------------------------------------------GRAD_Y_hardwired multipliers
 
          p1ya <=((GRAD_WIDTH-1 downto (8+4) => '0') & pData1 & (4-1 downto 0 => '0'));
          p1yb <=(others=>'0');
 
          p2ya <=((GRAD_WIDTH-1 downto (8+6) => '0') & pData2 & (6-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+4) => '0') & pData2 & (4-1 downto 0 => '0'));
          p2yb <=((GRAD_WIDTH-1 downto (8+2) => '0') & pData2 & (2-1 downto 0 => '0'));
 
          p3ya <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData3 & (8-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+5) => '0') & pData3 & (5-1 downto 0 => '0'));
          p3yb <=((GRAD_WIDTH-1 downto (8+3) => '0') & pData3 & (3-1 downto 0 => '0'));
 
          p4ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData4 & (9-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+6) => '0') & pData4 & (6-1 downto 0 => '0'));
          p4yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData4 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+4) => '0') & pData4 & (4-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+1) => '0') & pData4 & (1-1 downto 0 => '0'));
 
          p5ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData5 & (9-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+8) => '0') & pData5 & (8-1 downto 0 => '0'));
          p5yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData5 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+2) => '0') & pData5 & (2-1 downto 0 => '0'));
 
          p6ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData6 & (9-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+6) => '0') & pData6 & (6-1 downto 0 => '0'));
          p6yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData6 & (5-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+4) => '0') & pData6 & (4-1 downto 0 => '0')) +
                         ((GRAD_WIDTH-1 downto (8+1) => '0') & pData6 & (1-1 downto 0 => '0'));
 
          p7ya <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData7 & (8-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+5) => '0') & pData7 & (5-1 downto 0 => '0'));
          p7yb <=((GRAD_WIDTH-1 downto (8+3) => '0') & pData7 & (3-1 downto 0 => '0'));
 
          p8ya <=((GRAD_WIDTH-1 downto (8+6) => '0') & pData8 & (6-1 downto 0 => '0')) +
                     ((GRAD_WIDTH-1 downto (8+4) => '0') & pData8 & (4-1 downto 0 => '0'));
          p8yb <=((GRAD_WIDTH-1 downto (8+2) => '0') & pData8 & (2-1 downto 0 => '0'));
 
          p9ya <=((GRAD_WIDTH-1 downto (8+4) => '0') & pData9 & (4-1 downto 0 => '0'));
          p9yb <=(others=>'0');
        end if;
        end if;
  end process prod1;
 
--2----------------------------------------    
  prod2 : process (clk) -- for the frame sync signal
  begin
        if rising_edge(clk) then
        if fsync ='1' then
          p1x <= p1xa + p1xb;
          p2x <= p2xa + p2xb;
          p3x <= p3xa + p3xb;
          p4x <= p4xa + p4xb;
          p5x <= p5xa + p5xb;
          p6x <= p6xa + p6xb;
          p7x <= p7xa + p7xb;
          p8x <= p8xa + p8xb;
          p9x <= p9xa + p9xb;
          --
          p1y <= p1ya + p1yb;
          p2y <= p2ya + p2yb;
          p3y <= p3ya + p3yb;
          p4y <= p4ya + p4yb;
          p5y <= p5ya + p5yb;
          p6y <= p6ya + p6yb;
          p7y <= p7ya + p7yb;
          p8y <= p8ya + p8yb;
          p9y <= p9ya + p9yb;
        end if;
        end if;
  end process prod2;
 
--3---------------------------------------- 
  sum1 : process (clk)
  begin
        if rising_edge(clk) then
        if fsync ='1' then
          --sX1a <= p5x; ----DEBUG-----------
          sX1a <= p1x+p2x;
          sX1b <= p3x+p4x;
          sX2a <= p6x+p7x;
          sX2b <= p8x+p9x;
          sY1a <= p1y+p2y;
          sY1b <= p3y+p4y;
          sY2a <= p5y+p6y;
          sY2b <= p7y+p8y+p9y;
        end if;
        end if;
  end process sum1;
 
--4---------------------------------------- 
  sum2 : process (clk)
  begin
        if rising_edge(clk) then
        if fsync ='1' then
          --sX1 <= sX1a; ----DEBUG-----------
          sX1 <= sX1a+sX1b;
          sX2 <= sX2a+sX2b;
          sY1 <= sY1a+sY1b;
          sY2 <= sY2a+sY2b;
        end if;
        end if;
  end process sum2;
 
--5---------------------------------------- 
  sum3 : process (clk)
  begin
        if rising_edge(clk) then
        if fsync ='1' then
            sX2c <= (not sX2) + 1;
            sX1c <= sX1;
            sYc  <= sY1+sY2;
        end if;
        end if;
  end process sum3;
 
--6---------------------------------------- 
  outp : process (clk)
  begin
        if rising_edge(clk) then
        if fsync ='1' then
                --Xdata_o <= sX1c; -------DEBUG-------
           Xdata_o <= sX1c+sX2c;
                Ydata_o <= (not sYc) + 1;
        end if;
        end if;
  end process outp;
 
end Behavioral;

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Subversion Repositories canny_edge_detector

[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [kernel.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	angelobacc	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.std_logic_arith.all;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5			`--use IEEE.math_real."log2";`
6
7			`entity filterH is`
8			`generic (`
9			`DATA_WIDTH : integer := 8;`
10			`GRAD_WIDTH : integer := 16`
11			`);`
12			`port (`
13			`clk : in std_logic;`
14			`fsync : in std_logic;`
15			`pData1 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
16			`pData2 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
17			`pData3 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
18			`pData4 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
19			`pData5 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
20			`pData6 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
21			`pData7 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
22			`pData8 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
23			`pData9 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);`
24			`--fsync_o : out std_logic;`
25			`Xdata_o : out std_logic_vector(GRAD_WIDTH-1 downto 0); -- X gradient`
26			`Ydata_o : out std_logic_vector(GRAD_WIDTH-1 downto 0) -- Y gradient`
27			`);`
28			`end entity filterH;`
29
30			`architecture Behavioral of filterH is`
31
32			`signal p1x,p2x,p3x,p4x,p5x,p6x,p7x,p8x,p9x : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
33			`signal p1xa,p2xa,p3xa,p4xa,p5xa,p6xa,p7xa,p8xa,p9xa : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
34			`signal p1xb,p2xb,p3xb,p4xb,p5xb,p6xb,p7xb,p8xb,p9xb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
35
36			`signal p1y,p2y,p3y,p4y,p5y,p6y,p7y,p8y,p9y : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
37			`signal p1ya,p2ya,p3ya,p4ya,p5ya,p6ya,p7ya,p8ya,p9ya : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
38			`signal p1yb,p2yb,p3yb,p4yb,p5yb,p6yb,p7yb,p8yb,p9yb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
39
40			`signal sX1,sX2,sY1,sY2 : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
41			`signal SX1c, sX2c, sYc : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
42			`signal sX1a,sX1b,sX2a,sX2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
43			`signal sY1a,sY1b,sY2a,sY2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);`
44
45			`begin`
46
47			`--1----------------------------------------`
48			`prod1 : process (clk) -- for the frame sync signal`
49			`begin`
50			`if rising_edge(clk) then`
51			`if fsync ='1' then`
52
53			`-------------------------------------------------------------------GRAD_X_hardwired multipliers`
54
55			`p1xa <=((GRAD_WIDTH-1 downto (8+7) => '0') & pData1 & (7-1 downto 0 => '0')) +`
56			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData1 & (4-1 downto 0 => '0'));`
57			`p1xb <=((GRAD_WIDTH-1 downto (8+0) => '0') & pData1);`
58
59			`p2xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData2 & (8-1 downto 0 => '0')) +`
60			`((GRAD_WIDTH-1 downto (8+7) => '0') & pData2 & (7-1 downto 0 => '0'));`
61			`p2xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData2 & (5-1 downto 0 => '0')) +`
62			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData2 & (4-1 downto 0 => '0')) +`
63			`((GRAD_WIDTH-1 downto (8+2) => '0') & pData2 & (2-1 downto 0 => '0'));`
64
65			`p3xa <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData3 & (9-1 downto 0 => '0')) +`
66			`((GRAD_WIDTH-1 downto (8+7) => '0') & pData3 & (7-1 downto 0 => '0'));`
67			`p3xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData3 & (5-1 downto 0 => '0')) +`
68			`((GRAD_WIDTH-1 downto (8+3) => '0') & pData3 & (3-1 downto 0 => '0')) +`
69			`((GRAD_WIDTH-1 downto (8+1) => '0') & pData3 & (1-1 downto 0 => '0'));`
70
71			`p4xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData4 & (8-1 downto 0 => '0')) +`
72			`((GRAD_WIDTH-1 downto (8+6) => '0') & pData4 & (6-1 downto 0 => '0'));`
73			`p4xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData4 & (5-1 downto 0 => '0')) +`
74			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData4 & (4-1 downto 0 => '0'));`
75
76
77			`p5xb <= (others => '0');`
78			`p5xa <= (others => '0');`
79			`--p5xa <= x"000000" & pData5;--------DEBUG-------------`
80
81			`p6xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData6 & (8-1 downto 0 => '0')) +`
82			`((GRAD_WIDTH-1 downto (8+6) => '0') & pData6 & (6-1 downto 0 => '0'));`
83			`p6xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData6 & (5-1 downto 0 => '0')) +`
84			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData6 & (4-1 downto 0 => '0'));`
85
86			`p7xa <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData7 & (9-1 downto 0 => '0')) +`
87			`((GRAD_WIDTH-1 downto (8+7) => '0') & pData7 & (7-1 downto 0 => '0'));`
88			`p7xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData7 & (5-1 downto 0 => '0')) +`
89			`((GRAD_WIDTH-1 downto (8+3) => '0') & pData7 & (3-1 downto 0 => '0')) +`
90			`((GRAD_WIDTH-1 downto (8+1) => '0') & pData7 & (1-1 downto 0 => '0'));`
91
92			`p8xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData8 & (8-1 downto 0 => '0')) +`
93			`((GRAD_WIDTH-1 downto (8+7) => '0') & pData8 & (7-1 downto 0 => '0'));`
94			`p8xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData8 & (5-1 downto 0 => '0')) +`
95			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData8 & (4-1 downto 0 => '0')) +`
96			`((GRAD_WIDTH-1 downto (8+2) => '0') & pData8 & (2-1 downto 0 => '0'));`
97
98			`p9xa <=((GRAD_WIDTH-1 downto (8+7) => '0') & pData9 & (7-1 downto 0 => '0')) +`
99			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData9 & (4-1 downto 0 => '0'));`
100			`p9xb <=((GRAD_WIDTH-1 downto (8+0) => '0') & pData9);`
101
102			`-------------------------------------------------------------------GRAD_Y_hardwired multipliers`
103
104			`p1ya <=((GRAD_WIDTH-1 downto (8+4) => '0') & pData1 & (4-1 downto 0 => '0'));`
105			`p1yb <=(others=>'0');`
106
107			`p2ya <=((GRAD_WIDTH-1 downto (8+6) => '0') & pData2 & (6-1 downto 0 => '0')) +`
108			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData2 & (4-1 downto 0 => '0'));`
109			`p2yb <=((GRAD_WIDTH-1 downto (8+2) => '0') & pData2 & (2-1 downto 0 => '0'));`
110
111			`p3ya <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData3 & (8-1 downto 0 => '0')) +`
112			`((GRAD_WIDTH-1 downto (8+5) => '0') & pData3 & (5-1 downto 0 => '0'));`
113			`p3yb <=((GRAD_WIDTH-1 downto (8+3) => '0') & pData3 & (3-1 downto 0 => '0'));`
114
115			`p4ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData4 & (9-1 downto 0 => '0')) +`
116			`((GRAD_WIDTH-1 downto (8+6) => '0') & pData4 & (6-1 downto 0 => '0'));`
117			`p4yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData4 & (5-1 downto 0 => '0')) +`
118			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData4 & (4-1 downto 0 => '0')) +`
119			`((GRAD_WIDTH-1 downto (8+1) => '0') & pData4 & (1-1 downto 0 => '0'));`
120
121			`p5ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData5 & (9-1 downto 0 => '0')) +`
122			`((GRAD_WIDTH-1 downto (8+8) => '0') & pData5 & (8-1 downto 0 => '0'));`
123			`p5yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData5 & (5-1 downto 0 => '0')) +`
124			`((GRAD_WIDTH-1 downto (8+2) => '0') & pData5 & (2-1 downto 0 => '0'));`
125
126			`p6ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData6 & (9-1 downto 0 => '0')) +`
127			`((GRAD_WIDTH-1 downto (8+6) => '0') & pData6 & (6-1 downto 0 => '0'));`
128			`p6yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData6 & (5-1 downto 0 => '0')) +`
129			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData6 & (4-1 downto 0 => '0')) +`
130			`((GRAD_WIDTH-1 downto (8+1) => '0') & pData6 & (1-1 downto 0 => '0'));`
131
132			`p7ya <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData7 & (8-1 downto 0 => '0')) +`
133			`((GRAD_WIDTH-1 downto (8+5) => '0') & pData7 & (5-1 downto 0 => '0'));`
134			`p7yb <=((GRAD_WIDTH-1 downto (8+3) => '0') & pData7 & (3-1 downto 0 => '0'));`
135
136			`p8ya <=((GRAD_WIDTH-1 downto (8+6) => '0') & pData8 & (6-1 downto 0 => '0')) +`
137			`((GRAD_WIDTH-1 downto (8+4) => '0') & pData8 & (4-1 downto 0 => '0'));`
138			`p8yb <=((GRAD_WIDTH-1 downto (8+2) => '0') & pData8 & (2-1 downto 0 => '0'));`
139
140			`p9ya <=((GRAD_WIDTH-1 downto (8+4) => '0') & pData9 & (4-1 downto 0 => '0'));`
141			`p9yb <=(others=>'0');`
142			`end if;`
143			`end if;`
144			`end process prod1;`
145
146			`--2----------------------------------------`
147			`prod2 : process (clk) -- for the frame sync signal`
148			`begin`
149			`if rising_edge(clk) then`
150			`if fsync ='1' then`
151			`p1x <= p1xa + p1xb;`
152			`p2x <= p2xa + p2xb;`
153			`p3x <= p3xa + p3xb;`
154			`p4x <= p4xa + p4xb;`
155			`p5x <= p5xa + p5xb;`
156			`p6x <= p6xa + p6xb;`
157			`p7x <= p7xa + p7xb;`
158			`p8x <= p8xa + p8xb;`
159			`p9x <= p9xa + p9xb;`
160			`--`
161			`p1y <= p1ya + p1yb;`
162			`p2y <= p2ya + p2yb;`
163			`p3y <= p3ya + p3yb;`
164			`p4y <= p4ya + p4yb;`
165			`p5y <= p5ya + p5yb;`
166			`p6y <= p6ya + p6yb;`
167			`p7y <= p7ya + p7yb;`
168			`p8y <= p8ya + p8yb;`
169			`p9y <= p9ya + p9yb;`
170			`end if;`
171			`end if;`
172			`end process prod2;`
173
174			`--3----------------------------------------`
175			`sum1 : process (clk)`
176			`begin`
177			`if rising_edge(clk) then`
178			`if fsync ='1' then`
179			`--sX1a <= p5x; ----DEBUG-----------`
180			`sX1a <= p1x+p2x;`
181			`sX1b <= p3x+p4x;`
182			`sX2a <= p6x+p7x;`
183			`sX2b <= p8x+p9x;`
184			`sY1a <= p1y+p2y;`
185			`sY1b <= p3y+p4y;`
186			`sY2a <= p5y+p6y;`
187			`sY2b <= p7y+p8y+p9y;`
188			`end if;`
189			`end if;`
190			`end process sum1;`
191
192			`--4----------------------------------------`
193			`sum2 : process (clk)`
194			`begin`
195			`if rising_edge(clk) then`
196			`if fsync ='1' then`
197			`--sX1 <= sX1a; ----DEBUG-----------`
198			`sX1 <= sX1a+sX1b;`
199			`sX2 <= sX2a+sX2b;`
200			`sY1 <= sY1a+sY1b;`
201			`sY2 <= sY2a+sY2b;`
202			`end if;`
203			`end if;`
204			`end process sum2;`
205
206			`--5----------------------------------------`
207			`sum3 : process (clk)`
208			`begin`
209			`if rising_edge(clk) then`
210			`if fsync ='1' then`
211			`sX2c <= (not sX2) + 1;`
212			`sX1c <= sX1;`
213			`sYc <= sY1+sY2;`
214			`end if;`
215			`end if;`
216			`end process sum3;`
217
218			`--6----------------------------------------`
219			`outp : process (clk)`
220			`begin`
221			`if rising_edge(clk) then`
222			`if fsync ='1' then`
223			`--Xdata_o <= sX1c; -------DEBUG-------`
224			`Xdata_o <= sX1c+sX2c;`
225			`Ydata_o <= (not sYc) + 1;`
226			`end if;`
227			`end if;`
228			`end process outp;`
229
230			`end Behavioral;`