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[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [ninerowsbuffer.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity nineFiFOLineBuffer is
  generic (
        DATA_WIDTH : integer := 8;
        NO_OF_COLS : integer := 640
        );
  port(
    clk : in std_logic;
        fsync : in std_logic;
        pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out4 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out5 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out6 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out7 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out8 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out9 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
        );
  end nineFiFOLineBuffer;
 
architecture Behavioral of nineFiFOLineBuffer is
 
signal pdata_in_r : std_logic_vector(DATA_WIDTH -1 downto 0);
 
component FIFOLineBuffer is
  generic (
        DATA_WIDTH : integer := DATA_WIDTH;
        NO_OF_COLS : integer := 640
        );
  port(
        clk : in std_logic;
        fsync : in std_logic;
        pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
        );
  end component;
 
begin
 
  pdata_out1 <= pdata_in_r;
 
  update_reg : process (clk)
  begin
    if rising_edge(clk) then
        if fsync = '1' then
          pdata_in_r <= pdata_in;
        end if;
        end if;
  end process update_reg;
 
  LineBuffer1 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_in_r, pdata_out2);
 
  LineBuffer2 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_out2, pdata_out3);
 
    LineBuffer3 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_out3, pdata_out4);
 
  LineBuffer4 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_out4, pdata_out5);
 
  LineBuffer5 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_out5, pdata_out6);
 
  LineBuffer6 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_out6, pdata_out7);
 
  LineBuffer7 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_out7, pdata_out8);
 
  LineBuffer8 : FIFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map(clk, fsync, pdata_out8, pdata_out9);
 
 
 
end Behavioral;

Line No.	Rev	Author	Line
1	2	angelobacc	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3
4			`entity nineFiFOLineBuffer is`
5			`generic (`
6			`DATA_WIDTH : integer := 8;`
7			`NO_OF_COLS : integer := 640`
8			`);`
9			`port(`
10			`clk : in std_logic;`
11			`fsync : in std_logic;`
12			`pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);`
13			`pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);`
14			`pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
15			`pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
16			`pdata_out4 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
17			`pdata_out5 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
18			`pdata_out6 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
19			`pdata_out7 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
20			`pdata_out8 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
21			`pdata_out9 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)`
22			`);`
23			`end nineFiFOLineBuffer;`
24
25			`architecture Behavioral of nineFiFOLineBuffer is`
26
27			`signal pdata_in_r : std_logic_vector(DATA_WIDTH -1 downto 0);`
28
29			`component FIFOLineBuffer is`
30			`generic (`
31			`DATA_WIDTH : integer := DATA_WIDTH;`
32			`NO_OF_COLS : integer := 640`
33			`);`
34			`port(`
35			`clk : in std_logic;`
36			`fsync : in std_logic;`
37			`pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);`
38			`pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0)`
39			`);`
40			`end component;`
41
42			`begin`
43
44			`pdata_out1 <= pdata_in_r;`
45
46			`update_reg : process (clk)`
47			`begin`
48			`if rising_edge(clk) then`
49			`if fsync = '1' then`
50			`pdata_in_r <= pdata_in;`
51			`end if;`
52			`end if;`
53			`end process update_reg;`
54
55			`LineBuffer1 : FIFOLineBuffer`
56			`generic map (`
57			`DATA_WIDTH => DATA_WIDTH,`
58			`NO_OF_COLS => NO_OF_COLS`
59			`)`
60			`port map(clk, fsync, pdata_in_r, pdata_out2);`
61
62			`LineBuffer2 : FIFOLineBuffer`
63			`generic map (`
64			`DATA_WIDTH => DATA_WIDTH,`
65			`NO_OF_COLS => NO_OF_COLS`
66			`)`
67			`port map(clk, fsync, pdata_out2, pdata_out3);`
68
69			`LineBuffer3 : FIFOLineBuffer`
70			`generic map (`
71			`DATA_WIDTH => DATA_WIDTH,`
72			`NO_OF_COLS => NO_OF_COLS`
73			`)`
74			`port map(clk, fsync, pdata_out3, pdata_out4);`
75
76			`LineBuffer4 : FIFOLineBuffer`
77			`generic map (`
78			`DATA_WIDTH => DATA_WIDTH,`
79			`NO_OF_COLS => NO_OF_COLS`
80			`)`
81			`port map(clk, fsync, pdata_out4, pdata_out5);`
82
83			`LineBuffer5 : FIFOLineBuffer`
84			`generic map (`
85			`DATA_WIDTH => DATA_WIDTH,`
86			`NO_OF_COLS => NO_OF_COLS`
87			`)`
88			`port map(clk, fsync, pdata_out5, pdata_out6);`
89
90			`LineBuffer6 : FIFOLineBuffer`
91			`generic map (`
92			`DATA_WIDTH => DATA_WIDTH,`
93			`NO_OF_COLS => NO_OF_COLS`
94			`)`
95			`port map(clk, fsync, pdata_out6, pdata_out7);`
96
97			`LineBuffer7 : FIFOLineBuffer`
98			`generic map (`
99			`DATA_WIDTH => DATA_WIDTH,`
100			`NO_OF_COLS => NO_OF_COLS`
101			`)`
102			`port map(clk, fsync, pdata_out7, pdata_out8);`
103
104			`LineBuffer8 : FIFOLineBuffer`
105			`generic map (`
106			`DATA_WIDTH => DATA_WIDTH,`
107			`NO_OF_COLS => NO_OF_COLS`
108			`)`
109			`port map(clk, fsync, pdata_out8, pdata_out9);`
110
111
112
113			`end Behavioral;`

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[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [ninerowsbuffer.vhd] - Blame information for rev 2