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[/] [cavlc/] [trunk/] [bench/] [cavlc_tb.v] - Blame information for rev 7

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1 7 qiubin 
//2011-8-12  initial version
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`include "defines.v"
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module cavlc_tb;
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//------------------------------------------------
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// task : read inputs(nC, rbsp, max_coff_num)
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//------------------------------------------------
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reg     [0:1023]    rbsp_data;
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reg     [7:0]  ch;
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integer fp_r, fp_w;
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integer rbsp_length;
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integer rbsp_offset;
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integer i;
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reg     signed  [5:0]   nC_t;
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reg     [4:0]   max_coeff_num_t;
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task read_test_data;
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//format
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//AA BB CCC DDD.......
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//AA:   nC
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//BB:   max_coeff_num
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//CCC:  length of D
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//DD... rbsp bits
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    begin
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        //nC_t
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        ch  = $fgetc(fp_r);
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        if (ch == 8'h2d)
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        begin
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            nC_t = -1;
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            ch = $fgetc(fp_r);
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            ch = $fgetc(fp_r);
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        end
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        else
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        begin
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            nC_t = ch - 8'h30;
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            ch  = $fgetc(fp_r);
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            if (ch != 8'h20)
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            begin
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                nC_t = nC_t * 10 + ch -8'h30;
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            end
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            ch = $fgetc(fp_r);
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        end
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        //max_coeff_num
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        ch  = $fgetc(fp_r);
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        max_coeff_num_t =  ch -8'h30;
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        ch  = $fgetc(fp_r);
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        if (ch != 8'h20)
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        begin
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            max_coeff_num_t = max_coeff_num_t * 10 + ch -8'h30;
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        end
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        ch  = $fgetc(fp_r);
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        //rbsp_length
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        ch  = $fgetc(fp_r);
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        rbsp_length = ch -8'h30;
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        ch  = $fgetc(fp_r);
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        if (ch != 8'h20)
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        begin
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            rbsp_length = rbsp_length * 10 + ch -8'h30;
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        end
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        ch  = $fgetc(fp_r);
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        if (ch != 8'h20)
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        begin
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            rbsp_length = rbsp_length * 10 + ch -8'h30;
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        end
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        ch  = $fgetc(fp_r);
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        //rbsp
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        rbsp_data = 0;
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        for(i = 0; i < rbsp_length; i = i+1)
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        begin
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            ch  = $fgetc(fp_r);
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            if (ch == 8'h30)
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                rbsp_data[i] = 1'b0;
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            else if (ch == 8'h31)
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                rbsp_data[i] = 1'b1;
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            else
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                $display("rbsp error!\n");
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        end
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        ch  = $fgetc(fp_r);
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    end
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endtask
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//-----------------------------------------------------------------------------
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// dut
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//-----------------------------------------------------------------------------
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reg     clk;
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reg             rst_n;
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reg     ena;
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reg     start;
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reg     [0:15]  rbsp;
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reg     signed  [5:0]   nC;
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reg     [4:0]   max_coeff_num;
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wire signed [8:0]   coeff_0;
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wire signed [8:0]   coeff_1;
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wire signed [8:0]   coeff_2;
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wire signed [8:0]   coeff_3;
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wire signed [8:0]   coeff_4;
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wire signed [8:0]   coeff_5;
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wire signed [8:0]   coeff_6;
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wire signed [8:0]   coeff_7;
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wire signed [8:0]   coeff_8;
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wire signed [8:0]   coeff_9;
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wire signed [8:0]   coeff_10;
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wire signed [8:0]   coeff_11;
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wire signed [8:0]   coeff_12;
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wire signed [8:0]   coeff_13;
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wire signed [8:0]   coeff_14;
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wire signed [8:0]   coeff_15;
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wire    [4:0]   TotalCoeff;
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wire    [4:0]   len_comb;
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wire    idle;
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wire    valid;
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cavlc_top dut(
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    clk,
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    rst_n,
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    ena,
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    start,
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    rbsp,
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    nC,
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    max_coeff_num,
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    coeff_0,
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    coeff_1,
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    coeff_2,
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    coeff_3,
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    coeff_4,
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    coeff_5,
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    coeff_6,
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    coeff_7,
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    coeff_8,
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    coeff_9,
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    coeff_10,
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    coeff_11,
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    coeff_12,
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    coeff_13,
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    coeff_14,
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    coeff_15,
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    TotalCoeff,
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    len_comb,
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    idle,
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    valid
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);
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parameter
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        Tp = 3,
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        TestBlockNum = 1000;    //number of cavlc blocks to test
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//-----------------------------------------------------------------------------
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// clock and reset
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//-----------------------------------------------------------------------------
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initial
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begin
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        clk = 0;
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        rst_n = 1;
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        # 10 rst_n = 0;
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        repeat(2) @(posedge clk);
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        rst_n = #5 1;
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end
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initial
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forever #10 clk = ~clk;
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//-----------------------------------------------------------------------------
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// generate module enable signal
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//-----------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n)
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if (!rst_n)
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    ena  <= #Tp 0;
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else
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    ena  <= #Tp 1; // always 1, or use {$random} % 2;
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//-----------------------------------------------------------------------------
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// generate start signal
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//-----------------------------------------------------------------------------
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initial
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begin
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   start = 0;
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   @(negedge rst_n);
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   @(posedge rst_n);
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   forever
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   begin
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      @(posedge clk);
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      start = 1;
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      @(posedge clk);
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      start = #Tp 0;   //start must be high for one cycle
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      @(posedge valid);
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   end
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end
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//-----------------------------------------------------------------------------
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// generate rbsp data and deal with forward_len
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//-----------------------------------------------------------------------------
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always @(*) rbsp <= # Tp rbsp_data[rbsp_offset +: 16];
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always @(posedge clk or negedge rst_n)
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if (!rst_n)
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    rbsp_offset <=  0;
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else if (!idle && ena)
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    rbsp_offset <=  rbsp_offset + len_comb;
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else if(ena)
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    rbsp_offset <=  0;
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//-----------------------------------------------------------------------------
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// generate inputs(nC, max_coff_num) from 'in.txt' and display output to 'out.txt'
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//-----------------------------------------------------------------------------
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integer blk_num;
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initial
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begin
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    fp_r = $fopen("in.txt", "r");
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    fp_w = $fopen("out.txt", "w");
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    if (fp_r == 0 || fp_w == 0)
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    begin
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        $display(" >> can not open 'in.txt' or 'out.txt'");
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        $finish;
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    end
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    blk_num = 0;
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    while(blk_num < TestBlockNum)
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    begin
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        if ($feof(fp_r) == 1)
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        begin
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                $fclose(fp_r);
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                $fclose(fp_w);
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                $display(" >> end of file @ %d", $time);
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                $finish;
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        end
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        read_test_data;
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        nC =  nC_t;
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        max_coeff_num =  max_coeff_num_t;
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        @(posedge valid);
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        blk_num = blk_num + 1;
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        @(posedge clk);
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        $fdisplay(fp_w, "blk_num:%-5dnC:%-5dTotalCoeff:%-5d", blk_num, nC, TotalCoeff);
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        $fdisplay(fp_w, "%5d%5d%5d%5d", coeff_0, coeff_1, coeff_2, coeff_3);
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        $fdisplay(fp_w, "%5d%5d%5d%5d", coeff_4, coeff_5, coeff_6, coeff_7);
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        $fdisplay(fp_w, "%5d%5d%5d%5d", coeff_8, coeff_9, coeff_10, coeff_11);
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        $fdisplay(fp_w, "%5d%5d%5d%5d\n", coeff_12, coeff_13, coeff_14, coeff_15);
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    end
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   $fclose(fp_r);
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   $fclose(fp_w);
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   $display(" >> done @ %d", $time);
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   $display(" >> tested cavlc blocks : %d", blk_num);
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   $finish;
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end
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endmodule

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