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[/] [cavlc/] [trunk/] [rtl/] [cavlc_read_total_zeros.v] - Blame information for rev 7

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1 7 qiubin
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  cavlc_read_total_zeros                                      ////
4
////                                                              ////
5
////  Description                                                 ////
6
////       decode total_zeros                                     ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - bin qiu, qiubin@opencores.org                         ////
10
////                                                              ////
11
//////////////////////////////////////////////////////////////////////
12
////                                                              ////
13
//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
14
////                                                              ////
15
//// This source file may be used and distributed without         ////
16
//// restriction provided that this copyright statement is not    ////
17
//// removed from the file and that any derivative work contains  ////
18
//// the original copyright notice and the associated disclaimer. ////
19
////                                                              ////
20
//// This source file is free software; you can redistribute it   ////
21
//// and/or modify it under the terms of the GNU Lesser General   ////
22
//// Public License as published by the Free Software Foundation; ////
23
//// either version 2.1 of the License, or (at your option) any   ////
24
//// later version.                                               ////
25
////                                                              ////
26
//// This source is distributed in the hope that it will be       ////
27
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30
//// details.                                                     ////
31
////                                                              ////
32
//// You should have received a copy of the GNU Lesser General    ////
33
//// Public License along with this source; if not, download it   ////
34
//// from http://www.opencores.org/lgpl.shtml                     ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
 
38 6 qiubin
//2011-8-14 initial version
39
 
40
`include "defines.v"
41
 
42 7 qiubin
module cavlc_read_total_zeros
43
(
44
    ena,
45
    sel,
46
    chroma_DC_sel,
47
    rbsp,
48
    TotalCoeff,
49
    TotalZeros_comb,
50
    len_comb
51 6 qiubin
);
52
//------------------------
53
//ports
54
//------------------------
55 7 qiubin
input   ena;
56
input   sel;
57
input   chroma_DC_sel;
58
input   [0:8]   rbsp;
59
input   [3:0]   TotalCoeff;
60 6 qiubin
 
61 7 qiubin
output  [3:0]   TotalZeros_comb;
62
output  [3:0]   len_comb;
63 6 qiubin
 
64
//-------------------------
65
//rregs
66
//-------------------------
67 7 qiubin
reg     [3:0]   TotalZeros_comb;    //TotalZeros will be saved as ZeroLeft in module cavlc_read_run_befores 
68
reg     [3:0]   len_comb;
69 6 qiubin
 
70
 
71
//for  chroma_DC
72 7 qiubin
reg     [0:2]   rbsp_chroma_DC;
73
reg     [1:0]   TotalZeros_chroma_DC;
74
reg     [1:0]   len_chroma_DC;
75 6 qiubin
 
76
//for TotalCoeff <= 3
77 7 qiubin
reg     [0:8]   rbsp_LE3;
78
reg     [3:0]   TotalZeros_LE3;
79
reg     [3:0]   len_LE3;
80 6 qiubin
 
81
//for TotalCoeff > 3
82 7 qiubin
reg     [0:5]   rbsp_G3;
83
reg     [3:0]   TotalZeros_G3;
84
reg     [2:0]   len_G3;
85 6 qiubin
 
86
 
87
//----------------------------------------
88
//input mux
89
//----------------------------------------
90
always @(*)
91
if (ena && sel && chroma_DC_sel) begin
92 7 qiubin
    rbsp_chroma_DC  <= rbsp[0:2];
93
    rbsp_LE3        <= 'hffff;
94
    rbsp_G3         <= 'hffff;
95 6 qiubin
end
96
else if (ena && sel && TotalCoeff[3:2] == 2'b00) begin
97 7 qiubin
    rbsp_chroma_DC  <= 'hffff;
98
    rbsp_LE3        <= rbsp[0:8];
99
    rbsp_G3         <= 'hffff;
100 6 qiubin
end
101
else if (ena && sel)begin
102 7 qiubin
    rbsp_chroma_DC  <= 'hffff;
103
    rbsp_LE3        <= 'hffff;
104
    rbsp_G3         <= rbsp[0:5];
105 6 qiubin
end
106
else begin
107 7 qiubin
    rbsp_chroma_DC  <= 'hffff;
108
    rbsp_LE3        <= 'hffff;
109
    rbsp_G3         <= 'hffff;
110 6 qiubin
end
111
 
112
//----------------------------------------
113
//TotalZeros_chroma_DC & len_chroma_DC
114
//----------------------------------------
115
always @(*)
116
if ( TotalCoeff == 1 && rbsp_chroma_DC[0] ) begin
117 7 qiubin
    TotalZeros_chroma_DC    <= 0;
118
    len_chroma_DC           <= 1;
119 6 qiubin
end
120
else if ( TotalCoeff == 1 && rbsp_chroma_DC[1] ) begin
121 7 qiubin
    TotalZeros_chroma_DC    <= 1;
122
    len_chroma_DC           <= 2;
123 6 qiubin
end
124
else if ( TotalCoeff == 1 && rbsp_chroma_DC[2] ) begin
125 7 qiubin
    TotalZeros_chroma_DC    <= 2;
126
    len_chroma_DC           <= 3;
127 6 qiubin
end
128
else if ( TotalCoeff == 1 ) begin
129 7 qiubin
    TotalZeros_chroma_DC    <= 3;
130
    len_chroma_DC           <= 3;
131 6 qiubin
end
132
else if ( TotalCoeff == 2 && rbsp_chroma_DC[0] ) begin
133 7 qiubin
    TotalZeros_chroma_DC    <= 0;
134
    len_chroma_DC           <= 1;
135 6 qiubin
end
136
else if ( TotalCoeff == 2 && rbsp_chroma_DC[1] ) begin
137 7 qiubin
    TotalZeros_chroma_DC    <= 1;
138
    len_chroma_DC           <= 2;
139 6 qiubin
end
140
else if ( TotalCoeff == 2 ) begin
141 7 qiubin
    TotalZeros_chroma_DC    <= 2;
142
    len_chroma_DC           <= 2;
143 6 qiubin
end
144
else if ( rbsp_chroma_DC[0] ) begin
145 7 qiubin
    TotalZeros_chroma_DC    <= 0;
146
    len_chroma_DC           <= 1;
147 6 qiubin
end
148
else begin
149 7 qiubin
    TotalZeros_chroma_DC    <= 1;
150
    len_chroma_DC           <= 1;
151 6 qiubin
end
152
 
153
 
154
//---------------------------------
155
//TotalZeros_LE3 & len_LE3
156
//---------------------------------
157
always @(rbsp_LE3 or TotalCoeff)
158
case (TotalCoeff[1:0])
159
1 :begin
160 7 qiubin
    case(1'b1)
161
    rbsp_LE3[0] : begin
162
        TotalZeros_LE3  <= 0;
163
        len_LE3         <= 1;
164
    end
165
    rbsp_LE3[1] : begin
166
        len_LE3         <= 3;
167
        if (rbsp_LE3[2])
168
            TotalZeros_LE3  <= 1;
169
        else
170
            TotalZeros_LE3  <= 2;
171
    end
172
    rbsp_LE3[2] : begin
173
        len_LE3         <= 4;
174
        if (rbsp_LE3[3])
175
            TotalZeros_LE3  <= 3;
176
        else
177
            TotalZeros_LE3  <= 4;
178
    end
179
    rbsp_LE3[3] : begin
180
        len_LE3         <= 5;
181
        if (rbsp_LE3[4])
182
            TotalZeros_LE3  <= 5;
183
        else
184
            TotalZeros_LE3  <= 6;
185
    end
186
    rbsp_LE3[4] : begin
187
        len_LE3         <= 6;
188
        if (rbsp_LE3[5])
189
            TotalZeros_LE3  <= 7;
190
        else
191
            TotalZeros_LE3  <= 8;
192
    end
193
    rbsp_LE3[5] : begin
194
        len_LE3         <= 7;
195
        if (rbsp_LE3[6])
196
            TotalZeros_LE3  <= 9;
197
        else
198
            TotalZeros_LE3  <= 10;
199
    end
200
    rbsp_LE3[6] : begin
201
        len_LE3         <= 8;
202
        if (rbsp_LE3[7])
203
            TotalZeros_LE3  <= 11;
204
        else
205
            TotalZeros_LE3  <= 12;
206
    end
207
    rbsp_LE3[7] : begin
208
        len_LE3         <= 9;
209
        if (rbsp_LE3[8])
210
            TotalZeros_LE3  <= 13;
211
        else
212
            TotalZeros_LE3  <= 14;
213
    end
214
    default : begin
215
        len_LE3         <= 9;
216
        TotalZeros_LE3  <= 15;
217
    end
218
    endcase
219 6 qiubin
end
220
2 : begin
221 7 qiubin
    case(1'b1)
222
    rbsp_LE3[0] : begin
223
        len_LE3 <= 3;
224
        case(rbsp_LE3[1:2])
225
        'b11 :  TotalZeros_LE3  <= 0;
226
        'b10 :  TotalZeros_LE3  <= 1;
227
        'b01 :  TotalZeros_LE3  <= 2;
228
        'b00 :  TotalZeros_LE3  <= 3;
229
        endcase
230
    end
231
    rbsp_LE3[1] : begin
232
        if (rbsp_LE3[2]) begin
233
            TotalZeros_LE3  <= 4;
234
            len_LE3         <= 3;
235
        end
236
        else begin
237
            len_LE3         <= 4;
238
            if (rbsp_LE3[3])
239
                TotalZeros_LE3  <= 5;
240
            else
241
                TotalZeros_LE3  <= 6;
242
        end
243
    end
244
    rbsp_LE3[2] : begin
245
        len_LE3         <= 4;
246
        if (rbsp_LE3[3])
247
            TotalZeros_LE3  <= 7;
248
        else
249
            TotalZeros_LE3  <= 8;
250
    end
251
    rbsp_LE3[3] : begin
252
        len_LE3         <= 5;
253
        if (rbsp_LE3[4])
254
            TotalZeros_LE3  <= 9;
255
        else
256
            TotalZeros_LE3  <= 10;
257
    end
258
    default : begin
259
        len_LE3 <= 6;
260
        case(rbsp_LE3[4:5])
261
        'b11 :  TotalZeros_LE3  <= 11;
262
        'b10 :  TotalZeros_LE3  <= 12;
263
        'b01 :  TotalZeros_LE3  <= 13;
264
        'b00 :  TotalZeros_LE3  <= 14;
265
        endcase
266
    end
267
    endcase
268 6 qiubin
end
269
3 : begin
270 7 qiubin
    case(1'b1)
271
    rbsp_LE3[0] : begin
272
        len_LE3 <= 3;
273
        case(rbsp_LE3[1:2])
274
        'b11 :  TotalZeros_LE3  <= 1;
275
        'b10 :  TotalZeros_LE3  <= 2;
276
        'b01 :  TotalZeros_LE3  <= 3;
277
        'b00 :  TotalZeros_LE3  <= 6;
278
        endcase
279
    end
280
    rbsp_LE3[1] : begin
281
        if (rbsp_LE3[2]) begin
282
            TotalZeros_LE3  <= 7;
283
            len_LE3         <= 3;
284
        end
285
        else begin
286
            len_LE3         <= 4;
287
            if (rbsp_LE3[3])
288
                TotalZeros_LE3  <= 0;
289
            else
290
                TotalZeros_LE3  <= 4;
291
        end
292
    end
293
    rbsp_LE3[2] : begin
294
        len_LE3         <= 4;
295
        if (rbsp_LE3[3])
296
            TotalZeros_LE3  <= 5;
297
        else
298
            TotalZeros_LE3  <= 8;
299
    end
300
    rbsp_LE3[3] : begin
301
        len_LE3         <= 5;
302
        if (rbsp_LE3[4])
303
            TotalZeros_LE3  <= 9;
304
        else
305
            TotalZeros_LE3  <= 10;
306
    end
307
    rbsp_LE3[4] : begin
308
        len_LE3         <= 5;
309
        TotalZeros_LE3  <= 12;
310
    end
311
    default : begin
312
        len_LE3 <= 6;
313
        if(rbsp_LE3[5])
314
            TotalZeros_LE3  <= 11;
315
        else
316
            TotalZeros_LE3  <= 13;
317
    end
318
    endcase
319 6 qiubin
end
320 7 qiubin
default : begin
321
    len_LE3         <= 'bx;
322
    TotalZeros_LE3  <= 'bx;
323 6 qiubin
end
324
endcase
325
 
326
//---------------------------------
327
//TotalZeros_G3 & len_G3
328
//---------------------------------
329
always @(rbsp_G3 or TotalCoeff)
330
case (TotalCoeff)
331
4 : begin
332 7 qiubin
    case(1'b1)
333
    rbsp_G3[0] : begin
334
        len_G3  <= 3;
335
        case(rbsp_G3[1:2])
336
        'b11 :  TotalZeros_G3   <= 1;
337
        'b10 :  TotalZeros_G3   <= 4;
338
        'b01 :  TotalZeros_G3   <= 5;
339
        'b00 :  TotalZeros_G3   <= 6;
340
        endcase
341
    end
342
    rbsp_G3[1] : begin
343
        if (rbsp_G3[2]) begin
344
            TotalZeros_G3   <= 8;
345
            len_G3          <= 3;
346
        end
347
        else begin
348
            len_G3          <= 4;
349
            if (rbsp_G3[3])
350
                TotalZeros_G3   <= 2;
351
            else
352
                TotalZeros_G3   <= 3;
353
        end
354
    end
355
    rbsp_G3[2] : begin
356
        len_G3          <= 4;
357
        if (rbsp_G3[3])
358
            TotalZeros_G3   <= 7;
359
        else
360
            TotalZeros_G3   <= 9;
361
    end
362
    default : begin
363
        len_G3  <= 5;
364
        case(rbsp_G3[3:4])
365
        'b11 :  TotalZeros_G3   <= 0;
366
        'b10 :  TotalZeros_G3   <= 10;
367
        'b01 :  TotalZeros_G3   <= 11;
368
        'b00 :  TotalZeros_G3   <= 12;
369
        endcase
370
    end
371
    endcase
372 6 qiubin
end
373
5 :begin
374 7 qiubin
    case(1'b1)
375
    rbsp_G3[0] : begin
376
        len_G3  <= 3;
377
        case(rbsp_G3[1:2])
378
        'b11 :  TotalZeros_G3   <= 3;
379
        'b10 :  TotalZeros_G3   <= 4;
380
        'b01 :  TotalZeros_G3   <= 5;
381
        'b00 :  TotalZeros_G3   <= 6;
382
        endcase
383
    end
384
    rbsp_G3[1] : begin
385
        if (rbsp_G3[2]) begin
386
            TotalZeros_G3   <= 7;
387
            len_G3          <= 3;
388
        end
389
        else begin
390
            len_G3          <= 4;
391
            if (rbsp_G3[3])
392
                TotalZeros_G3   <= 0;
393
            else
394
                TotalZeros_G3   <= 1;
395
        end
396
    end
397
    rbsp_G3[2] : begin
398
        len_G3          <= 4;
399
        if (rbsp_G3[3])
400
            TotalZeros_G3   <= 2;
401
        else
402
            TotalZeros_G3   <= 8;
403
    end
404
    rbsp_G3[3] : begin
405
        len_G3          <= 4;
406
        TotalZeros_G3   <= 10;
407
    end
408
    default : begin
409
        len_G3  <= 5;
410
        if (rbsp_G3[4])
411
            TotalZeros_G3   <= 9;
412
        else
413
            TotalZeros_G3   <= 11;
414
    end
415
    endcase
416 6 qiubin
end
417
6 : begin
418 7 qiubin
    case(1'b1)
419
    rbsp_G3[0] : begin
420
        len_G3  <= 3;
421
        case(rbsp_G3[1:2])
422
        'b11 :  TotalZeros_G3   <= 2;
423
        'b10 :  TotalZeros_G3   <= 3;
424
        'b01 :  TotalZeros_G3   <= 4;
425
        'b00 :  TotalZeros_G3   <= 5;
426
        endcase
427
    end
428
    rbsp_G3[1] : begin
429
        len_G3          <= 3;
430
        if (rbsp_G3[2])
431
            TotalZeros_G3   <= 6;
432
        else
433
            TotalZeros_G3   <= 7;
434
    end
435
    rbsp_G3[2] : begin
436
        len_G3          <= 3;
437
        TotalZeros_G3   <= 9;
438
    end
439
    rbsp_G3[3] : begin
440
        len_G3          <= 4;
441
        TotalZeros_G3   <= 8;
442
    end
443
    rbsp_G3[4] : begin
444
        len_G3          <= 5;
445
        TotalZeros_G3   <= 1;
446
    end
447
    default : begin
448
        len_G3  <= 6;
449
        if (rbsp_G3[5])
450
            TotalZeros_G3   <= 0;
451
        else
452
            TotalZeros_G3   <= 10;
453
    end
454
    endcase
455 6 qiubin
end
456
7 :begin
457 7 qiubin
    case(1'b1)
458
    rbsp_G3[0] : begin
459
        if (rbsp_G3[1]) begin
460
            TotalZeros_G3   <= 5;
461
            len_G3          <= 2;
462
        end
463
        else begin
464
            len_G3          <= 3;
465
            if (rbsp_G3[2])
466
                TotalZeros_G3   <= 2;
467
            else
468
                TotalZeros_G3   <= 3;
469
        end
470
    end
471
    rbsp_G3[1] : begin
472
        len_G3  <= 3;
473
        if (rbsp_G3[2])
474
            TotalZeros_G3   <= 4;
475
        else
476
            TotalZeros_G3   <= 6;
477
    end
478
    rbsp_G3[2] : begin
479
        len_G3          <= 3;
480
        TotalZeros_G3   <= 8;
481
    end
482
    rbsp_G3[3] : begin
483
        len_G3          <= 4;
484
        TotalZeros_G3   <= 7;
485
    end
486
    rbsp_G3[4] : begin
487
        len_G3          <= 5;
488
        TotalZeros_G3   <= 1;
489
    end
490
    default : begin
491
        len_G3          <= 6;
492
        if (rbsp_G3[5])
493
            TotalZeros_G3   <= 0;
494
        else
495
            TotalZeros_G3   <= 9;
496
    end
497
    endcase
498 6 qiubin
end
499
8 :begin
500 7 qiubin
    case(1'b1)
501
    rbsp_G3[0] : begin
502
        len_G3          <= 2;
503
        if (rbsp_G3[1])
504
            TotalZeros_G3   <= 4;
505
        else
506
            TotalZeros_G3   <= 5;
507
    end
508
    rbsp_G3[1] : begin
509
        len_G3          <= 3;
510
        if (rbsp_G3[2])
511
            TotalZeros_G3   <= 3;
512
        else
513
            TotalZeros_G3   <= 6;
514
    end
515
    rbsp_G3[2] : begin
516
        len_G3          <= 3;
517
        TotalZeros_G3   <= 7;
518
    end
519
    rbsp_G3[3] : begin
520
        len_G3          <= 4;
521
        TotalZeros_G3   <= 1;
522
    end
523
    rbsp_G3[4] : begin
524
        len_G3          <= 5;
525
        TotalZeros_G3   <= 2;
526
    end
527
    default : begin
528
        len_G3          <= 6;
529
        if (rbsp_G3[5])
530
            TotalZeros_G3   <= 0;
531
        else
532
            TotalZeros_G3   <= 8;
533
    end
534
    endcase
535 6 qiubin
end
536
9 : begin
537 7 qiubin
    case(1'b1)
538
    rbsp_G3[0] : begin
539
        len_G3          <= 2;
540
        if (rbsp_G3[1])
541
            TotalZeros_G3   <= 3;
542
        else
543
            TotalZeros_G3   <= 4;
544
    end
545
    rbsp_G3[1] : begin
546
        len_G3          <= 2;
547
        TotalZeros_G3   <= 6;
548
    end
549
    rbsp_G3[2] : begin
550
        len_G3          <= 3;
551
        TotalZeros_G3   <= 5;
552
    end
553
    rbsp_G3[3] : begin
554
        len_G3          <= 4;
555
        TotalZeros_G3   <= 2;
556
    end
557
    rbsp_G3[4] : begin
558
        len_G3          <= 5;
559
        TotalZeros_G3   <= 7;
560
    end
561
    default : begin
562
        len_G3          <= 6;
563
        if (rbsp_G3[5])
564
            TotalZeros_G3   <= 0;
565
        else
566
            TotalZeros_G3   <= 1;
567
    end
568
    endcase
569 6 qiubin
end
570
10 : begin
571 7 qiubin
    case(1'b1)
572
    rbsp_G3[0] : begin
573
        len_G3          <= 2;
574
        if (rbsp_G3[1])
575
            TotalZeros_G3   <= 3;
576
        else
577
            TotalZeros_G3   <= 4;
578
    end
579
    rbsp_G3[1] : begin
580
        len_G3          <= 2;
581
        TotalZeros_G3   <= 5;
582
    end
583
    rbsp_G3[2] : begin
584
        len_G3          <= 3;
585
        TotalZeros_G3   <= 2;
586
    end
587
    rbsp_G3[3] : begin
588
        len_G3          <= 4;
589
        TotalZeros_G3   <= 6;
590
    end
591
    default : begin
592
        len_G3          <= 5;
593
        if (rbsp_G3[4])
594
            TotalZeros_G3   <= 0;
595
        else
596
            TotalZeros_G3   <= 1;
597
    end
598
    endcase
599 6 qiubin
end
600
11 : begin
601 7 qiubin
    case(1'b1)
602
    rbsp_G3[0] : begin
603
        len_G3          <= 1;
604
        TotalZeros_G3   <= 4;
605
    end
606
    rbsp_G3[1] : begin
607
        len_G3          <= 3;
608
        if (rbsp_G3[2])
609
            TotalZeros_G3   <= 5;
610
        else
611
            TotalZeros_G3   <= 3;
612
    end
613
    rbsp_G3[2] : begin
614
        len_G3          <= 3;
615
        TotalZeros_G3   <= 2;
616
    end
617
    default : begin
618
        len_G3          <= 4;
619
        if (rbsp_G3[3])
620
            TotalZeros_G3   <= 1;
621
        else
622
            TotalZeros_G3   <= 0;
623
    end
624
    endcase
625 6 qiubin
end
626
12 : begin
627 7 qiubin
    case(1'b1)
628
    rbsp_G3[0] : begin
629
        len_G3          <= 1;
630
        TotalZeros_G3   <= 3;
631
    end
632
    rbsp_G3[1] : begin
633
        len_G3          <= 2;
634
        TotalZeros_G3   <= 2;
635
    end
636
    rbsp_G3[2] : begin
637
        len_G3          <= 3;
638
        TotalZeros_G3   <= 4;
639
    end
640
    default : begin
641
        len_G3          <= 4;
642
        if (rbsp_G3[3])
643
            TotalZeros_G3   <= 1;
644
        else
645
            TotalZeros_G3   <= 0;
646
    end
647
    endcase
648 6 qiubin
end
649 7 qiubin
13  :begin
650
    if (rbsp_G3[0]) begin
651
        TotalZeros_G3   <= 2;
652
        len_G3          <= 1;
653
    end
654
    else if (rbsp_G3[1]) begin
655
        TotalZeros_G3   <= 3;
656
        len_G3          <= 2;
657
    end
658
    else if (rbsp_G3[2]) begin
659
        TotalZeros_G3   <= 1;
660
        len_G3          <= 3;
661
    end
662
    else begin
663
        TotalZeros_G3   <= 0;
664
        len_G3          <= 3;
665
    end
666 6 qiubin
end
667 7 qiubin
14  : begin
668
    if (rbsp_G3[0]) begin
669
        TotalZeros_G3   <= 2;
670
        len_G3          <= 1;
671
    end
672
    else if (rbsp_G3[1]) begin
673
        TotalZeros_G3   <= 1;
674
        len_G3          <= 2;
675
    end
676
    else begin
677
        TotalZeros_G3   <= 0;
678
        len_G3          <= 2;
679
    end
680 6 qiubin
end
681 7 qiubin
15  : begin
682
    len_G3  <= 1;
683
    if (rbsp_G3[0])
684
        TotalZeros_G3   <= 1;
685
    else
686
        TotalZeros_G3   <= 0;
687 6 qiubin
end
688 7 qiubin
default : begin
689
    len_G3          <= 'bx;
690
    TotalZeros_G3   <= 'bx;
691 6 qiubin
end
692
endcase
693
 
694
//---------------------------------
695
//TotalZeros_comb & len_comb
696
//---------------------------------
697
always @(*)
698
if (ena && sel && chroma_DC_sel) begin
699 7 qiubin
    TotalZeros_comb     <= TotalZeros_chroma_DC;
700
    len_comb            <= len_chroma_DC;
701 6 qiubin
end
702
else if (ena && sel && TotalCoeff[3:2] == 2'b00) begin
703 7 qiubin
    TotalZeros_comb     <= TotalZeros_LE3;
704
    len_comb            <= len_LE3;
705 6 qiubin
end
706
else if (ena && sel)begin
707 7 qiubin
    TotalZeros_comb     <= TotalZeros_G3;
708
    len_comb            <= len_G3;
709 6 qiubin
end
710
else begin
711 7 qiubin
    TotalZeros_comb     <= 0;
712
    len_comb            <= 0;
713 6 qiubin
end
714
 
715
 
716
endmodule

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