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zguig52 |
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---- Project: EurySPACE CCSDS RX/TX with wishbone interface
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---- Design Name: ccsds_rxtx_lfsr
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---- Version: 1.0.0
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---- Description:
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---- Linear Feedback Shift Register
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---- Input: none
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---- Timing requirements: CCSDS_RXTX_LFSR_DATA_BUS_SIZE+1 clock cycles for valid output data
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---- Output: dat_val_o <= "1" / dat_o <= "LFSRSEQUENCE"
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---- Ressources requirements: TODO
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-------------------------------
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---- Author(s):
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---- Guillaume REMBERT
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-------------------------------
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---- Licence:
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---- MIT
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-------------------------------
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---- Changes list:
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---- 2016/11/05: initial release
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-------------------------------
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-- Test ressources:
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-- GNURADIO GLFSR block
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-- CCSDS parameters
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-- Width = 8
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-- Mode = Fibonacci ('0')
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-- Polynomial = x"A9"
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-- Seed = x"FF"
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-- Result = "1111111101001000000011101100000010011010"
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-- Width = 8
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-- Mode = Galois ('1')
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-- Polynomial = x"A9"
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-- Seed = x"FF"
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-- Result = "101001011011000001011000110110"
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-- libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--=============================================================================
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-- Entity declaration for ccsds_tx / unitary tx randomizer inputs and outputs
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--=============================================================================
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entity ccsds_rxtx_lfsr is
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generic(
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constant CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer; -- in bits
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constant CCSDS_RXTX_LFSR_MEMORY_SIZE: integer range 2 to 256 := 8; -- in bits
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constant CCSDS_RXTX_LFSR_MODE: std_logic := '0'; -- 0: Fibonacci / 1: Galois
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constant CCSDS_RXTX_LFSR_POLYNOMIAL: std_logic_vector := x"A9"; -- Polynomial / MSB <=> lower polynome (needs to be '1')
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constant CCSDS_RXTX_LFSR_SEED: std_logic_vector := x"FF" -- Initial Value
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);
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port(
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-- inputs
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clk_i: in std_logic;
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rst_i: in std_logic;
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-- outputs
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dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
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dat_val_o: out std_logic
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);
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end ccsds_rxtx_lfsr;
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--=============================================================================
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-- architecture declaration / internal components and connections
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--=============================================================================
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architecture structure of ccsds_rxtx_lfsr is
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-- internal constants
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-- internal variable signals
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signal lfsr_memory: std_logic_vector(CCSDS_RXTX_LFSR_MEMORY_SIZE-1 downto 0) := CCSDS_RXTX_LFSR_SEED;
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-- components instanciation and mapping
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begin
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-- presynthesis checks
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CHKLFSRP0 : if CCSDS_RXTX_LFSR_POLYNOMIAL'length /= CCSDS_RXTX_LFSR_MEMORY_SIZE generate
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process
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begin
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report "ERROR: LFSR_POLYNOMIAL LENGTH MUST BE EQUAL TO MEMORY SIZE (SHORTENED VERSION / DON'T PUT MANDATORY HIGHER POLYNOME '1')" severity failure;
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wait;
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end process;
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end generate CHKLFSRP0;
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CHKLFSRP1 : if CCSDS_RXTX_LFSR_MEMORY_SIZE <= 1 generate
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process
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begin
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report "ERROR: LFSR_MEMORY_SIZE MUST BE BIGGER THAN 1" severity failure;
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wait;
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end process;
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end generate CHKLFSRP1;
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CHKLFSRP2 : if CCSDS_RXTX_LFSR_SEED'length /= CCSDS_RXTX_LFSR_MEMORY_SIZE generate
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process
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begin
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report "ERROR: LFSR_SEED LENGTH MUST BE EQUAL TO LFSR_MEMORY_SIZE" severity failure;
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wait;
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end process;
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end generate CHKLFSRP2;
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CHKLFSRP3 : if CCSDS_RXTX_LFSR_POLYNOMIAL(CCSDS_RXTX_LFSR_MEMORY_SIZE-1) = '0' generate
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process
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begin
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report "ERROR: LFSR POLYNOMIAL MSB MUST BE EQUAL TO 1" severity failure;
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wait;
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end process;
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end generate CHKLFSRP3;
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-- internal processing
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--=============================================================================
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-- Begin of crcp
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-- Compute CRC based on input data
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--=============================================================================
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-- read: rst_i
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-- write: dat_o, dat_val_o
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-- r/w: lfsr_memory
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LFSRP: process (clk_i)
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variable output_pointer: integer range -1 to (CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1) := CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1;
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variable feedback_register: std_logic := '0';
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begin
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-- on each clock rising edge
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if rising_edge(clk_i) then
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-- reset signal received
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if (rst_i = '1') then
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lfsr_memory <= CCSDS_RXTX_LFSR_SEED;
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dat_o <= (others => '0');
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dat_val_o <= '0';
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output_pointer := CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1;
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feedback_register := '0';
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else
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-- generation is finished
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if (output_pointer = -1) then
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dat_val_o <= '1';
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-- generating sequence
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else
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dat_val_o <= '0';
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-- Fibonacci
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if (CCSDS_RXTX_LFSR_MODE = '0') then
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dat_o(output_pointer) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
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output_pointer := output_pointer - 1;
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feedback_register := lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
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for i in 0 to CCSDS_RXTX_LFSR_MEMORY_SIZE-2 loop
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if (CCSDS_RXTX_LFSR_POLYNOMIAL(i) = '1') then
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feedback_register := feedback_register xor lfsr_memory(i);
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end if;
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end loop;
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lfsr_memory <= std_logic_vector(resize(unsigned(lfsr_memory),CCSDS_RXTX_LFSR_MEMORY_SIZE-1)) & feedback_register;
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-- Galois
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else
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dat_o(output_pointer) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
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output_pointer := output_pointer - 1;
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lfsr_memory(0) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
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for i in 1 to CCSDS_RXTX_LFSR_MEMORY_SIZE-1 loop
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if (CCSDS_RXTX_LFSR_POLYNOMIAL(i) = '1') then
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lfsr_memory(i) <= lfsr_memory(i-1) xor lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
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else
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lfsr_memory(i) <= lfsr_memory(i-1);
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end if;
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end loop;
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end if;
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end if;
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end if;
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end if;
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end process;
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end structure;
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