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zguig52 |
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---- Project: EurySPACE CCSDS RX/TX with wishbone interface
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---- Design Name: ccsds_rxtx_oversampler
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---- Version: 1.0.0
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---- Description:
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---- Insert OSR-1 '0' between symbols
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-------------------------------
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---- Author(s):
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---- Guillaume REMBERT
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-------------------------------
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---- Licence:
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---- MIT
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-------------------------------
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---- Changes list:
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---- 2016/11/06: initial release
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-------------------------------
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-- libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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--=============================================================================
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-- Entity declaration for ccsds_tx / unitary rxtx oversampler inputs and outputs
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--=============================================================================
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entity ccsds_rxtx_oversampler is
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generic(
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constant CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer := 4;
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constant CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: boolean := false;
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constant CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
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);
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port(
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-- inputs
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clk_i: in std_logic;
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rst_i: in std_logic;
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sam_i: in std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
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sam_val_i: in std_logic;
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-- outputs
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sam_o: out std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
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sam_val_o: out std_logic
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);
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end ccsds_rxtx_oversampler;
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--=============================================================================
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-- architecture declaration / internal components and connections
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--=============================================================================
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architecture structure of ccsds_rxtx_oversampler is
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-- internal constants
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-- internal variable signals
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-- components instanciation and mapping
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begin
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-- presynthesis checks
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CHKOVERSAMPLERP0 : if (CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO mod 2 /= 0) generate
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process
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begin
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report "ERROR: OVERSAMPLING RATIO HAS TO BE A MULTIPLE OF 2" severity failure;
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wait;
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end process;
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end generate CHKOVERSAMPLERP0;
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CHKOVERSAMPLERP1 : if (CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO = 0) generate
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process
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begin
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report "ERROR: OVERSAMPLING RATIO CANNOT BE 0" severity failure;
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wait;
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end process;
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end generate CHKOVERSAMPLERP1;
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-- internal processing
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--=============================================================================
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-- Begin of osrp
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-- Insert all 0 samples
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--=============================================================================
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-- read: rst_i, sam_i
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-- write: sam_o
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-- r/w:
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OSRP: process (clk_i)
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variable samples_counter: integer range 0 to CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1 := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
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begin
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-- on each clock rising edge
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if rising_edge(clk_i) then
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-- reset signal received
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if (rst_i = '1') then
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sam_o <= (others => '0');
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samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
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else
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if (sam_val_i = '1') then
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sam_val_o <= '1';
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if (CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING = true) then
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if (samples_counter <= 0) then
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sam_o <= (others => '0');
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samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
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else
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if (samples_counter = CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO/2) then
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sam_o <= sam_i;
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else
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sam_o <= (others => '0');
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end if;
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samples_counter := samples_counter - 1;
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end if;
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else
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if (samples_counter <= 0) then
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sam_o <= sam_i;
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samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
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else
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sam_o <= (others => '0');
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samples_counter := samples_counter - 1;
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end if;
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end if;
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else
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sam_val_o <= '0';
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end if;
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end if;
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end if;
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end process;
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end structure;
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