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zguig52 |
---- Design Name: ccsds_tx_coder_differential
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---- Version: 1.0.0
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---- Description:
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---- Word by word differential coder
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-------------------------------
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---- Author(s):
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---- Guillaume REMBERT
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-------------------------------
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---- Licence:
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---- MIT
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-------------------------------
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---- Changes list:
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---- 2016/11/18: initial release
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-------------------------------
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-- libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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--=============================================================================
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-- Entity declaration for ccsds_tx / unitary tx differential coder inputs and outputs
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--=============================================================================
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entity ccsds_tx_coder_differential is
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generic(
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constant CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
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constant CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer -- in bits
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);
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port(
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-- inputs
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clk_i: in std_logic;
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dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
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dat_val_i: in std_logic;
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rst_i: in std_logic;
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-- outputs
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dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
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dat_val_o: out std_logic
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);
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end ccsds_tx_coder_differential;
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--=============================================================================
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-- architecture declaration / internal components and connections
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--=============================================================================
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architecture rtl of ccsds_tx_coder_differential is
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-- internal constants
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-- internal variable signals
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-- components instanciation and mapping
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begin
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-- presynthesis checks
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CHKCODERP0 : if (CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE mod (CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) /= 0) generate
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process
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begin
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report "ERROR: DATA BUS SIZE HAS TO BE A MULTIPLE OF BITS PER CODE WORD" severity failure;
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wait;
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end process;
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end generate CHKCODERP0;
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-- internal processing
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--=============================================================================
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-- Begin of coderdiffp
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-- Differential encode words
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--=============================================================================
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-- read: rst_i, dat_i, dat_val_i
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-- write: dat_o, dat_val_o
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-- r/w:
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CODERDIFFP: process (clk_i)
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variable prev_sym: std_logic_vector(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto 0) := (others => '0');
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begin
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-- on each clock rising edge
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if rising_edge(clk_i) then
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-- reset signal received
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if (rst_i = '1') then
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dat_o <= (others => '0');
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dat_val_o <= '0';
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prev_sym := (others => '0');
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else
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if (dat_val_i = '1') then
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dat_val_o <= '1';
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dat_o(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) <= prev_sym xor dat_i(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD);
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for i in CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE/(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD)-1 downto 1 loop
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dat_o(i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto (i-1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) <= dat_i(i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto (i-1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) xor dat_i((i+1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD);
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end loop;
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prev_sym := dat_i(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto 0);
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else
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dat_val_o <= '0';
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end if;
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end if;
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end if;
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end process;
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end rtl;
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