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<META NAME="KEYWORDS" CONTENT="start">
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<META NAME="date" CONTENT="2008-01-08T12:01:41-0500">
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<BODY LANG="en-US" DIR="LTR">
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<DIV ID="toc__header" DIR="LTR">
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<H1><A NAME="socgen ip"></A>CDE LIBRARY:
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</H1>
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<P>The Common Design Environment (CDE) is a library of verilog IP
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modules for use in fpga and asic designs. One problem that we face
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is that not all rtl code is synthesisable into all target processes.
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The CDE project seeks to identify this problem code and provide
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documented and functioning models for each case. A CDE module will
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isolate the problem code inside a single module that can be easily
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replaced when the design is targeted to a process that requires
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substitution of custom hard macros. This can be done without
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touching the users rtl code so that a single code base can support
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both fpga and asic targets without modification.</P>
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<P><BR><BR>
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</P>
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<P>CDE is part of the SOCEN design environment and uses IP-Xact
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module descriptors. Documention is autogenerated and uses the gEDA
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tool set.
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</P>
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<P><BR><BR>
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</P>
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<P><BR><BR>
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</P>
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<P><BR><BR>
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</P>
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<P><BR><BR>
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</P>
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</DIV>
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<DIV ID="toc__inside" DIR="LTR">
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<UL>
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<LI><P STYLE="margin-bottom: 0in"><A HREF="#IPModules">IP Modules</A></P>
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<UL>
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<LI><P><A HREF="../ip/pad/doc/html/component.html">IO Pads</A></P>
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<LI><P><A HREF="../ip/sram/doc/html/component.html">Synchronous
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Rams</A></P>
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</UL>
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</UL>
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</DIV>
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<P><BR><BR>
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</P>
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