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[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_se_dig.xml] - Blame information for rev 2

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
pad
se_dig
 
 
 

 
 pad_ring
  
  
  
    
      
        PAD_io
        PAD
       
      
 
    
 
 
 
 
 pad
  
  
  
    
      
        pad_out
        pad_out
        
      
      
        pad_oe
        pad_oe
      
      
        pad_in
        pad_in
         
      
 
    
 
 

 
 
 
 
 

       
 
              
              sim*simulation*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn*synthesis*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              *documentation*
              Verilog
              
 
 
 
      
 
 

WIDTH1

 
 

 
PAD
wire
inout
WIDTH-10

 
pad_in
wire
out
WIDTH-10

 
pad_out
wire
in
WIDTH-10

 
pad_oe
wire
in

 
 
 
 
 

 

 
 
 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 
 
 


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[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_se_dig.xml] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`se_dig`
16
17
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19
20
21			`pad_ring`
22
23
24
25
26
27			`PAD_io`
28			`PAD`
29
30
31
32
33
34
35
36
37			`pad`
38
39
40
41
42
43			`pad_out`
44			`pad_out`
45
46
47
48			`pad_oe`
49			`pad_oe`
50
51
52			`pad_in`
53			`pad_in`
54
55
56
57
58
59
60
61
62
63
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65
66
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68
69
70			`simsimulation`
71			`Verilog`
72
73
74			`fs-sim`
75
76
77
78
79			`synsynthesis`
80			`Verilog`
81
82
83			`fs-syn`
84
85
86
87
88
89			`doc`
90
91
92			`spirit:library="Testbench"`
93			`spirit:name="toolflow"`
94			`spirit:version="documentation"/>`
95
96			`documentation`
97			`Verilog`
98
99
100
101
102
103
104
105
106			`WIDTH1`
107
108
109
110
111
112			`PAD`
113			`wire`
114			`inout`
115			`WIDTH-10`
116
117
118			`pad_in`
119			`wire`
120			`out`
121			`WIDTH-10`
122
123
124			`pad_out`
125			`wire`
126			`in`
127			`WIDTH-10`
128
129
130			`pad_oe`
131			`wire`
132			`in`
133
134
135
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142
143
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145
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147
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149
150
151
152
153			`fs-sim`
154
155
156
157			`dest_dir`
158			`../verilog/`
159			`verilogSourcelibraryDir`
160
161
162
163
164
165
166			`fs-syn`
167
168
169			`dest_dir`
170			`../verilog/`
171			`verilogSourcelibraryDir`
172
173
174
175
176
177
178
179
180
181			`fs-lint`
182
183			`dest_dir`
184			`../verilog/`
185			`verilogSourcelibraryDir`
186
187
188
189
190
191
192
193
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195
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