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Subversion Repositories cde

[/] [cde/] [trunk/] [ip/] [sram/] [doc/] [sch/] [sram_timing.sch] - Blame information for rev 2

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Line No. Rev Author Line
1 2 jt_eaton 
v 20121203 2
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B 2800 600 4300 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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addr
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T 3100 3000 9 10 1 0 0 0 1
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clk
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T 3200 2400 9 10 1 0 0 0 1
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cs
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T 3200 2100 9 10 1 0 0 0 1
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wr
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T 3200 1800 9 10 1 0 0 0 1
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rd
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be
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T 3000 1200 9 10 1 0 0 0 1
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wdata
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rdata
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L 3600 3000 3700 3000 3 0 1 0 -1 -1
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L 3700 3000 3800 3200 3 0 1 0 -1 -1
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L 3800 3200 4100 3200 3 0 1 0 -1 -1
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L 4200 3000 4500 3000 3 0 1 0 -1 -1
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L 4600 3200 4900 3200 3 0 1 0 -1 -1
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L 5300 3000 5400 3200 3 0 1 0 -1 -1
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L 5400 3200 5700 3200 3 0 1 0 -1 -1
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L 5700 3200 5800 3000 3 0 1 0 -1 -1
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L 5800 3000 6100 3000 3 0 1 0 -1 -1
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L 6100 3000 6200 3200 3 0 1 0 -1 -1
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L 6200 3200 6500 3200 3 0 1 0 -1 -1
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L 3600 2700 4500 2700 3 0 1 0 -1 -1
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L 4500 2700 4600 2900 3 0 1 0 -1 -1
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L 4600 2900 5300 2900 3 0 1 0 -1 -1
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L 5300 2900 5400 2700 3 0 1 0 -1 -1
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L 5400 2700 6500 2700 3 0 1 0 -1 -1
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L 3600 2900 4500 2900 3 0 1 0 -1 -1
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L 4500 2900 4600 2700 3 0 1 0 -1 -1
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L 4600 2700 5300 2700 3 0 1 0 -1 -1
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L 5300 2700 5400 2900 3 0 1 0 -1 -1
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L 5400 2900 6500 2900 3 0 1 0 -1 -1
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L 3600 2400 4500 2400 3 0 1 0 -1 -1
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L 4500 2400 4600 2600 3 0 1 0 -1 -1
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L 4600 2600 5300 2600 3 0 1 0 -1 -1
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L 5300 2600 5400 2400 3 0 1 0 -1 -1
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L 5400 2400 6500 2400 3 0 1 0 -1 -1
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L 3600 2100 4500 2100 3 0 1 0 -1 -1
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L 4500 2100 4600 2300 3 0 1 0 -1 -1
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L 4600 2300 5300 2300 3 0 1 0 -1 -1
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L 5300 2300 5400 2100 3 0 1 0 -1 -1
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L 5400 2100 6500 2100 3 0 1 0 -1 -1
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L 3600 1800 4500 1800 3 0 1 0 -1 -1
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L 4500 1800 4600 2000 3 0 1 0 -1 -1
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L 4600 2000 5300 2000 3 0 1 0 -1 -1
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L 5300 2000 5400 1800 3 0 1 0 -1 -1
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L 5400 1800 6500 1800 3 0 1 0 -1 -1
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L 3600 1500 4500 1500 3 0 1 0 -1 -1
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L 4500 1500 4600 1700 3 0 1 0 -1 -1
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L 4600 1700 5300 1700 3 0 1 0 -1 -1
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L 5300 1700 5400 1500 3 0 1 0 -1 -1
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L 5400 1500 6500 1500 3 0 1 0 -1 -1
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L 3600 1200 4500 1200 3 0 1 0 -1 -1
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L 4500 1200 4600 1400 3 0 1 0 -1 -1
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L 4600 1400 5300 1400 3 0 1 0 -1 -1
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L 5300 1400 5400 1200 3 0 1 0 -1 -1
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L 5400 1200 6500 1200 3 0 1 0 -1 -1
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L 3600 1400 4500 1400 3 0 1 0 -1 -1
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L 4500 1400 4600 1200 3 0 1 0 -1 -1
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L 4600 1200 5300 1200 3 0 1 0 -1 -1
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L 5300 1200 5400 1400 3 0 1 0 -1 -1
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L 5400 1400 6500 1400 3 0 1 0 -1 -1
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L 3600 900 5300 900 3 0 1 0 -1 -1
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L 5300 900 5400 1100 3 0 1 0 -1 -1
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L 5400 1100 6100 1100 3 0 1 0 -1 -1
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L 6100 1100 6200 900 3 0 1 0 -1 -1
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L 6200 900 6500 900 3 0 1 0 -1 -1
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L 3600 1100 5300 1100 3 0 1 0 -1 -1
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L 5300 1100 5400 900 3 0 1 0 -1 -1
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L 5400 900 6100 900 3 0 1 0 -1 -1
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L 6100 900 6200 1100 3 0 1 0 -1 -1
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L 6200 1100 6500 1100 3 0 1 0 -1 -1
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T 4720 2740 9 10 1 0 0 0 1
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valid
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T 4730 1250 9 10 1 0 0 0 1
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valid
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