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[/] [cfft/] [tags/] [arelease/] [src/] [address.vhd] - Blame information for rev 15

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---------------------------------------------------------------------------------------------------
--
-- Title       : address
-- Design      : cfft
-- Author      : ZHAO Ming
-- email           : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File        : address.vhd
-- Generated   : Thu Oct  3 01:44:47 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : Generate RAM read write address and start finish control signal
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    1
-- Version         :    1.1.0
-- Date            :    Oct 17 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Data width configurable 
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    2
-- Version         :    1.2.0
-- Date            :    Oct 18 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Data width configurable 
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    1
-- Revision Number :    2
-- Version         :    1.2.1
-- Date            :    Oct 19 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    modified fuction counter2address for syn        
--                                              add rmask1,rmask2,wmask1,wmask2 signal
--
---------------------------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_signed.all;
 
entity address is
        generic (
                WIDTH : Natural;
                POINT : Natural;
                STAGE : Natural
        );
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 Iin : in std_logic_vector( WIDTH-1 downto 0 );
                 Qin : in std_logic_vector( WIDTH-1 downto 0 );
                 fftI : in std_logic_vector( WIDTH-1 downto 0 );
                 fftQ : in std_logic_vector( WIDTH-1 downto 0 );
                 wdataI : out std_logic_vector( WIDTH-1 downto 0 );
                 wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
                 raddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
                 waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
                 wen : out std_logic;
                 factorstart : out STD_LOGIC;
                 cfft4start : out STD_LOGIC;
                 outdataen : out std_logic;
                 inputbusy : out std_logic
             );
end address;
 
 
architecture address of address is
 
 
--      function counter2addr(counter : std_logic_vector; state:std_logic_vector) return std_logic_vector is
--      variable result :std_logic_vector(counter'range);
--      variable istate : Natural;
--      begin                                     
--              istate:=CONV_INTEGER(unsigned(state));
--              if istate=0     then
--                      result := counter( 1 downto 0 )&counter( counter'high downto 2 );
--              elsif istate=(counter'high-1)/2 then
--                      result := counter;
--              elsif istate<(counter'high-1)/2 then
--                      result := counter( counter'high downto counter'high-istate*2+1 )&counter( 1 downto 0 )&counter( counter'high-istate*2 downto 2 );
--              else
--                      result := counter;
--              end if;
--              return result;
--      end counter2addr;
 
        function counter2addr(
                counter : std_logic_vector;
                mask1:std_logic_vector;
                mask2:std_logic_vector
        ) return std_logic_vector is
        variable result :std_logic_vector(counter'range);
        begin
                for n in mask1'range loop
                        if mask1(n)='1' then
                                result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
                        elsif mask2(n)='1' and n/=STAGE-1 then
                                result( 2*n+1 downto 2*n ):=counter( 2*n+3 downto 2*n+2 );
                        else
                                result( 2*n+1 downto 2*n ):=counter( 2*n+1 downto 2*n );
                        end if;
                end loop;
                return result;
        end counter2addr;
 
 
signal rstate,wstate,state:std_logic_vector( 3 downto 0 );
signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );
signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );
signal outcounter:std_logic_vector( STAGE*2 downto 0 );
 
constant FFTDELAY:integer:=12+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=7;
 
 
 
begin
outdataen<=outcounter(STAGE*2);
 
count:process( clk, rst )
begin
        if rst='1' then
                counter<=( others=>'0' );
                state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);
        elsif clk'event and clk='1' then
                if start='1' then
                        counter<=( others=>'0' );
                        state<=(others=>'0');
                elsif unsigned(state)/=STAGE+1 then
                        counter<=unsigned(counter)+1;
                        if signed(counter)=-1 then
                                state<=unsigned(state)+1;
                        end if;
                end if;
        end if;
end process count;
 
readaddr:process( clk,rst )
begin
        if rst='1' then
                raddr<=( others=>'0' );
                rcounter<=( others=>'0' );
                rstate<=( others=>'0' );
                rmask1<=( others=>'0' );
                rmask2<=( others=>'0' );
        elsif clk'event and clk='1' then
                if unsigned(state)=0 and signed(counter)=-1 then
                        rmask1(STAGE-1)<='1';
                        rmask1(STAGE-2 downto 0)<=(others=>'0');
                        rmask2(STAGE-1)<='0';
                        rmask2(STAGE-2 downto 0)<=(others=>'1');
                elsif signed(counter)=-1 then
                        rmask1<='0'&rmask1( STAGE-1 downto 1 );
                        rmask2<='0'&rmask2( STAGE-1 downto 1 );
                end if;
                if unsigned(state)/=STAGE+1 and signed(counter)=-1 then
                        rcounter<=( others=>'0' );
                        rstate<=state;
                else
                        rcounter<=unsigned(rcounter)+1;
                end if;
                raddr<=counter2addr( rcounter, rmask1, rmask2 );
--              modified for point configurable
--              case rstate is
--                      when "000" =>
--                      raddr<=rcounter( 1 downto 0 )&rcounter( 9 downto 2);
--                      when "001" =>
--                      raddr<=rcounter( 9 downto 8 )&rcounter( 1 downto 0 )&rcounter( 7 downto 2);
--                      when "010" =>
--                      raddr<=rcounter( 9 downto 6 )&rcounter( 1 downto 0 )&rcounter( 5 downto 2);
--                      when "011" =>
--                      raddr<=rcounter( 9 downto 4 )&rcounter( 1 downto 0 )&rcounter( 3 downto 2);
--                      when "100" =>
--                      raddr<=rcounter( 9 downto 2 )&rcounter( 1 downto 0 );
--                      when others =>
--                      raddr<=( others=> '0' );
--              end case;
        end if;
end process readaddr;
 
writeaddr:process( clk,rst )
begin
        if rst='1' then
                waddr<=( others=>'0' );
                wcounter<=( others=>'0' );
                wstate<=( others=>'0' );
                wmask1<=( others=>'0' );
                wmask2<=( others=>'0' );
        elsif clk'event and clk='1' then
                if unsigned(state)=0 then
                        waddr<=counter;
                else
                        if UNSIGNED(rstate)=0 and unsigned(rcounter)=FFTDELAY-1 then
                                wmask1(STAGE-1)<='1';
                                wmask1(STAGE-2 downto 0)<=(others=>'0');
                                wmask2(STAGE-1)<='0';
                                wmask2(STAGE-2 downto 0)<=(others=>'1');
                        elsif unsigned(rcounter)=FFTDELAY-1 then
                                wmask1<='0'&wmask1( STAGE-1 downto 1 );
                                wmask2<='0'&wmask2( STAGE-1 downto 1 );
                        end if;
                        if UNSIGNED(rstate)<STAGE and unsigned(rcounter)=FFTDELAY-1 then
                                wcounter<=( others=>'0' );
                                wstate<=rstate;
                        else
                                wcounter<=unsigned(wcounter)+1;
                        end if;
                        waddr<=counter2addr( wcounter, wmask1, wmask2 );
--                      modified for point configurable
--                      case wstate is
--                              when "000" =>
--                              waddr<=wcounter( 1 downto 0 )&wcounter( 9 downto 2);
--                              when "001" =>
--                              waddr<=wcounter( 9 downto 8 )&wcounter( 1 downto 0 )&wcounter( 7 downto 2);
--                              when "010" =>
--                              waddr<=wcounter( 9 downto 6 )&wcounter( 1 downto 0 )&wcounter( 5 downto 2);
--                              when "011" =>
--                              waddr<=wcounter( 9 downto 4 )&wcounter( 1 downto 0 )&wcounter( 3 downto 2);
--                              when others =>
--                              waddr<=( others=> '0' );
--                      end case;
                end if;
        end if;
end process writeaddr;
 
writeen : process( clk, rst )
begin
        if rst='1' then
                wen<='0';
        elsif clk'event and clk='1' then
                if unsigned(state)=0 then
                        wen<='1';
                elsif unsigned(state)=1 and unsigned(counter)=0 then
                        wen<='0';
                elsif unsigned(rstate)=0 and unsigned(rcounter)=FFTDELAY then
                        wen<='1';
                elsif unsigned(rstate)=STAGE-1 and unsigned(rcounter)=FFTDELAY then
                        wen<='0';
                end if;
        end if;
end process writeen;
 
otherstart : process( clk, rst )
begin
        if rst='1' then
                factorstart<='0';
                cfft4start<='0';
                outcounter<=(others=>'0');
                inputbusy<='0';
        elsif clk'event and clk='1' then
                if start='1' then
                        inputbusy<='1';
                elsif unsigned(state)=STAGE and unsigned(counter)=FFTDELAY  then
                        inputbusy<='0';
                end if;
                if unsigned(state)=1 and unsigned(counter)=0 then
                        cfft4start<='1';
                else
                        cfft4start<='0';
                end if;
                if unsigned(rstate)=0 and unsigned(rcounter)=FACTORDELAY then
                        factorstart<='1';
                else
                        factorstart<='0';
                end if;
                if unsigned(state)=STAGE and unsigned(rcounter)=OUTDELAY then
                        outcounter<=CONV_STD_LOGIC_VECTOR(POINT,2*STAGE+1);
                elsif outcounter(STAGE*2)='1' then
                        outcounter<=unsigned(outcounter)+1;
                end if;
   end if;
end process otherstart;
 
datasel : process( clk,rst )
begin
        if rst='1' then
                wdataI<=( others=>'0' );
                wdataQ<=( others=>'0' );
        elsif clk'event and clk='1' then
                if unsigned(state)=0 then
                        wdataI<=Iin;
                        wdataQ<=Qin;
                else
                        wdataI<=fftI;
                        wdataQ<=fftQ;
                end if;
        end if;
end process datasel;
 
end address;

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Subversion Repositories cfft

[/] [cfft/] [tags/] [arelease/] [src/] [address.vhd] - Blame information for rev 15

Line No.	Rev	Author	Line
1	2	sradio	`---------------------------------------------------------------------------------------------------`
2			`--`
3			`-- Title : address`
4			`-- Design : cfft`
5			`-- Author : ZHAO Ming`
6			`-- email : sradio@opencores.org`
7			`--`
8			`---------------------------------------------------------------------------------------------------`
9			`--`
10			`-- File : address.vhd`
11			`-- Generated : Thu Oct 3 01:44:47 2002`
12			`--`
13			`---------------------------------------------------------------------------------------------------`
14			`--`
15			`-- Description : Generate RAM read write address and start finish control signal`
16			`--`
17			`---------------------------------------------------------------------------------------------------`
18			`--`
19			`-- Revisions : 0`
20			`-- Revision Number : 1`
21			`-- Version : 1.1.0`
22			`-- Date : Oct 17 2002`
23			`-- Modifier : ZHAO Ming`
24			`-- Desccription : Data width configurable`
25			`--`
26			`---------------------------------------------------------------------------------------------------`
27			`--`
28			`-- Revisions : 0`
29			`-- Revision Number : 2`
30			`-- Version : 1.2.0`
31			`-- Date : Oct 18 2002`
32			`-- Modifier : ZHAO Ming`
33			`-- Desccription : Data width configurable`
34			`--`
35			`---------------------------------------------------------------------------------------------------`
36			`--`
37			`-- Revisions : 1`
38			`-- Revision Number : 2`
39			`-- Version : 1.2.1`
40			`-- Date : Oct 19 2002`
41			`-- Modifier : ZHAO Ming`
42			`-- Desccription : modified fuction counter2address for syn`
43			`-- add rmask1,rmask2,wmask1,wmask2 signal`
44			`--`
45			`---------------------------------------------------------------------------------------------------`
46
47
48			`library IEEE;`
49			`use IEEE.STD_LOGIC_1164.all;`
50			`use IEEE.STD_LOGIC_ARITH.all;`
51			`use IEEE.std_logic_unsigned.all;`
52			`use IEEE.std_logic_signed.all;`
53
54			`entity address is`
55			`generic (`
56			`WIDTH : Natural;`
57			`POINT : Natural;`
58			`STAGE : Natural`
59			`);`
60			`port(`
61			`clk : in STD_LOGIC;`
62			`rst : in STD_LOGIC;`
63			`start : in STD_LOGIC;`
64			`Iin : in std_logic_vector( WIDTH-1 downto 0 );`
65			`Qin : in std_logic_vector( WIDTH-1 downto 0 );`
66			`fftI : in std_logic_vector( WIDTH-1 downto 0 );`
67			`fftQ : in std_logic_vector( WIDTH-1 downto 0 );`
68			`wdataI : out std_logic_vector( WIDTH-1 downto 0 );`
69			`wdataQ : out std_logic_vector( WIDTH-1 downto 0 );`
70			`raddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);`
71			`waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);`
72			`wen : out std_logic;`
73			`factorstart : out STD_LOGIC;`
74			`cfft4start : out STD_LOGIC;`
75			`outdataen : out std_logic;`
76			`inputbusy : out std_logic`
77			`);`
78			`end address;`
79
80
81			`architecture address of address is`
82
83
84			`-- function counter2addr(counter : std_logic_vector; state:std_logic_vector) return std_logic_vector is`
85			`-- variable result :std_logic_vector(counter'range);`
86			`-- variable istate : Natural;`
87			`-- begin`
88			`-- istate:=CONV_INTEGER(unsigned(state));`
89			`-- if istate=0 then`
90			`-- result := counter( 1 downto 0 )&counter( counter'high downto 2 );`
91			`-- elsif istate=(counter'high-1)/2 then`
92			`-- result := counter;`
93			`-- elsif istate<(counter'high-1)/2 then`
94			`-- result := counter( counter'high downto counter'high-istate2+1 )&counter( 1 downto 0 )&counter( counter'high-istate2 downto 2 );`
95			`-- else`
96			`-- result := counter;`
97			`-- end if;`
98			`-- return result;`
99			`-- end counter2addr;`
100
101			`function counter2addr(`
102			`counter : std_logic_vector;`
103			`mask1:std_logic_vector;`
104			`mask2:std_logic_vector`
105			`) return std_logic_vector is`
106			`variable result :std_logic_vector(counter'range);`
107			`begin`
108			`for n in mask1'range loop`
109			`if mask1(n)='1' then`
110			`result( 2n+1 downto 2n ):=counter( 1 downto 0 );`
111			`elsif mask2(n)='1' and n/=STAGE-1 then`
112			`result( 2n+1 downto 2n ):=counter( 2n+3 downto 2n+2 );`
113			`else`
114			`result( 2n+1 downto 2n ):=counter( 2n+1 downto 2n );`
115			`end if;`
116			`end loop;`
117			`return result;`
118			`end counter2addr;`
119
120
121			`signal rstate,wstate,state:std_logic_vector( 3 downto 0 );`
122			`signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );`
123			`signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );`
124			`signal outcounter:std_logic_vector( STAGE*2 downto 0 );`
125
126			`constant FFTDELAY:integer:=12+2*STAGE;`
127			`constant FACTORDELAY:integer:=6;`
128			`constant OUTDELAY:integer:=7;`
129
130
131
132			`begin`
133			`outdataen<=outcounter(STAGE*2);`
134
135			`count:process( clk, rst )`
136			`begin`
137			`if rst='1' then`
138			`counter<=( others=>'0' );`
139			`state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);`
140			`elsif clk'event and clk='1' then`
141			`if start='1' then`
142			`counter<=( others=>'0' );`
143			`state<=(others=>'0');`
144			`elsif unsigned(state)/=STAGE+1 then`
145			`counter<=unsigned(counter)+1;`
146			`if signed(counter)=-1 then`
147			`state<=unsigned(state)+1;`
148			`end if;`
149			`end if;`
150			`end if;`
151			`end process count;`
152
153			`readaddr:process( clk,rst )`
154			`begin`
155			`if rst='1' then`
156			`raddr<=( others=>'0' );`
157			`rcounter<=( others=>'0' );`
158			`rstate<=( others=>'0' );`
159			`rmask1<=( others=>'0' );`
160			`rmask2<=( others=>'0' );`
161			`elsif clk'event and clk='1' then`
162			`if unsigned(state)=0 and signed(counter)=-1 then`
163			`rmask1(STAGE-1)<='1';`
164			`rmask1(STAGE-2 downto 0)<=(others=>'0');`
165			`rmask2(STAGE-1)<='0';`
166			`rmask2(STAGE-2 downto 0)<=(others=>'1');`
167			`elsif signed(counter)=-1 then`
168			`rmask1<='0'&rmask1( STAGE-1 downto 1 );`
169			`rmask2<='0'&rmask2( STAGE-1 downto 1 );`
170			`end if;`
171			`if unsigned(state)/=STAGE+1 and signed(counter)=-1 then`
172			`rcounter<=( others=>'0' );`
173			`rstate<=state;`
174			`else`
175			`rcounter<=unsigned(rcounter)+1;`
176			`end if;`
177			`raddr<=counter2addr( rcounter, rmask1, rmask2 );`
178			`-- modified for point configurable`
179			`-- case rstate is`
180			`-- when "000" =>`
181			`-- raddr<=rcounter( 1 downto 0 )&rcounter( 9 downto 2);`
182			`-- when "001" =>`
183			`-- raddr<=rcounter( 9 downto 8 )&rcounter( 1 downto 0 )&rcounter( 7 downto 2);`
184			`-- when "010" =>`
185			`-- raddr<=rcounter( 9 downto 6 )&rcounter( 1 downto 0 )&rcounter( 5 downto 2);`
186			`-- when "011" =>`
187			`-- raddr<=rcounter( 9 downto 4 )&rcounter( 1 downto 0 )&rcounter( 3 downto 2);`
188			`-- when "100" =>`
189			`-- raddr<=rcounter( 9 downto 2 )&rcounter( 1 downto 0 );`
190			`-- when others =>`
191			`-- raddr<=( others=> '0' );`
192			`-- end case;`
193			`end if;`
194			`end process readaddr;`
195
196			`writeaddr:process( clk,rst )`
197			`begin`
198			`if rst='1' then`
199			`waddr<=( others=>'0' );`
200			`wcounter<=( others=>'0' );`
201			`wstate<=( others=>'0' );`
202			`wmask1<=( others=>'0' );`
203			`wmask2<=( others=>'0' );`
204			`elsif clk'event and clk='1' then`
205			`if unsigned(state)=0 then`
206			`waddr<=counter;`
207			`else`
208			`if UNSIGNED(rstate)=0 and unsigned(rcounter)=FFTDELAY-1 then`
209			`wmask1(STAGE-1)<='1';`
210			`wmask1(STAGE-2 downto 0)<=(others=>'0');`
211			`wmask2(STAGE-1)<='0';`
212			`wmask2(STAGE-2 downto 0)<=(others=>'1');`
213			`elsif unsigned(rcounter)=FFTDELAY-1 then`
214			`wmask1<='0'&wmask1( STAGE-1 downto 1 );`
215			`wmask2<='0'&wmask2( STAGE-1 downto 1 );`
216			`end if;`
217			`if UNSIGNED(rstate)<STAGE and unsigned(rcounter)=FFTDELAY-1 then`
218			`wcounter<=( others=>'0' );`
219			`wstate<=rstate;`
220			`else`
221			`wcounter<=unsigned(wcounter)+1;`
222			`end if;`
223			`waddr<=counter2addr( wcounter, wmask1, wmask2 );`
224			`-- modified for point configurable`
225			`-- case wstate is`
226			`-- when "000" =>`
227			`-- waddr<=wcounter( 1 downto 0 )&wcounter( 9 downto 2);`
228			`-- when "001" =>`
229			`-- waddr<=wcounter( 9 downto 8 )&wcounter( 1 downto 0 )&wcounter( 7 downto 2);`
230			`-- when "010" =>`
231			`-- waddr<=wcounter( 9 downto 6 )&wcounter( 1 downto 0 )&wcounter( 5 downto 2);`
232			`-- when "011" =>`
233			`-- waddr<=wcounter( 9 downto 4 )&wcounter( 1 downto 0 )&wcounter( 3 downto 2);`
234			`-- when others =>`
235			`-- waddr<=( others=> '0' );`
236			`-- end case;`
237			`end if;`
238			`end if;`
239			`end process writeaddr;`
240
241			`writeen : process( clk, rst )`
242			`begin`
243			`if rst='1' then`
244			`wen<='0';`
245			`elsif clk'event and clk='1' then`
246			`if unsigned(state)=0 then`
247			`wen<='1';`
248			`elsif unsigned(state)=1 and unsigned(counter)=0 then`
249			`wen<='0';`
250			`elsif unsigned(rstate)=0 and unsigned(rcounter)=FFTDELAY then`
251			`wen<='1';`
252			`elsif unsigned(rstate)=STAGE-1 and unsigned(rcounter)=FFTDELAY then`
253			`wen<='0';`
254			`end if;`
255			`end if;`
256			`end process writeen;`
257
258			`otherstart : process( clk, rst )`
259			`begin`
260			`if rst='1' then`
261			`factorstart<='0';`
262			`cfft4start<='0';`
263			`outcounter<=(others=>'0');`
264			`inputbusy<='0';`
265			`elsif clk'event and clk='1' then`
266			`if start='1' then`
267			`inputbusy<='1';`
268			`elsif unsigned(state)=STAGE and unsigned(counter)=FFTDELAY then`
269			`inputbusy<='0';`
270			`end if;`
271			`if unsigned(state)=1 and unsigned(counter)=0 then`
272			`cfft4start<='1';`
273			`else`
274			`cfft4start<='0';`
275			`end if;`
276			`if unsigned(rstate)=0 and unsigned(rcounter)=FACTORDELAY then`
277			`factorstart<='1';`
278			`else`
279			`factorstart<='0';`
280			`end if;`
281			`if unsigned(state)=STAGE and unsigned(rcounter)=OUTDELAY then`
282			`outcounter<=CONV_STD_LOGIC_VECTOR(POINT,2*STAGE+1);`
283			`elsif outcounter(STAGE*2)='1' then`
284			`outcounter<=unsigned(outcounter)+1;`
285			`end if;`
286			`end if;`
287			`end process otherstart;`
288
289			`datasel : process( clk,rst )`
290			`begin`
291			`if rst='1' then`
292			`wdataI<=( others=>'0' );`
293			`wdataQ<=( others=>'0' );`
294			`elsif clk'event and clk='1' then`
295			`if unsigned(state)=0 then`
296			`wdataI<=Iin;`
297			`wdataQ<=Qin;`
298			`else`
299			`wdataI<=fftI;`
300			`wdataQ<=fftQ;`
301			`end if;`
302			`end if;`
303			`end process datasel;`
304
305			`end address;`