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[/] [cfft/] [trunk/] [src/] [address.vhd] - Blame information for rev 14

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---------------------------------------------------------------------------------------------------
--
-- Title       : address
-- Design      : cfft
-- Author      : ZHAO Ming
-- email           : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File        : address.vhd
-- Generated   : Thu Oct  3 01:44:47 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : Generate RAM read write address and start finish control signal
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    1
-- Version         :    1.1.0
-- Date            :    Oct 17 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Data width configurable 
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    2
-- Version         :    1.2.0
-- Date            :    Oct 18 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Data width configurable 
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    1
-- Revision Number :    2
-- Version         :    1.2.1
-- Date            :    Oct 19 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    modified fuction counter2address for syn        
--                                              add rmask1,rmask2,wmask1,wmask2 signal
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    3
-- Version         :    1.3.0
-- Date            :    Nov 19 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    add output data position indication 
--                   
--
---------------------------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_signed.all;
 
entity address is
        generic (
                WIDTH : Natural;
                POINT : Natural;
                STAGE : Natural
        );
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 Iin : in std_logic_vector( WIDTH-1 downto 0 );
                 Qin : in std_logic_vector( WIDTH-1 downto 0 );
                 fftI : in std_logic_vector( WIDTH-1 downto 0 );
                 fftQ : in std_logic_vector( WIDTH-1 downto 0 );
                 wdataI : out std_logic_vector( WIDTH-1 downto 0 );
                 wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
                 raddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
                 waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
                 wen : out std_logic;
                 factorstart : out STD_LOGIC;
                 cfft4start : out STD_LOGIC;
                 outdataen : out std_logic;
                 inputbusy : out std_logic;
                 OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
             );
end address;
 
 
architecture address of address is
 
 
--      function counter2addr(counter : std_logic_vector; state:std_logic_vector) return std_logic_vector is
--      variable result :std_logic_vector(counter'range);
--      variable istate : Natural;
--      begin                                     
--              istate:=CONV_INTEGER(unsigned(state));
--              if istate=0     then
--                      result := counter( 1 downto 0 )&counter( counter'high downto 2 );
--              elsif istate=(counter'high-1)/2 then
--                      result := counter;
--              elsif istate<(counter'high-1)/2 then
--                      result := counter( counter'high downto counter'high-istate*2+1 )&counter( 1 downto 0 )&counter( counter'high-istate*2 downto 2 );
--              else
--                      result := counter;
--              end if;
--              return result;
--      end counter2addr;
 
        function counter2addr(
                counter : std_logic_vector;
                mask1:std_logic_vector;
                mask2:std_logic_vector
        ) return std_logic_vector is
        variable result :std_logic_vector(counter'range);
        begin
                for n in mask1'range loop
                        if mask1(n)='1' then
                                result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
                        elsif mask2(n)='1' and n/=STAGE-1 then
                                result( 2*n+1 downto 2*n ):=counter( 2*n+3 downto 2*n+2 );
                        else
                                result( 2*n+1 downto 2*n ):=counter( 2*n+1 downto 2*n );
                        end if;
                end loop;
                return result;
        end counter2addr;
 
        function outcounter2addr(
                counter : std_logic_vector
        ) return std_logic_vector is
        variable result :std_logic_vector(counter'range);
        begin
                for n in 0 to STAGE-1 loop
                        result( 2*n+1 downto 2*n ):=counter( counter'high-2*n downto counter'high-2*n-1 );
                end loop;
                return result;
        end outcounter2addr;
 
signal rstate,wstate,state:std_logic_vector( 3 downto 0 );
signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );
signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );
signal outcounter:std_logic_vector( STAGE*2 downto 0 );
 
constant FFTDELAY:integer:=12+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=7;
 
 
 
begin
outdataen<=outcounter(STAGE*2);
OutPosition<=outcounter2addr( outcounter( STAGE*2-1 downto 0 ));
count:process( clk, rst )
begin
        if rst='1' then
                counter<=( others=>'0' );
                state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);
        elsif clk'event and clk='1' then
                if start='1' then
                        counter<=( others=>'0' );
                        state<=(others=>'0');
                elsif unsigned(state)/=STAGE+1 then
                        counter<=unsigned(counter)+1;
                        if signed(counter)=-1 then
                                state<=unsigned(state)+1;
                        end if;
                end if;
        end if;
end process count;
 
readaddr:process( clk,rst )
begin
        if rst='1' then
                raddr<=( others=>'0' );
                rcounter<=( others=>'0' );
                rstate<=( others=>'0' );
                rmask1<=( others=>'0' );
                rmask2<=( others=>'0' );
        elsif clk'event and clk='1' then
                if unsigned(state)=0 and signed(counter)=-1 then
                        rmask1(STAGE-1)<='1';
                        rmask1(STAGE-2 downto 0)<=(others=>'0');
                        rmask2(STAGE-1)<='0';
                        rmask2(STAGE-2 downto 0)<=(others=>'1');
                elsif signed(counter)=-1 then
                        rmask1<='0'&rmask1( STAGE-1 downto 1 );
                        rmask2<='0'&rmask2( STAGE-1 downto 1 );
                end if;
                if unsigned(state)/=STAGE+1 and signed(counter)=-1 then
                        rcounter<=( others=>'0' );
                        rstate<=state;
                else
                        rcounter<=unsigned(rcounter)+1;
                end if;
                raddr<=counter2addr( rcounter, rmask1, rmask2 );
--              modified for point configurable
--              case rstate is
--                      when "000" =>
--                      raddr<=rcounter( 1 downto 0 )&rcounter( 9 downto 2);
--                      when "001" =>
--                      raddr<=rcounter( 9 downto 8 )&rcounter( 1 downto 0 )&rcounter( 7 downto 2);
--                      when "010" =>
--                      raddr<=rcounter( 9 downto 6 )&rcounter( 1 downto 0 )&rcounter( 5 downto 2);
--                      when "011" =>
--                      raddr<=rcounter( 9 downto 4 )&rcounter( 1 downto 0 )&rcounter( 3 downto 2);
--                      when "100" =>
--                      raddr<=rcounter( 9 downto 2 )&rcounter( 1 downto 0 );
--                      when others =>
--                      raddr<=( others=> '0' );
--              end case;
        end if;
end process readaddr;
 
writeaddr:process( clk,rst )
begin
        if rst='1' then
                waddr<=( others=>'0' );
                wcounter<=( others=>'0' );
                wstate<=( others=>'0' );
                wmask1<=( others=>'0' );
                wmask2<=( others=>'0' );
        elsif clk'event and clk='1' then
                if unsigned(state)=0 then
                        waddr<=counter;
                else
                        if UNSIGNED(rstate)=0 and unsigned(rcounter)=FFTDELAY-1 then
                                wmask1(STAGE-1)<='1';
                                wmask1(STAGE-2 downto 0)<=(others=>'0');
                                wmask2(STAGE-1)<='0';
                                wmask2(STAGE-2 downto 0)<=(others=>'1');
                        elsif unsigned(rcounter)=FFTDELAY-1 then
                                wmask1<='0'&wmask1( STAGE-1 downto 1 );
                                wmask2<='0'&wmask2( STAGE-1 downto 1 );
                        end if;
                        if UNSIGNED(rstate)<STAGE and unsigned(rcounter)=FFTDELAY-1 then
                                wcounter<=( others=>'0' );
                                wstate<=rstate;
                        else
                                wcounter<=unsigned(wcounter)+1;
                        end if;
                        waddr<=counter2addr( wcounter, wmask1, wmask2 );
--                      modified for point configurable
--                      case wstate is
--                              when "000" =>
--                              waddr<=wcounter( 1 downto 0 )&wcounter( 9 downto 2);
--                              when "001" =>
--                              waddr<=wcounter( 9 downto 8 )&wcounter( 1 downto 0 )&wcounter( 7 downto 2);
--                              when "010" =>
--                              waddr<=wcounter( 9 downto 6 )&wcounter( 1 downto 0 )&wcounter( 5 downto 2);
--                              when "011" =>
--                              waddr<=wcounter( 9 downto 4 )&wcounter( 1 downto 0 )&wcounter( 3 downto 2);
--                              when others =>
--                              waddr<=( others=> '0' );
--                      end case;
                end if;
        end if;
end process writeaddr;
 
writeen : process( clk, rst )
begin
        if rst='1' then
                wen<='0';
        elsif clk'event and clk='1' then
                if unsigned(state)=0 then
                        wen<='1';
                elsif unsigned(state)=1 and unsigned(counter)=0 then
                        wen<='0';
                elsif unsigned(rstate)=0 and unsigned(rcounter)=FFTDELAY then
                        wen<='1';
                elsif unsigned(rstate)=STAGE-1 and unsigned(rcounter)=FFTDELAY then
                        wen<='0';
                end if;
        end if;
end process writeen;
 
otherstart : process( clk, rst )
begin
        if rst='1' then
                factorstart<='0';
                cfft4start<='0';
                outcounter<=(others=>'0');
                inputbusy<='0';
        elsif clk'event and clk='1' then
                if start='1' then
                        inputbusy<='1';
                elsif unsigned(state)=STAGE and unsigned(counter)=FFTDELAY  then
                        inputbusy<='0';
                end if;
                if unsigned(state)=1 and unsigned(counter)=0 then
                        cfft4start<='1';
                else
                        cfft4start<='0';
                end if;
                if unsigned(rstate)=0 and unsigned(rcounter)=FACTORDELAY then
                        factorstart<='1';
                else
                        factorstart<='0';
                end if;
                if unsigned(state)=STAGE and unsigned(rcounter)=OUTDELAY then
                        outcounter<=CONV_STD_LOGIC_VECTOR(POINT,2*STAGE+1);
                elsif outcounter(STAGE*2)='1' then
                        outcounter<=unsigned(outcounter)+1;
                end if;
   end if;
end process otherstart;
 
datasel : process( clk,rst )
begin
        if rst='1' then
                wdataI<=( others=>'0' );
                wdataQ<=( others=>'0' );
        elsif clk'event and clk='1' then
                if unsigned(state)=0 then
                        wdataI<=Iin;
                        wdataQ<=Qin;
                else
                        wdataI<=fftI;
                        wdataQ<=fftQ;
                end if;
        end if;
end process datasel;
 
end address;

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Subversion Repositories cfft

[/] [cfft/] [trunk/] [src/] [address.vhd] - Blame information for rev 14

Line No.	Rev	Author	Line
1	2	sradio	`---------------------------------------------------------------------------------------------------`
2			`--`
3			`-- Title : address`
4			`-- Design : cfft`
5			`-- Author : ZHAO Ming`
6			`-- email : sradio@opencores.org`
7			`--`
8			`---------------------------------------------------------------------------------------------------`
9			`--`
10			`-- File : address.vhd`
11			`-- Generated : Thu Oct 3 01:44:47 2002`
12			`--`
13			`---------------------------------------------------------------------------------------------------`
14			`--`
15			`-- Description : Generate RAM read write address and start finish control signal`
16			`--`
17			`---------------------------------------------------------------------------------------------------`
18			`--`
19			`-- Revisions : 0`
20			`-- Revision Number : 1`
21			`-- Version : 1.1.0`
22			`-- Date : Oct 17 2002`
23			`-- Modifier : ZHAO Ming`
24			`-- Desccription : Data width configurable`
25			`--`
26			`---------------------------------------------------------------------------------------------------`
27			`--`
28			`-- Revisions : 0`
29			`-- Revision Number : 2`
30			`-- Version : 1.2.0`
31			`-- Date : Oct 18 2002`
32			`-- Modifier : ZHAO Ming`
33			`-- Desccription : Data width configurable`
34			`--`
35			`---------------------------------------------------------------------------------------------------`
36			`--`
37			`-- Revisions : 1`
38			`-- Revision Number : 2`
39			`-- Version : 1.2.1`
40			`-- Date : Oct 19 2002`
41			`-- Modifier : ZHAO Ming`
42			`-- Desccription : modified fuction counter2address for syn`
43			`-- add rmask1,rmask2,wmask1,wmask2 signal`
44			`--`
45			`---------------------------------------------------------------------------------------------------`
46	9	sradio	`--`
47			`-- Revisions : 0`
48			`-- Revision Number : 3`
49			`-- Version : 1.3.0`
50			`-- Date : Nov 19 2002`
51			`-- Modifier : ZHAO Ming`
52			`-- Desccription : add output data position indication`
53			`--`
54			`--`
55			`---------------------------------------------------------------------------------------------------`
56	2	sradio
57
58			`library IEEE;`
59			`use IEEE.STD_LOGIC_1164.all;`
60			`use IEEE.STD_LOGIC_ARITH.all;`
61			`use IEEE.std_logic_unsigned.all;`
62			`use IEEE.std_logic_signed.all;`
63
64			`entity address is`
65			`generic (`
66			`WIDTH : Natural;`
67			`POINT : Natural;`
68			`STAGE : Natural`
69			`);`
70			`port(`
71			`clk : in STD_LOGIC;`
72			`rst : in STD_LOGIC;`
73			`start : in STD_LOGIC;`
74			`Iin : in std_logic_vector( WIDTH-1 downto 0 );`
75			`Qin : in std_logic_vector( WIDTH-1 downto 0 );`
76			`fftI : in std_logic_vector( WIDTH-1 downto 0 );`
77			`fftQ : in std_logic_vector( WIDTH-1 downto 0 );`
78			`wdataI : out std_logic_vector( WIDTH-1 downto 0 );`
79			`wdataQ : out std_logic_vector( WIDTH-1 downto 0 );`
80			`raddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);`
81			`waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);`
82			`wen : out std_logic;`
83			`factorstart : out STD_LOGIC;`
84			`cfft4start : out STD_LOGIC;`
85			`outdataen : out std_logic;`
86	9	sradio	`inputbusy : out std_logic;`
87			`OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )`
88	2	sradio	`);`
89			`end address;`
90
91
92			`architecture address of address is`
93
94
95			`-- function counter2addr(counter : std_logic_vector; state:std_logic_vector) return std_logic_vector is`
96			`-- variable result :std_logic_vector(counter'range);`
97			`-- variable istate : Natural;`
98			`-- begin`
99			`-- istate:=CONV_INTEGER(unsigned(state));`
100			`-- if istate=0 then`
101			`-- result := counter( 1 downto 0 )&counter( counter'high downto 2 );`
102			`-- elsif istate=(counter'high-1)/2 then`
103			`-- result := counter;`
104			`-- elsif istate<(counter'high-1)/2 then`
105			`-- result := counter( counter'high downto counter'high-istate2+1 )&counter( 1 downto 0 )&counter( counter'high-istate2 downto 2 );`
106			`-- else`
107			`-- result := counter;`
108			`-- end if;`
109			`-- return result;`
110			`-- end counter2addr;`
111
112			`function counter2addr(`
113			`counter : std_logic_vector;`
114			`mask1:std_logic_vector;`
115			`mask2:std_logic_vector`
116			`) return std_logic_vector is`
117			`variable result :std_logic_vector(counter'range);`
118			`begin`
119			`for n in mask1'range loop`
120			`if mask1(n)='1' then`
121			`result( 2n+1 downto 2n ):=counter( 1 downto 0 );`
122			`elsif mask2(n)='1' and n/=STAGE-1 then`
123			`result( 2n+1 downto 2n ):=counter( 2n+3 downto 2n+2 );`
124			`else`
125			`result( 2n+1 downto 2n ):=counter( 2n+1 downto 2n );`
126			`end if;`
127			`end loop;`
128			`return result;`
129			`end counter2addr;`
130
131	9	sradio	`function outcounter2addr(`
132			`counter : std_logic_vector`
133			`) return std_logic_vector is`
134			`variable result :std_logic_vector(counter'range);`
135			`begin`
136			`for n in 0 to STAGE-1 loop`
137			`result( 2n+1 downto 2n ):=counter( counter'high-2n downto counter'high-2n-1 );`
138			`end loop;`
139			`return result;`
140			`end outcounter2addr;`
141	2	sradio
142			`signal rstate,wstate,state:std_logic_vector( 3 downto 0 );`
143			`signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );`
144			`signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );`
145			`signal outcounter:std_logic_vector( STAGE*2 downto 0 );`
146
147			`constant FFTDELAY:integer:=12+2*STAGE;`
148			`constant FACTORDELAY:integer:=6;`
149			`constant OUTDELAY:integer:=7;`
150
151
152
153			`begin`
154			`outdataen<=outcounter(STAGE*2);`
155	9	sradio	`OutPosition<=outcounter2addr( outcounter( STAGE*2-1 downto 0 ));`
156	2	sradio	`count:process( clk, rst )`
157			`begin`
158			`if rst='1' then`
159			`counter<=( others=>'0' );`
160			`state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);`
161			`elsif clk'event and clk='1' then`
162			`if start='1' then`
163			`counter<=( others=>'0' );`
164			`state<=(others=>'0');`
165			`elsif unsigned(state)/=STAGE+1 then`
166			`counter<=unsigned(counter)+1;`
167			`if signed(counter)=-1 then`
168			`state<=unsigned(state)+1;`
169			`end if;`
170			`end if;`
171			`end if;`
172			`end process count;`
173
174			`readaddr:process( clk,rst )`
175			`begin`
176			`if rst='1' then`
177			`raddr<=( others=>'0' );`
178			`rcounter<=( others=>'0' );`
179			`rstate<=( others=>'0' );`
180			`rmask1<=( others=>'0' );`
181			`rmask2<=( others=>'0' );`
182			`elsif clk'event and clk='1' then`
183			`if unsigned(state)=0 and signed(counter)=-1 then`
184			`rmask1(STAGE-1)<='1';`
185			`rmask1(STAGE-2 downto 0)<=(others=>'0');`
186			`rmask2(STAGE-1)<='0';`
187			`rmask2(STAGE-2 downto 0)<=(others=>'1');`
188			`elsif signed(counter)=-1 then`
189			`rmask1<='0'&rmask1( STAGE-1 downto 1 );`
190			`rmask2<='0'&rmask2( STAGE-1 downto 1 );`
191			`end if;`
192			`if unsigned(state)/=STAGE+1 and signed(counter)=-1 then`
193			`rcounter<=( others=>'0' );`
194			`rstate<=state;`
195			`else`
196			`rcounter<=unsigned(rcounter)+1;`
197			`end if;`
198			`raddr<=counter2addr( rcounter, rmask1, rmask2 );`
199			`-- modified for point configurable`
200			`-- case rstate is`
201			`-- when "000" =>`
202			`-- raddr<=rcounter( 1 downto 0 )&rcounter( 9 downto 2);`
203			`-- when "001" =>`
204			`-- raddr<=rcounter( 9 downto 8 )&rcounter( 1 downto 0 )&rcounter( 7 downto 2);`
205			`-- when "010" =>`
206			`-- raddr<=rcounter( 9 downto 6 )&rcounter( 1 downto 0 )&rcounter( 5 downto 2);`
207			`-- when "011" =>`
208			`-- raddr<=rcounter( 9 downto 4 )&rcounter( 1 downto 0 )&rcounter( 3 downto 2);`
209			`-- when "100" =>`
210			`-- raddr<=rcounter( 9 downto 2 )&rcounter( 1 downto 0 );`
211			`-- when others =>`
212			`-- raddr<=( others=> '0' );`
213			`-- end case;`
214			`end if;`
215			`end process readaddr;`
216
217			`writeaddr:process( clk,rst )`
218			`begin`
219			`if rst='1' then`
220			`waddr<=( others=>'0' );`
221			`wcounter<=( others=>'0' );`
222			`wstate<=( others=>'0' );`
223			`wmask1<=( others=>'0' );`
224			`wmask2<=( others=>'0' );`
225			`elsif clk'event and clk='1' then`
226			`if unsigned(state)=0 then`
227			`waddr<=counter;`
228			`else`
229			`if UNSIGNED(rstate)=0 and unsigned(rcounter)=FFTDELAY-1 then`
230			`wmask1(STAGE-1)<='1';`
231			`wmask1(STAGE-2 downto 0)<=(others=>'0');`
232			`wmask2(STAGE-1)<='0';`
233			`wmask2(STAGE-2 downto 0)<=(others=>'1');`
234			`elsif unsigned(rcounter)=FFTDELAY-1 then`
235			`wmask1<='0'&wmask1( STAGE-1 downto 1 );`
236			`wmask2<='0'&wmask2( STAGE-1 downto 1 );`
237			`end if;`
238			`if UNSIGNED(rstate)<STAGE and unsigned(rcounter)=FFTDELAY-1 then`
239			`wcounter<=( others=>'0' );`
240			`wstate<=rstate;`
241			`else`
242			`wcounter<=unsigned(wcounter)+1;`
243			`end if;`
244			`waddr<=counter2addr( wcounter, wmask1, wmask2 );`
245			`-- modified for point configurable`
246			`-- case wstate is`
247			`-- when "000" =>`
248			`-- waddr<=wcounter( 1 downto 0 )&wcounter( 9 downto 2);`
249			`-- when "001" =>`
250			`-- waddr<=wcounter( 9 downto 8 )&wcounter( 1 downto 0 )&wcounter( 7 downto 2);`
251			`-- when "010" =>`
252			`-- waddr<=wcounter( 9 downto 6 )&wcounter( 1 downto 0 )&wcounter( 5 downto 2);`
253			`-- when "011" =>`
254			`-- waddr<=wcounter( 9 downto 4 )&wcounter( 1 downto 0 )&wcounter( 3 downto 2);`
255			`-- when others =>`
256			`-- waddr<=( others=> '0' );`
257			`-- end case;`
258			`end if;`
259			`end if;`
260			`end process writeaddr;`
261
262			`writeen : process( clk, rst )`
263			`begin`
264			`if rst='1' then`
265			`wen<='0';`
266			`elsif clk'event and clk='1' then`
267			`if unsigned(state)=0 then`
268			`wen<='1';`
269			`elsif unsigned(state)=1 and unsigned(counter)=0 then`
270			`wen<='0';`
271			`elsif unsigned(rstate)=0 and unsigned(rcounter)=FFTDELAY then`
272			`wen<='1';`
273			`elsif unsigned(rstate)=STAGE-1 and unsigned(rcounter)=FFTDELAY then`
274			`wen<='0';`
275			`end if;`
276			`end if;`
277			`end process writeen;`
278
279			`otherstart : process( clk, rst )`
280			`begin`
281			`if rst='1' then`
282			`factorstart<='0';`
283			`cfft4start<='0';`
284			`outcounter<=(others=>'0');`
285			`inputbusy<='0';`
286			`elsif clk'event and clk='1' then`
287			`if start='1' then`
288			`inputbusy<='1';`
289			`elsif unsigned(state)=STAGE and unsigned(counter)=FFTDELAY then`
290			`inputbusy<='0';`
291			`end if;`
292			`if unsigned(state)=1 and unsigned(counter)=0 then`
293			`cfft4start<='1';`
294			`else`
295			`cfft4start<='0';`
296			`end if;`
297			`if unsigned(rstate)=0 and unsigned(rcounter)=FACTORDELAY then`
298			`factorstart<='1';`
299			`else`
300			`factorstart<='0';`
301			`end if;`
302			`if unsigned(state)=STAGE and unsigned(rcounter)=OUTDELAY then`
303			`outcounter<=CONV_STD_LOGIC_VECTOR(POINT,2*STAGE+1);`
304			`elsif outcounter(STAGE*2)='1' then`
305			`outcounter<=unsigned(outcounter)+1;`
306			`end if;`
307			`end if;`
308			`end process otherstart;`
309
310			`datasel : process( clk,rst )`
311			`begin`
312			`if rst='1' then`
313			`wdataI<=( others=>'0' );`
314			`wdataQ<=( others=>'0' );`
315			`elsif clk'event and clk='1' then`
316			`if unsigned(state)=0 then`
317			`wdataI<=Iin;`
318			`wdataQ<=Qin;`
319			`else`
320			`wdataI<=fftI;`
321			`wdataQ<=fftQ;`
322			`end if;`
323			`end if;`
324			`end process datasel;`
325
326			`end address;`