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1 2 sradio 
---------------------------------------------------------------------------------------------------
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--
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-- Title       : cfft
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-- Design      : cfft
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-- Author      : ZHAO Ming
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-- email        : sradio@opencores.org
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--
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---------------------------------------------------------------------------------------------------
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--
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-- File        : cfft.vhd
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-- Generated   : Thu Oct  3 03:03:58 2002
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : 4-based 1024 point FFT input 12 bit Output 14 bit with
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--               limit and overfall processing internal
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--
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--              The gain is 0.0287 for FFT and 29.4 for IFFT
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--
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--                              The output is 4-based reversed ordered, it means
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--                              a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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-- port :
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--                      clk : main clk          -- I have test 90M with Xilinx virtex600E
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--          rst : globe reset   -- '1' for reset
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--                      start : start fft       -- one clock '1' before data input
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--                      inv : '0' for fft and '1' for ifft, it is sampled when start is '1'
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--                      Iin,Qin : data input-- following start immediately, input data
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--                              -- power should not be too big
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--          inputbusy : if it change to '0' then next fft is enable
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--                      outdataen : when it is '1', the valid data is output
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--          Iout,Qout : fft data output when outdataen is '1'
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions       :    0
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-- Revision Number :    1
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-- Version         :    1.1.0
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-- Date            :    Oct 17 2002
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-- Modifier        :    ZHAO Ming
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-- Desccription    :    Data width configurable
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions       :    0
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-- Revision Number :    2
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-- Version         :    1.2.0
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-- Date            :    Oct 18 2002
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-- Modifier        :    ZHAO Ming
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-- Desccription    :    Point configurable
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--                      FFT Gain                IFFT GAIN
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--                               256    0.0698                  17.9
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--                              1024    0.0287                  29.4
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--                              4096    0.0118                  48.2742
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--
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--
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---------------------------------------------------------------------------------------------------
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65 
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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69 
entity cfft is
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        generic (
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                WIDTH : Natural;
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                POINT : Natural;
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                STAGE : Natural   -- STAGE=log4(POINT)
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        );
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         port(
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                 clk : in STD_LOGIC;
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                 rst : in STD_LOGIC;
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                 start : in STD_LOGIC;
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                 inv : in std_logic;
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                 Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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                 Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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                 inputbusy : out STD_LOGIC;
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                 outdataen : out STD_LOGIC;
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                 Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
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                 Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
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             );
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end cfft;
88 
 
89 
 
90 
architecture cfft of cfft is
91 
 
92 
component address
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        generic (
94 
                WIDTH : Natural;
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                POINT : Natural;
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                STAGE : Natural
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        );
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         port(
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                 clk : in STD_LOGIC;
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                 rst : in STD_LOGIC;
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                 start : in STD_LOGIC;
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                 Iin : in std_logic_vector( WIDTH-1 downto 0 );
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                 Qin : in std_logic_vector( WIDTH-1 downto 0 );
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                 fftI : in std_logic_vector( WIDTH-1 downto 0 );
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                 fftQ : in std_logic_vector( WIDTH-1 downto 0 );
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                 wdataI : out std_logic_vector( WIDTH-1 downto 0 );
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                 wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
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                 raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
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                 waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
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                 wen : out std_logic;
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                 factorstart : out STD_LOGIC;
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                 cfft4start : out STD_LOGIC;
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                 outdataen : out std_logic;
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                 inputbusy : out std_logic
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             );
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end component;
117 
 
118 
component blockdram
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generic(
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        depth:  integer;
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        Dwidth: integer;
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        Awidth: integer
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);
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port(
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        addra: IN std_logic_VECTOR(Awidth-1 downto 0);
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        clka: IN std_logic;
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        addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
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        clkb: IN std_logic;
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        dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
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        wea: IN std_logic;
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        dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
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end component;
133 
 
134 
component cfft4
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        generic (
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                WIDTH : Natural
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        );
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         port(
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                 clk : in STD_LOGIC;
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                 rst : in STD_LOGIC;
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                 start : in STD_LOGIC;
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                 inv : in std_logic;
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                 I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
144 
                 Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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                 Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
146 
                 Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
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             );
148 
end component;
149 
 
150 
component div4limit
151 
        generic (
152 
                WIDTH : Natural
153 
        );
154 
        port(
155 
                clk : in std_logic;
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                 D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
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                 Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
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             );
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end component;
160 
 
161 
component mulfactor
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        generic (
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                WIDTH : Natural;
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                STAGE : Natural
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        );
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         port(
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                 clk : in STD_LOGIC;
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                 rst : in STD_LOGIC;
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                 angle : in signed(2*STAGE-1 downto 0);
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                 I : in signed(WIDTH+1 downto 0);
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                 Q : in signed(WIDTH+1 downto 0);
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                 Iout : out signed(WIDTH+3 downto 0);
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                 Qout : out signed(WIDTH+3 downto 0)
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             );
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end component;
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component rofactor
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        generic (
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                POINT : Natural;
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                STAGE : Natural
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        );
182 
         port(
183 
                 clk : in STD_LOGIC;
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                 rst : in STD_LOGIC;
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                 start : in STD_LOGIC;
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                 inv : in std_logic;
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                 angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
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             );
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end component;
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signal wea,cfft4start,factorstart:std_logic:='0';
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signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');
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signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0');
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signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0');
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signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0');
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signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0');
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signal inv_reg:std_logic:='0';
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198 
begin
199 
 
200 
Aaddress:address
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generic map (
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        WIDTH=>WIDTH,
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        POINT=>POINT,
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        STAGE=>STAGE
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)
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port map (
207 
        clk=>clk,
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        rst=>rst,
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        start=>start,
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        Iin=>Iin,
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        Qin=>Qin,
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        fftI=>fftI,
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        fftQ=>fftQ,
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        wdataI=>wdataI,
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        wdataQ=>wdataQ,
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        raddr=>raddr,
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        waddr=>waddr,
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        wen=>wea,
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        factorstart=>factorstart,
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        cfft4start=>cfft4start,
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        outdataen=>outdataen,
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        inputbusy=>inputbusy
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             );
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Iram:blockdram
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generic map (
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        depth=>POINT,
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        Dwidth=>WIDTH,
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        Awidth=>2*STAGE
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)
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port map (
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        addra=>waddr,
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        clka=>clk,
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        addrb=>raddr,
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        clkb=>clk,
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        dia=>wdataI,
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        wea=>wea,
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        dob=>Iramout
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);
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Qram:blockdram
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generic map (
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        depth=>POINT,
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        Dwidth=>WIDTH,
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        Awidth=>2*STAGE
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)
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port map (
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        addra=>waddr,
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        clka=>clk,
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        addrb=>raddr,
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        clkb=>clk,
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        dia=>wdataQ,
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        wea=>wea,
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        dob=>Qramout
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);
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acfft4:cfft4
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generic map (
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        WIDTH=>WIDTH
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)
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port map (
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        clk=>clk,
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        rst=>rst,
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        start=>cfft4start,
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        inv=>inv_reg,
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        I=>Iramout,
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        Q=>Qramout,
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        Iout=>Icfft4out,
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        Qout=>Qcfft4out
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             );
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Iout<=Icfft4out;
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Qout<=Qcfft4out;
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275 
Ilimit:div4limit
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generic map (
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        WIDTH=>WIDTH
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)
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port map (
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        clk=>clk,
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        D=>std_logic_vector(Imulout),
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        Q=>fftI
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             );
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Qlimit:div4limit
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generic map (
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        WIDTH=>WIDTH
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)
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port map (
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        clk=>clk,
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        D=>std_logic_vector(Qmulout),
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        Q=>fftQ
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             );
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amulfactor:mulfactor
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generic map (
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        WIDTH=>WIDTH,
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        STAGE=>STAGE
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)
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port map (
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        clk=>clk,
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        rst=>rst,
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        angle=>signed(angle),
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        I=>signed(Icfft4out),
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        Q=>signed(Qcfft4out),
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        Iout=>Imulout,
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        Qout=>Qmulout
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             );
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arofactor:rofactor
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generic map (
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        POINT=>POINT,
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        STAGE=>STAGE
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)
314 
port map (
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        clk=>clk,
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        rst=>rst,
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        start=>factorstart,
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        inv=>inv_reg,
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        angle=>angle
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             );
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process( clk, rst )
323 
begin
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        if rst='1' then
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                inv_reg<='0';
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        elsif clk'event and clk='1' then
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                if start='1' then
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                        inv_reg<=inv;
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                end if;
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        end if;
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end process;
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end cfft;

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