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[/] [cic_core/] [trunk/] [sim/] [cic_d_tb.sv] - Blame information for rev 3

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1 3 vadimuzzz
`timescale 1ns / 1ns
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package cmath;
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    import "DPI-C" function real sin(input real x);
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endpackage
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module cic_d_tb
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(
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);
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localparam R = 25;
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localparam idw = 16;
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localparam odw = 16;
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localparam M = 4;
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localparam G = 1;
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/*************************************************************/
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localparam real Fs = 100;//MHz
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localparam real T_ns = 10**3/Fs;//ns
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localparam time half_T = T_ns/2;
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localparam real f = 0.5;//MHz
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localparam real f_inc = f/Fs;
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localparam bias = 5;
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real f_n = 0.0;
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/*************************************************************/
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reg                     clk;
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reg                     reset_n;
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reg signed[idw-1:0]     filter_in;
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wire                    filter_valid;
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wire signed[odw-1:0]    filter_out;
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/*************************************************************/
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import cmath::*;
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/*************************************************************/
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initial begin : clk_gen
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  clk <= 1'b0;
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  #half_T forever #half_T clk = ~clk;
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end
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/*************************************************************/
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initial begin : reset_gen
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  $display($time, " << Starting the Simulation >>");
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  reset_n = 1'b0;
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  repeat (2) @(negedge clk);
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  $display($time, " << Coming out of reset >>");
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  reset_n = 1'b1;
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  repeat (20) @(posedge clk);
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  @(posedge clk);
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end
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/*************************************************************/
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always @(posedge clk)
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begin
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    f_n = f_n + f_inc;
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end
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/*************************************************************/
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assign filter_in = $rtoi((2**(idw-1)-1)*($sin(f_n)));
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/*************************************************************/
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cic_d #(idw,odw,R,M,G) dut1
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(
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    .clk(clk),
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    .reset_n(reset_n),
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    .data_in(filter_in),
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    .data_out(filter_out),
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    .out_dv(filter_valid)
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);
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/*************************************************************/
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endmodule
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