OpenCores
URL https://opencores.org/ocsvn/cic_core/cic_core/trunk

Subversion Repositories cic_core

[/] [cic_core/] [trunk/] [sim/] [cic_i_tb.sv] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 vadimuzzz
`timescale 1ns / 1ns
2
/*********************************************************************************************/
3
module cic_i_tb();
4
/*********************************************************************************************/
5
//TB example: impulse responce
6
/*********************************************************************************************/
7
localparam dw = 10;
8
localparam m = 4;
9
localparam r = 4;
10
localparam g = 1;
11
/*********************************************************************************************/
12
reg clk;
13
reg reset_n;
14
reg signed [dw-1:0] data_in;
15
wire in_dv;
16
reg [$clog2(r)-1:0] counter;
17
wire signed [dw+$clog2((r**(m))/r)-1:0] data_out;
18
/*********************************************************************************************/
19
initial begin : clk_gen
20
    clk <= 1'b0;
21
    #5 forever #5 clk <= ~clk;
22
end
23
/*********************************************************************************************/
24
initial begin : reset_gen
25
    $display($time, " << Starting the Simulation >>");
26
    reset_n = 1'b0;
27
    data_in = '0;
28
    repeat (2) @(negedge clk);
29
    $display($time, " << Coming out of reset >>");
30
    reset_n = 1'b1;
31
    repeat(3) @(posedge clk);
32
    data_in = 2**(dw-1)-1;
33
    @(posedge clk);
34
    data_in = '0;
35
end
36
/*********************************************************************************************/
37
assign in_dv = &counter;
38
/*********************************************************************************************/
39
always @(posedge clk)
40
begin
41
    if (!reset_n)
42
        counter = '0;
43
    else
44
        counter++;
45
end
46
/*********************************************************************************************/
47
cic_i #(dw, r, m, g) dut1
48
(
49
    .clk(clk),
50
    .reset_n(reset_n),
51
    .data_in(data_in),
52
    .in_dv(in_dv),
53
    .data_out(data_out)
54
);
55
/*********************************************************************************************/
56
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.