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vadimuzzz |
module cic_d
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/*********************************************************************************************/
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#(parameter idw = 8, odw = 8, r = 4, m = 4, g = 1)
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/*********************************************************************************************/
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//m - CIC order (comb chain length, integrator chain length)
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//r - interpolation ratio
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//idw - input data width
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//odw - output data width
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//g - differential delay in combs
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/*********************************************************************************************/
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(
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input clk,
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input reset_n,
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input signed [idw-1:0] data_in,
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output signed [odw-1:0] data_out,
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output out_dv
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);
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/*********************************************************************************************/
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localparam b_max = $clog2((r*g)**m)+idw;
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/*********************************************************************************************/
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genvar i;
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generate
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for (i = 0; i < m; i++) begin:int_stage
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localparam idw_cur = b_max-cic_package::B(i+1,r,g,m,idw,odw)+1;
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localparam odw_cur = idw_cur;
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localparam odw_prev = (i!=0) ? b_max-cic_package::B(i,r,g,m,idw,odw)+1 : 0;
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wire signed [idw_cur-1:0] int_in;
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if (i!=0)
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assign int_in = int_stage[i-1].int_out[odw_prev-1:odw_prev-idw_cur];
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else
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assign int_in = data_in;
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wire signed [odw_cur-1:0] int_out;
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integrator #(idw_cur, odw_cur) int_inst(.clk(clk) , .reset_n(reset_n) , .data_in(int_in) , .data_out(int_out));
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end
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endgenerate
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/*********************************************************************************************/
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localparam ds_dw = b_max-cic_package::B(m,r,g,m,idw,odw)+1;
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wire signed [ds_dw-1:0] ds_out;
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wire ds_dv;
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/*********************************************************************************************/
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downsampler #(ds_dw, r) u1
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(
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.clk(clk),
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.reset_n(reset_n),
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.data_in(int_stage[m-1].int_out),
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.data_out(ds_out),
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.dv(ds_dv)
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);
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/*********************************************************************************************/
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genvar j;
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generate
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for (j = 0; j < m; j++) begin:comb_stage
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localparam idw_cur = b_max-cic_package::B(m+j+1,r,g,m,idw,odw);
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localparam odw_cur = idw_cur;
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localparam odw_prev = (j!=0) ? b_max-cic_package::B(m+j,r,g,m,idw,odw) : 0;
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wire signed [idw_cur-1:0] comb_in;
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if (j!=0)
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assign comb_in = comb_stage[j-1].comb_out[odw_prev-1:odw_prev-idw_cur];
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else
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assign comb_in = ds_out[ds_dw-1:ds_dw-idw_cur];
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wire signed [odw_cur-1:0] comb_out;
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comb #(idw_cur, odw_cur, g) comb_inst(.clk(clk) , .reset_n(reset_n) , .in_dv(ds_dv) , .data_in(comb_in) , .data_out(comb_out));
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end
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endgenerate
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/*********************************************************************************************/
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localparam dw_out = b_max-cic_package::B(2*m,r,g,m,idw,odw);
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assign data_out = comb_stage[m-1].comb_out[dw_out-1:dw_out-odw];
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assign out_dv = ds_dv;
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/*********************************************************************************************/
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endmodule
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