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[/] [cic_core/] [trunk/] [src/] [integrator.sv] - Blame information for rev 4
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vadimuzzz |
module integrator
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/*********************************************************************************************/
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#(parameter idw = 8 , odw = 9)
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/*********************************************************************************************/
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(
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input clk,
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input reset_n,
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input signed [idw-1:0] data_in,
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output reg signed [odw-1:0] data_out
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);
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/*********************************************************************************************/
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always_ff @(posedge clk)
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begin
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if (!reset_n)
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data_out <= '0;
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else
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data_out <= data_out + data_in;
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end
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/*********************************************************************************************/
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endmodule
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