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[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [cic_d.sv] - Blame information for rev 6

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module cic_d
/*********************************************************************************************/
#(
        parameter INP_DW = 18,                  ///< input data width
        parameter OUT_DW = 18,                  ///< output data width
        parameter CIC_R = 100,                  ///< decimation ratio
        parameter CIC_N = 7,                    ///< number of stages
        parameter CIC_M = 1,                    ///< delay in comb
        parameter SMALL_FOOTPRINT = 1   ///< reduced registers usage, f_clk / (f_samp/CIC_R)  > CIC_N required
)
/*********************************************************************************************/
(
        input                                                           clk,
        input                                                           reset_n,
        input                                                           clear,
        input   wire    signed [INP_DW-1:0]     inp_samp_data,
        input                                                           inp_samp_str,
        output  wire    signed [OUT_DW-1:0]     out_samp_data,
        output                                                          out_samp_str
);
/*********************************************************************************************/
`include "cic_functions.vh"
/*********************************************************************************************/
localparam      B_max = clog2_l((CIC_R * CIC_M) ** CIC_N) + INP_DW - 1;
/*********************************************************************************************/
 
genvar  i;
generate
        for (i = 0; i < CIC_N; i = i + 1) begin : int_stage
                localparam B_j          = B(i + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);
                localparam B_jm1        = B(i    , CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);
                localparam logic [127:0 ] F_sq_j        = F_sq(i , CIC_R, CIC_M, CIC_N);
                localparam dw_cur = B_max - B_j + 1;
                localparam odw_cur = dw_cur;
                localparam B_dw_prev = (i != 0) ? B_max - B_jm1 + 1 : 0;
                localparam odw_prev = (B_dw_prev > 1) ? B_dw_prev : 2;  /// icarus stops with error if in [a -: b] a is <= 0
                localparam idw_cur = dw_cur > 0 ? dw_cur : 1;
                wire signed [idw_cur - 1 : 0] int_in;
                if ( i == 0 )   assign int_in = inp_samp_data;
                        else            assign int_in = int_stage[i - 1].int_out[odw_prev - 1 -: idw_cur];
                wire signed [odw_cur - 1 : 0] int_out;
                integrator #(
                                idw_cur,
                                odw_cur
                        )
                        int_inst(
                                .clk                    (clk),
                                .reset_n                (reset_n),
                                .clear                  (clear) ,
                                .inp_samp_data  (int_in),
                                .inp_samp_str   (inp_samp_str),
                                .out_samp_data  (int_out)
                                );
                initial begin
                        //$display("i:%d integ dw %d         B(%d, %d, %d, %d, %d, %d)=%d, F_sq=%d", i, odw_cur, i + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW, B_j, F_sq_j);
                        $display("i:%d integ dw %d ", i, odw_cur);
                end
        end
endgenerate
/*********************************************************************************************/
localparam B_m = B(CIC_N, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);
localparam ds_dw = B_max - B_m + 1;
wire    signed [ds_dw - 1 : 0]  ds_out_samp_data;
wire                                                    ds_out_samp_str;
/*********************************************************************************************/
initial begin
        //$display("i downsamp dw %d , int_stage[%2d].dw_out = %2d", ds_dw, CIC_N - 1, int_stage[CIC_N - 1].odw_cur);
        $display("i downsamp dw %d", ds_dw);
end
downsampler #(
                .DATA_WIDTH_INP (ds_dw),
                .CIC_R                  (CIC_R)
        )
        downsampler_inst
        (
                .clk                    (clk),
                .reset_n                (reset_n),
                .clear                  (clear),
                .inp_samp_data  (int_stage[CIC_N - 1].int_out),
                .inp_samp_str   (inp_samp_str),
                .out_samp_data  (ds_out_samp_data),
                .out_samp_str   (ds_out_samp_str)
        );
/*********************************************************************************************/
genvar  j;
wire comb_chain_out_str;
reg     [CIC_N : 0]     comb_inp_str_d;
generate
        wire summ_rdy_str;
        if (SMALL_FOOTPRINT != 0) begin
                always @(negedge reset_n or posedge clk)
                        if              (~reset_n)      comb_inp_str_d <= '0;
                        else if (clear)         comb_inp_str_d <= '0;
                        else                            comb_inp_str_d <= {comb_inp_str_d[CIC_N - 1 : 0], ds_out_samp_str};
        end
 
        if (SMALL_FOOTPRINT == 0)       assign summ_rdy_str = '0;
        else                                            assign summ_rdy_str = comb_inp_str_d[CIC_N];
 
 
        for (j = 0; j < CIC_N; j = j + 1) begin : comb_stage
                localparam j_cic                = CIC_N + j + 1;
                localparam B_m_j                =    B(            j_cic,       CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);
                localparam F_sq_j               = F_sq(            j_cic,       CIC_R, CIC_M, CIC_N);
                localparam B_m_j_m1             =    B(    CIC_N + j,   CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);
                localparam F_sq_2Np1    = F_sq(2 * CIC_N + 1,   CIC_R, CIC_M, CIC_N);
                localparam idw_cur = B_max - B_m_j + 1;
                localparam odw_cur = idw_cur;
                localparam odw_prev = (j != 0) ? B_max - B_m_j_m1 + 1 : 0;
                wire signed [idw_cur - 1 : 0] comb_in;
                wire signed [odw_cur - 1 : 0] comb_out;
                wire comb_dv;
                if (j == 0)     assign comb_in = ds_out_samp_data[ds_dw - 1 -: idw_cur];
                        else    assign comb_in = comb_stage[j - 1].comb_out[odw_prev - 1 -: idw_cur];
                comb #(
                                .SAMP_WIDTH             (idw_cur),
                                .CIC_M                  (CIC_M),
                                .SMALL_FOOTPRINT(SMALL_FOOTPRINT)
                        )
                        comb_inst(
                                .clk                    (clk),
                                .reset_n                (reset_n),
                                .clear                  (clear),
                                .samp_inp_str   (ds_out_samp_str),
                                .samp_inp_data  (comb_in),
                                .summ_rdy_str   (summ_rdy_str),
                                .samp_out_str   (comb_dv),
                                .samp_out_data  (comb_out)
                                );
                if (SMALL_FOOTPRINT == 0)       assign comb_chain_out_str = comb_stage[CIC_N - 1].comb_dv;
                else                                            assign comb_chain_out_str = comb_inp_str_d[CIC_N - 1];
                initial begin
                        //$display("i:%d  comb dw %d inp comb_out[%2d -: %2d]; B(%2d, %1d, %1d, %1d, %1d, %1d)=%2d, ln(F_sq)=%4d, F_sq=%8d", j, odw_cur, odw_prev - 1, idw_cur, CIC_N + j + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW, B_m_j, $ln(F_sq_j), F_sq_j);
                        $display("i:%d  comb dw %d", j, odw_cur);
                end
        end
endgenerate
/*********************************************************************************************/
localparam dw_out = B_max - B(2 * CIC_N, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW) + 1;
reg             signed [OUT_DW-1:0]     comb_out_samp_data_reg;
reg                                                     comb_out_samp_str_reg;
 
always @(negedge reset_n or posedge clk)
begin
        if              (~reset_n)                                      comb_out_samp_data_reg <= '0;
        else if (comb_chain_out_str)            comb_out_samp_data_reg <= comb_stage[CIC_N - 1].comb_out[dw_out - 1 -: OUT_DW];
end
 
always @(negedge reset_n or posedge clk)
        if              (~reset_n)                                      comb_out_samp_str_reg <= '0;
        else if (clear)                                         comb_out_samp_str_reg <= '0;
        else                                                            comb_out_samp_str_reg <= comb_chain_out_str;
 
assign out_samp_data    = comb_out_samp_data_reg;
assign out_samp_str             = comb_out_samp_str_reg;
/*********************************************************************************************/
task print_parameters_nice;
        integer tot_registers;
        integer j;
        integer B_2Np1;
        integer dw_j;
        integer B_j;
        reg [127:0] h_f0_pre;
        integer log2_h_f0_pre;
        integer h_f0_pre_limit_prec;
        integer h_f0_pre_divider;
        integer h_f0_divider_exp;
        integer h_f0_x_mul;
        integer x_multiplier;
        reg [127:0] F_sq_curr;
        x_multiplier = 100000;
        B_2Np1 = B_max - dw_out + 1;
        h_f0_pre = (CIC_R*CIC_M)**CIC_N;
        h_f0_divider_exp = (B_2Np1 + 1);
        h_f0_pre_limit_prec = 30;
        log2_h_f0_pre = clog2_l(h_f0_pre);
        if (log2_h_f0_pre > h_f0_pre_limit_prec) begin
                //$display(" log2_h_f0_pre = %2d, lim %2d", log2_h_f0_pre, h_f0_pre_limit_prec);
                h_f0_pre_divider = log2_h_f0_pre - h_f0_pre_limit_prec;
                //$display(" h_f0_pre_divider = %2d", h_f0_pre_divider);
                h_f0_pre = h_f0_pre >> h_f0_pre_divider;
                h_f0_divider_exp = h_f0_divider_exp - h_f0_pre_divider;
                //$display(" log2_h_f0_pre limited = %2d, divider_exp limited %2d", log2_h_f0_pre, h_f0_divider_exp);
                h_f0_x_mul = x_multiplier * h_f0_pre / 2**(h_f0_divider_exp);
        end
        else begin
                h_f0_x_mul = x_multiplier * h_f0_pre / 2**(B_2Np1 + 1);
        end
        $display("CIC inp_dw   %d", INP_DW);
        $display("CIC out_dw   %d", OUT_DW);
        $display("CIC B_max    %d", B_max);
        $display("CIC B_2Np1   %d", B_2Np1);
        $display("CIC h(f=0)   %1d.%1d", h_f0_x_mul / x_multiplier, h_f0_x_mul % x_multiplier);
        $display(" clog2_l((r*m)**n)  %d", clog2_l((CIC_R*CIC_M)**CIC_N));
        tot_registers = 0;
        for (j = 1; j < 2 * CIC_N + 2; j = j + 1) begin : check_Bj
                F_sq_curr = F_sq(j, CIC_R, CIC_M, CIC_N);
                B_j = B(j, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);
                dw_j = B_max - B_j + 1;
                tot_registers = tot_registers + dw_j;
        end
        $display("CIC total registers %2d", tot_registers);
endtask
 
 
generate
        initial begin : initial_print_parameters
        if (0) begin
                print_parameters_nice;
        end
 
        end
        if (0) begin
                for (j = 0; j < CIC_N; j = j + 1) begin : print_int_stage
                        initial begin
                                $display("CIC integrator j:%2d B %2d B_ jm1 %2d odw_prev %2d in_dw %3d out_dw %3d data_width_pass %3d", j + 1, int_stage[j].B_j, int_stage[j].B_jm1, int_stage[j].odw_prev, int_stage[j].idw_cur, int_stage[j].odw_cur, 0);
                        end
                end
                initial begin
                                $display("CIC downsampler     B %2d                                  ds_dw %3d", B_m, ds_dw);
                end
                for (j = 0; j < CIC_N; j = j + 1) begin : print_comb_stage
                        initial begin
                                $display("CIC comb       j:%2d B %2d B_mjm1 %2d             in_dw %3d out_dw %3d", j, comb_stage[j].B_m_j, comb_stage[j].B_m_j_m1, comb_stage[j].idw_cur, comb_stage[j].odw_cur);
                        end
                end
                initial begin
                        $display("CIC out odw %3d", OUT_DW);
                end
        end
endgenerate
endmodule

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Subversion Repositories cic_core_2

[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [cic_d.sv] - Blame information for rev 6

Line No.	Rev	Author	Line
1	4	Juzujka	`module cic_d`
2			`/*********************************************************************************************/`
3			`#(`
4			`parameter INP_DW = 18, ///< input data width`
5			`parameter OUT_DW = 18, ///< output data width`
6			`parameter CIC_R = 100, ///< decimation ratio`
7			`parameter CIC_N = 7, ///< number of stages`
8			`parameter CIC_M = 1, ///< delay in comb`
9			`parameter SMALL_FOOTPRINT = 1 ///< reduced registers usage, f_clk / (f_samp/CIC_R) > CIC_N required`
10			`)`
11			`/*********************************************************************************************/`
12			`(`
13			`input clk,`
14			`input reset_n,`
15			`input clear,`
16			`input wire signed [INP_DW-1:0] inp_samp_data,`
17			`input inp_samp_str,`
18			`output wire signed [OUT_DW-1:0] out_samp_data,`
19			`output out_samp_str`
20			`);`
21			`/*********************************************************************************************/`
22	6	Juzujka	`include "cic_functions.vh"
23	4	Juzujka	`/*********************************************************************************************/`
24			`localparam B_max = clog2_l((CIC_R * CIC_M) ** CIC_N) + INP_DW - 1;`
25			`/*********************************************************************************************/`
26
27			`genvar i;`
28			`generate`
29			`for (i = 0; i < CIC_N; i = i + 1) begin : int_stage`
30			`localparam B_j = B(i + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);`
31			`localparam B_jm1 = B(i , CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);`
32			`localparam logic [127:0 ] F_sq_j = F_sq(i , CIC_R, CIC_M, CIC_N);`
33			`localparam dw_cur = B_max - B_j + 1;`
34			`localparam odw_cur = dw_cur;`
35			`localparam B_dw_prev = (i != 0) ? B_max - B_jm1 + 1 : 0;`
36			`localparam odw_prev = (B_dw_prev > 1) ? B_dw_prev : 2; /// icarus stops with error if in [a -: b] a is <= 0`
37			`localparam idw_cur = dw_cur > 0 ? dw_cur : 1;`
38			`wire signed [idw_cur - 1 : 0] int_in;`
39			`if ( i == 0 ) assign int_in = inp_samp_data;`
40			`else assign int_in = int_stage[i - 1].int_out[odw_prev - 1 -: idw_cur];`
41			`wire signed [odw_cur - 1 : 0] int_out;`
42			`integrator #(`
43			`idw_cur,`
44			`odw_cur`
45			`)`
46			`int_inst(`
47			`.clk (clk),`
48			`.reset_n (reset_n),`
49			`.clear (clear) ,`
50			`.inp_samp_data (int_in),`
51			`.inp_samp_str (inp_samp_str),`
52			`.out_samp_data (int_out)`
53			`);`
54			`initial begin`
55			`//$display("i:%d integ dw %d B(%d, %d, %d, %d, %d, %d)=%d, F_sq=%d", i, odw_cur, i + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW, B_j, F_sq_j);`
56			`$display("i:%d integ dw %d ", i, odw_cur);`
57			`end`
58			`end`
59			`endgenerate`
60			`/*********************************************************************************************/`
61			`localparam B_m = B(CIC_N, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);`
62			`localparam ds_dw = B_max - B_m + 1;`
63			`wire signed [ds_dw - 1 : 0] ds_out_samp_data;`
64			`wire ds_out_samp_str;`
65			`/*********************************************************************************************/`
66			`initial begin`
67			`//$display("i downsamp dw %d , int_stage[%2d].dw_out = %2d", ds_dw, CIC_N - 1, int_stage[CIC_N - 1].odw_cur);`
68			`$display("i downsamp dw %d", ds_dw);`
69			`end`
70			`downsampler #(`
71			`.DATA_WIDTH_INP (ds_dw),`
72			`.CIC_R (CIC_R)`
73			`)`
74			`downsampler_inst`
75			`(`
76			`.clk (clk),`
77			`.reset_n (reset_n),`
78			`.clear (clear),`
79			`.inp_samp_data (int_stage[CIC_N - 1].int_out),`
80			`.inp_samp_str (inp_samp_str),`
81			`.out_samp_data (ds_out_samp_data),`
82			`.out_samp_str (ds_out_samp_str)`
83			`);`
84			`/*********************************************************************************************/`
85			`genvar j;`
86			`wire comb_chain_out_str;`
87			`reg [CIC_N : 0] comb_inp_str_d;`
88			`generate`
89			`wire summ_rdy_str;`
90			`if (SMALL_FOOTPRINT != 0) begin`
91			`always @(negedge reset_n or posedge clk)`
92			`if (~reset_n) comb_inp_str_d <= '0;`
93			`else if (clear) comb_inp_str_d <= '0;`
94			`else comb_inp_str_d <= {comb_inp_str_d[CIC_N - 1 : 0], ds_out_samp_str};`
95			`end`
96
97			`if (SMALL_FOOTPRINT == 0) assign summ_rdy_str = '0;`
98			`else assign summ_rdy_str = comb_inp_str_d[CIC_N];`
99
100
101			`for (j = 0; j < CIC_N; j = j + 1) begin : comb_stage`
102			`localparam j_cic = CIC_N + j + 1;`
103			`localparam B_m_j = B( j_cic, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);`
104			`localparam F_sq_j = F_sq( j_cic, CIC_R, CIC_M, CIC_N);`
105			`localparam B_m_j_m1 = B( CIC_N + j, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);`
106			`localparam F_sq_2Np1 = F_sq(2 * CIC_N + 1, CIC_R, CIC_M, CIC_N);`
107			`localparam idw_cur = B_max - B_m_j + 1;`
108			`localparam odw_cur = idw_cur;`
109			`localparam odw_prev = (j != 0) ? B_max - B_m_j_m1 + 1 : 0;`
110			`wire signed [idw_cur - 1 : 0] comb_in;`
111			`wire signed [odw_cur - 1 : 0] comb_out;`
112			`wire comb_dv;`
113			`if (j == 0) assign comb_in = ds_out_samp_data[ds_dw - 1 -: idw_cur];`
114			`else assign comb_in = comb_stage[j - 1].comb_out[odw_prev - 1 -: idw_cur];`
115			`comb #(`
116			`.SAMP_WIDTH (idw_cur),`
117			`.CIC_M (CIC_M),`
118			`.SMALL_FOOTPRINT(SMALL_FOOTPRINT)`
119			`)`
120			`comb_inst(`
121			`.clk (clk),`
122			`.reset_n (reset_n),`
123			`.clear (clear),`
124			`.samp_inp_str (ds_out_samp_str),`
125			`.samp_inp_data (comb_in),`
126			`.summ_rdy_str (summ_rdy_str),`
127			`.samp_out_str (comb_dv),`
128			`.samp_out_data (comb_out)`
129			`);`
130			`if (SMALL_FOOTPRINT == 0) assign comb_chain_out_str = comb_stage[CIC_N - 1].comb_dv;`
131			`else assign comb_chain_out_str = comb_inp_str_d[CIC_N - 1];`
132			`initial begin`
133			`//$display("i:%d comb dw %d inp comb_out[%2d -: %2d]; B(%2d, %1d, %1d, %1d, %1d, %1d)=%2d, ln(F_sq)=%4d, F_sq=%8d", j, odw_cur, odw_prev - 1, idw_cur, CIC_N + j + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW, B_m_j, $ln(F_sq_j), F_sq_j);`
134			`$display("i:%d comb dw %d", j, odw_cur);`
135			`end`
136			`end`
137			`endgenerate`
138			`/*********************************************************************************************/`
139			`localparam dw_out = B_max - B(2 * CIC_N, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW) + 1;`
140			`reg signed [OUT_DW-1:0] comb_out_samp_data_reg;`
141			`reg comb_out_samp_str_reg;`
142
143			`always @(negedge reset_n or posedge clk)`
144			`begin`
145			`if (~reset_n) comb_out_samp_data_reg <= '0;`
146			`else if (comb_chain_out_str) comb_out_samp_data_reg <= comb_stage[CIC_N - 1].comb_out[dw_out - 1 -: OUT_DW];`
147			`end`
148
149			`always @(negedge reset_n or posedge clk)`
150			`if (~reset_n) comb_out_samp_str_reg <= '0;`
151			`else if (clear) comb_out_samp_str_reg <= '0;`
152			`else comb_out_samp_str_reg <= comb_chain_out_str;`
153
154			`assign out_samp_data = comb_out_samp_data_reg;`
155			`assign out_samp_str = comb_out_samp_str_reg;`
156			`/*********************************************************************************************/`
157			`task print_parameters_nice;`
158			`integer tot_registers;`
159			`integer j;`
160			`integer B_2Np1;`
161			`integer dw_j;`
162			`integer B_j;`
163			`reg [127:0] h_f0_pre;`
164			`integer log2_h_f0_pre;`
165			`integer h_f0_pre_limit_prec;`
166			`integer h_f0_pre_divider;`
167			`integer h_f0_divider_exp;`
168			`integer h_f0_x_mul;`
169			`integer x_multiplier;`
170			`reg [127:0] F_sq_curr;`
171			`x_multiplier = 100000;`
172			`B_2Np1 = B_max - dw_out + 1;`
173			`h_f0_pre = (CIC_RCIC_M)*CIC_N;`
174			`h_f0_divider_exp = (B_2Np1 + 1);`
175			`h_f0_pre_limit_prec = 30;`
176			`log2_h_f0_pre = clog2_l(h_f0_pre);`
177			`if (log2_h_f0_pre > h_f0_pre_limit_prec) begin`
178			`//$display(" log2_h_f0_pre = %2d, lim %2d", log2_h_f0_pre, h_f0_pre_limit_prec);`
179			`h_f0_pre_divider = log2_h_f0_pre - h_f0_pre_limit_prec;`
180			`//$display(" h_f0_pre_divider = %2d", h_f0_pre_divider);`
181			`h_f0_pre = h_f0_pre >> h_f0_pre_divider;`
182			`h_f0_divider_exp = h_f0_divider_exp - h_f0_pre_divider;`
183			`//$display(" log2_h_f0_pre limited = %2d, divider_exp limited %2d", log2_h_f0_pre, h_f0_divider_exp);`
184			`h_f0_x_mul = x_multiplier * h_f0_pre / 2**(h_f0_divider_exp);`
185			`end`
186			`else begin`
187			`h_f0_x_mul = x_multiplier * h_f0_pre / 2**(B_2Np1 + 1);`
188			`end`
189			`$display("CIC inp_dw %d", INP_DW);`
190			`$display("CIC out_dw %d", OUT_DW);`
191			`$display("CIC B_max %d", B_max);`
192			`$display("CIC B_2Np1 %d", B_2Np1);`
193			`$display("CIC h(f=0) %1d.%1d", h_f0_x_mul / x_multiplier, h_f0_x_mul % x_multiplier);`
194			`$display(" clog2_l((rm)n) %d", clog2_l((CIC_RCIC_M)**CIC_N));`
195			`tot_registers = 0;`
196			`for (j = 1; j < 2 * CIC_N + 2; j = j + 1) begin : check_Bj`
197			`F_sq_curr = F_sq(j, CIC_R, CIC_M, CIC_N);`
198			`B_j = B(j, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW);`
199			`dw_j = B_max - B_j + 1;`
200			`tot_registers = tot_registers + dw_j;`
201			`end`
202			`$display("CIC total registers %2d", tot_registers);`
203			`endtask`
204
205
206			`generate`
207			`initial begin : initial_print_parameters`
208			`if (0) begin`
209			`print_parameters_nice;`
210			`end`
211
212			`end`
213			`if (0) begin`
214			`for (j = 0; j < CIC_N; j = j + 1) begin : print_int_stage`
215			`initial begin`
216			`$display("CIC integrator j:%2d B %2d B_ jm1 %2d odw_prev %2d in_dw %3d out_dw %3d data_width_pass %3d", j + 1, int_stage[j].B_j, int_stage[j].B_jm1, int_stage[j].odw_prev, int_stage[j].idw_cur, int_stage[j].odw_cur, 0);`
217			`end`
218			`end`
219			`initial begin`
220			`$display("CIC downsampler B %2d ds_dw %3d", B_m, ds_dw);`
221			`end`
222			`for (j = 0; j < CIC_N; j = j + 1) begin : print_comb_stage`
223			`initial begin`
224			`$display("CIC comb j:%2d B %2d B_mjm1 %2d in_dw %3d out_dw %3d", j, comb_stage[j].B_m_j, comb_stage[j].B_m_j_m1, comb_stage[j].idw_cur, comb_stage[j].odw_cur);`
225			`end`
226			`end`
227			`initial begin`
228			`$display("CIC out odw %3d", OUT_DW);`
229			`end`
230			`end`
231			`endgenerate`
232			`endmodule`