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Juzujka |
`timescale 1ns / 1ns
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/**
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* Module: comb
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*
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* Comb stage for CIC filter
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* There is two variants of realisation.
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* Ordinary (SMALL_FOOTPRINT = 0).
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* For every stage in the output extra register added for isolation combinatorial logic outside own adder.
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* Small footprint (SMALL_FOOTPRINT = 1)
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* No additional register, adders are in the chain of CIC_N cells.
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* Output sample generated after CIC_N clocks, f_clk / f_comb_samp > CIC_N required.
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*
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*/
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module comb
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/*********************************************************************************************/
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#(
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parameter SAMP_WIDTH = 8,
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parameter CIC_M = 1,
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//parameter CIC_N = 1,
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parameter SMALL_FOOTPRINT = 0 ///< set to 1 for less registers usage, but for every sample CIC_N clocks required
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)
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/*********************************************************************************************/
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(
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input clk,
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input reset_n,
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input clear,
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input wire signed [SAMP_WIDTH - 1:0] samp_inp_data,
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input samp_inp_str,
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input summ_rdy_str, ///< for SMALL_FOOTPRINT set 1 after CIC_N cycles from inp_str to load FIFO registers with new sample
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///< output data must be latched before summ_rdy_str is set, read output data at CIC_N - 1 clock after inp_str
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output wire signed [SAMP_WIDTH - 1:0] samp_out_data,
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output wire samp_out_str
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);
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/*********************************************************************************************/
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integer i;
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reg signed [SAMP_WIDTH - 1 : 0] data_reg[CIC_M - 1 : 0]; ///< the storage for the FIFO register
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wire data_reg_push_str; ///< strobe to push data into data_reg FIFO
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/*********************************************************************************************/
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generate
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if (SMALL_FOOTPRINT == 0) begin
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reg samp_out_str_reg;
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reg signed [SAMP_WIDTH - 1 : 0] data_out_reg;
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assign data_reg_push_str = samp_inp_str;
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always @(posedge clk or negedge reset_n)
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begin
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if (!reset_n) data_out_reg <= '0;
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else if (clear) data_out_reg <= '0;
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else if (samp_inp_str) data_out_reg <= samp_inp_data - data_reg[CIC_M - 1];
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end
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assign samp_out_data = data_out_reg;
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always @(posedge clk or negedge reset_n)
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begin
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if (!reset_n) samp_out_str_reg <= '0;
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else if (clear) samp_out_str_reg <= '0;
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else samp_out_str_reg <= samp_inp_str;
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end
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assign samp_out_str = samp_out_str_reg;
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end else begin
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assign data_reg_push_str = summ_rdy_str;
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assign #4 samp_out_data = samp_inp_data - data_reg[CIC_M - 1]; // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
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assign samp_out_str = summ_rdy_str;
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end
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endgenerate
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/*********************************************************************************************/
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// FIFO register with reset and clear
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always @(posedge clk or negedge reset_n)
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begin
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if (!reset_n) for (i = 0; i < CIC_M; i = i + 1) data_reg[i] <= '0;
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else if (clear) for (i = 0; i < CIC_M; i = i + 1) data_reg[i] <= '0;
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else if (data_reg_push_str) begin
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data_reg[0] <= samp_inp_data;
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for (i = 1; i < CIC_M; i = i + 1) data_reg[i] <= data_reg[i - 1];
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end
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end
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/*********************************************************************************************/
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endmodule
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