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[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [downsampler.sv] - Blame information for rev 7

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Line No. Rev Author Line
1 7 Juzujka 
module downsampler
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/*********************************************************************************************/
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#(
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        parameter DATA_WIDTH_INP = 8,
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        parameter CIC_R = 4
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)
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/*********************************************************************************************/
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(
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        input                                                                                   clk,
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        input                                                                                   reset_n,
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        input                                                                                   clear,
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        input   wire    signed  [DATA_WIDTH_INP - 1:0]  inp_samp_data,
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        input                                                                                   inp_samp_str,
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        output  reg             signed  [DATA_WIDTH_INP - 1:0]  out_samp_data,
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        output  reg                                                                             out_samp_str
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);
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/*********************************************************************************************/
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localparam DECIM_COUNTER_WIDTH = $clog2(CIC_R);
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reg [DECIM_COUNTER_WIDTH - 1 : 0] counter;
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/*********************************************************************************************/
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// decimation counter
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always @(posedge clk or negedge reset_n)
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begin
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        if              (!reset_n)                      counter <= '0;
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        else    if (clear)                      counter <= '0;
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        else    if (inp_samp_str)       counter <= (counter < CIC_R - 1) ? counter + {{(DECIM_COUNTER_WIDTH - 1){1'b0}}, 1'b1} : '0;
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end
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/*********************************************************************************************/
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// output register
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always @(posedge clk or negedge reset_n)
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begin
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        if              (!reset_n)                      out_samp_data <= '0;
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        else    if (clear)                      out_samp_data <= '0;
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        else    if (inp_samp_str)       out_samp_data <= (counter < CIC_R - 1) ? out_samp_data : inp_samp_data;
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end
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/*********************************************************************************************/
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// data valid register
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always @(posedge clk or negedge reset_n)
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begin
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        if              (!reset_n)                      out_samp_str <= 1'b0;
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        else    if (clear)                      out_samp_str <= 1'b0;
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        else    if (inp_samp_str)       out_samp_str <= (counter == CIC_R - 1);
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        else                                            out_samp_str <= 1'b0;
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end
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/*********************************************************************************************/
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endmodule

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