OpenCores
URL https://opencores.org/ocsvn/cic_core_2/cic_core_2/trunk

Subversion Repositories cic_core_2

[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [downsampler.sv] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 Juzujka 
module downsampler
2 
/*********************************************************************************************/
3 
#(
4 
        parameter DATA_WIDTH_INP = 8,
5 
        parameter CIC_R = 4
6 
)
7 
/*********************************************************************************************/
8 
(
9 
        input                                                                                   clk,
10 
        input                                                                                   reset_n,
11 
        input                                                                                   clear,
12 
        input   wire    signed  [DATA_WIDTH_INP - 1:0]  inp_samp_data,
13 
        input                                                                                   inp_samp_str,
14 
        output  reg             signed  [DATA_WIDTH_INP - 1:0]  out_samp_data,
15 
        output  reg                                                                             out_samp_str
16 
);
17 
/*********************************************************************************************/
18 
localparam DECIM_COUNTER_WIDTH = $clog2(CIC_R);
19 
reg [DECIM_COUNTER_WIDTH - 1 : 0] counter;
20 
/*********************************************************************************************/
21 
// decimation counter
22 
always @(posedge clk or negedge reset_n)
23 
begin
24 
        if              (!reset_n)                      counter <= '0;
25 
        else    if (clear)                      counter <= '0;
26 
        else    if (inp_samp_str)       counter <= (counter < CIC_R - 1) ? counter + {{(DECIM_COUNTER_WIDTH - 1){1'b0}}, 1'b1} : '0;
27 
end
28 
/*********************************************************************************************/
29 
// output register
30 
always @(posedge clk or negedge reset_n)
31 
begin
32 
        if              (!reset_n)                      out_samp_data <= '0;
33 
        else    if (clear)                      out_samp_data <= '0;
34 
        else    if (inp_samp_str)       out_samp_data <= (counter < CIC_R - 1) ? out_samp_data : inp_samp_data;
35 
end
36 
/*********************************************************************************************/
37 
// data valid register
38 
always @(posedge clk or negedge reset_n)
39 
begin
40 
        if              (!reset_n)                      out_samp_str <= 1'b0;
41 
        else    if (clear)                      out_samp_str <= 1'b0;
42 
        else    if (inp_samp_str)       out_samp_str <= (counter == CIC_R - 1);
43 
        else                                            out_samp_str <= 1'b0;
44 
end
45 
/*********************************************************************************************/
46 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.