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[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [integrator.sv] - Blame information for rev 7

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Line No. Rev Author Line
1 7 Juzujka 
`timescale 1ns / 1ns
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module integrator
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/*********************************************************************************************/
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#(parameter DATA_WIDTH_INP = 8 , DATA_WIDTH_OUT = 9)
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/*********************************************************************************************/
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(
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        input                                                                                   clk,
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        input                                                                                   reset_n,
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        input                                                                                   clear,
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    input       wire    signed  [DATA_WIDTH_INP - 1:0]  inp_samp_data,
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    input                                                                                       inp_samp_str,
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    output      reg             signed  [DATA_WIDTH_OUT - 1:0]  out_samp_data
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);
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/*********************************************************************************************/
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                        wire    signed  [DATA_WIDTH_OUT - 1:0]  sum;
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assign #4       sum = out_samp_data + inp_samp_data;    // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
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always @(posedge clk or negedge reset_n)
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begin
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        if                      (!reset_n)              out_samp_data <= '0;
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        else    if      (clear)                 out_samp_data <= '0;
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        else    if      (inp_samp_str)  out_samp_data <= sum;
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end
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/*********************************************************************************************/
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endmodule

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