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[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [integrator.sv] - Blame information for rev 9

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`timescale 1ns / 1ns
module integrator
/*********************************************************************************************/
#(parameter DATA_WIDTH_INP = 8 , DATA_WIDTH_OUT = 9)
/*********************************************************************************************/
(
        input                                                                                   clk,
        input                                                                                   reset_n,
        input                                                                                   clear,
    input       wire    signed  [DATA_WIDTH_INP - 1:0]  inp_samp_data,
    input                                                                                       inp_samp_str,
    output      wire    signed  [DATA_WIDTH_OUT - 1:0]  out_samp_data
);
/*********************************************************************************************/
localparam SUMMER_WIDTH = DATA_WIDTH_INP > DATA_WIDTH_OUT ? DATA_WIDTH_INP : DATA_WIDTH_OUT;
wire    signed  [SUMMER_WIDTH - 1:0]    sum;
reg             signed  [SUMMER_WIDTH - 1:0]    acc_reg;
assign #4       sum = acc_reg + inp_samp_data;  // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
always @(posedge clk or negedge reset_n)
begin
        if                      (!reset_n)              acc_reg <= '0;
        else    if      (clear)                 acc_reg <= '0;
        else    if      (inp_samp_str)  acc_reg <= sum;
end
 
assign out_samp_data = acc_reg[SUMMER_WIDTH - 1 -: DATA_WIDTH_OUT];
/*********************************************************************************************/
endmodule

Line No.	Rev	Author	Line
1	7	Juzujka	`timescale 1ns / 1ns
2			`module integrator`
3			`/*********************************************************************************************/`
4			`#(parameter DATA_WIDTH_INP = 8 , DATA_WIDTH_OUT = 9)`
5			`/*********************************************************************************************/`
6			`(`
7			`input clk,`
8			`input reset_n,`
9			`input clear,`
10			`input wire signed [DATA_WIDTH_INP - 1:0] inp_samp_data,`
11			`input inp_samp_str,`
12	9	Juzujka	`output wire signed [DATA_WIDTH_OUT - 1:0] out_samp_data`
13	7	Juzujka	`);`
14			`/*********************************************************************************************/`
15	9	Juzujka	`localparam SUMMER_WIDTH = DATA_WIDTH_INP > DATA_WIDTH_OUT ? DATA_WIDTH_INP : DATA_WIDTH_OUT;`
16			`wire signed [SUMMER_WIDTH - 1:0] sum;`
17			`reg signed [SUMMER_WIDTH - 1:0] acc_reg;`
18			`assign #4 sum = acc_reg + inp_samp_data; // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns`
19	7	Juzujka	`always @(posedge clk or negedge reset_n)`
20			`begin`
21	9	Juzujka	`if (!reset_n) acc_reg <= '0;`
22			`else if (clear) acc_reg <= '0;`
23			`else if (inp_samp_str) acc_reg <= sum;`
24	7	Juzujka	`end`
25	9	Juzujka
26			`assign out_samp_data = acc_reg[SUMMER_WIDTH - 1 -: DATA_WIDTH_OUT];`
27	7	Juzujka	`/*********************************************************************************************/`
28			`endmodule`

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[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [integrator.sv] - Blame information for rev 9