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1 2 conte 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's Debug Unit                                         ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Basic OR1200 debug unit.                                    ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - make it smaller and faster                               ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: not supported by cvs2svn $
47 
// Revision 1.10  2004/04/05 08:29:57  lampret
48 
// Merged branch_qmem into main tree.
49 
//
50 
// Revision 1.9.4.4  2004/02/11 01:40:11  lampret
51 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
52 
//
53 
// Revision 1.9.4.3  2004/01/18 10:08:00  simons
54 
// Error fixed.
55 
//
56 
// Revision 1.9.4.2  2004/01/17 21:14:14  simons
57 
// Errors fixed.
58 
//
59 
// Revision 1.9.4.1  2004/01/15 06:46:38  markom
60 
// interface to debug changed; no more opselect; stb-ack protocol
61 
//
62 
// Revision 1.9  2003/01/22 03:23:47  lampret
63 
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
64 
//
65 
// Revision 1.8  2002/09/08 19:31:52  lampret
66 
// Fixed a typo, reported by Taylor Su.
67 
//
68 
// Revision 1.7  2002/07/14 22:17:17  lampret
69 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
70 
//
71 
// Revision 1.6  2002/03/14 00:30:24  lampret
72 
// Added alternative for critical path in DU.
73 
//
74 
// Revision 1.5  2002/02/11 04:33:17  lampret
75 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
76 
//
77 
// Revision 1.4  2002/01/28 01:16:00  lampret
78 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
79 
//
80 
// Revision 1.3  2002/01/18 07:56:00  lampret
81 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
82 
//
83 
// Revision 1.2  2002/01/14 06:18:22  lampret
84 
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
85 
//
86 
// Revision 1.1  2002/01/03 08:16:15  lampret
87 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
88 
//
89 
// Revision 1.12  2001/11/30 18:58:00  simons
90 
// Trap insn couses break after exits ex_insn.
91 
//
92 
// Revision 1.11  2001/11/23 08:38:51  lampret
93 
// Changed DSR/DRR behavior and exception detection.
94 
//
95 
// Revision 1.10  2001/11/20 21:25:44  lampret
96 
// Fixed dbg_is_o assignment width.
97 
//
98 
// Revision 1.9  2001/11/20 18:46:14  simons
99 
// Break point bug fixed
100 
//
101 
// Revision 1.8  2001/11/18 08:36:28  lampret
102 
// For GDB changed single stepping and disabled trap exception.
103 
//
104 
// Revision 1.7  2001/10/21 18:09:53  lampret
105 
// Fixed sensitivity list.
106 
//
107 
// Revision 1.6  2001/10/14 13:12:09  lampret
108 
// MP3 version.
109 
//
110 
//
111 
 
112 
// synopsys translate_off
113 
`include "timescale.v"
114 
// synopsys translate_on
115 
`include "or1200_defines.v"
116 
 
117 
//
118 
// Debug unit
119 
//
120 
 
121 
module or1200_du(
122 
        // RISC Internal Interface
123 
        clk, rst,
124 
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
125 
        dcpu_dat_dc, icpu_cycstb_i,
126 
        ex_freeze, branch_op, ex_insn, id_pc,
127 
        spr_dat_npc, rf_dataw,
128 
        du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
129 
        du_read, du_write, du_except, du_hwbkpt,
130 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
131 
 
132 
        // External Debug Interface
133 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
134 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
135 
);
136 
 
137 
parameter dw = 32; // `OR1200_OPERAND_WIDTH;
138 
parameter aw = 32; // `OR1200_OPERAND_WIDTH;
139 
 
140 
//
141 
// I/O
142 
//
143 
 
144 
//
145 
// RISC Internal Interface
146 
//
147 
input                           clk;            // Clock
148 
input                           rst;            // Reset
149 
input                           dcpu_cycstb_i;  // LSU status
150 
input                           dcpu_we_i;      // LSU status
151 
input   [31:0]                   dcpu_adr_i;     // LSU addr
152 
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
153 
input   [31:0]                   dcpu_dat_dc;    // LSU load data
154 
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
155 
input                           ex_freeze;      // EX stage freeze
156 
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
157 
input   [dw-1:0]         ex_insn;        // EX insn
158 
input   [31:0]                   id_pc;          // insn fetch EA
159 
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
160 
input   [31:0]                   rf_dataw;       // ALU result (for trace)
161 
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
162 
output                          du_stall;       // Debug Unit Stall
163 
output  [aw-1:0]         du_addr;        // Debug Unit Address
164 
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
165 
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
166 
output                          du_read;        // Debug Unit Read Enable
167 
output                          du_write;       // Debug Unit Write Enable
168 
input   [12:0]                   du_except;      // Exception masked by DSR
169 
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
170 
input                           spr_cs;         // SPR Chip Select
171 
input                           spr_write;      // SPR Read/Write
172 
input   [aw-1:0]         spr_addr;       // SPR Address
173 
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
174 
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
175 
 
176 
//
177 
// External Debug Interface
178 
//
179 
input                   dbg_stall_i;    // External Stall Input
180 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
181 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
182 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
183 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
184 
output                  dbg_bp_o;       // Breakpoint Output
185 
input                   dbg_stb_i;      // External Address/Data Strobe
186 
input                   dbg_we_i;       // External Write Enable
187 
input   [aw-1:0] dbg_adr_i;      // External Address Input
188 
input   [dw-1:0] dbg_dat_i;      // External Data Input
189 
output  [dw-1:0] dbg_dat_o;      // External Data Output
190 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
191 
 
192 
 
193 
//
194 
// Some connections go directly from the CPU through DU to Debug I/F
195 
//
196 
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
197 
assign dbg_lss_o = 4'b0000;
198 
 
199 
reg     [1:0]                    dbg_is_o;
200 
//
201 
// Show insn activity (temp, must be removed)
202 
//
203 
always @(posedge clk or posedge rst)
204 
        if (rst)
205 
                dbg_is_o <=  2'b00;
206 
        else if (!ex_freeze &
207 
                ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
208 
                dbg_is_o <=  ~dbg_is_o;
209 
`ifdef UNUSED
210 
assign dbg_is_o = 2'b00;
211 
`endif
212 
`else
213 
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
214 
assign dbg_is_o = {1'b0, icpu_cycstb_i};
215 
`endif
216 
assign dbg_wp_o = 11'b000_0000_0000;
217 
assign dbg_dat_o = du_dat_i;
218 
 
219 
//
220 
// Some connections go directly from Debug I/F through DU to the CPU
221 
//
222 
assign du_stall = dbg_stall_i;
223 
assign du_addr = dbg_adr_i;
224 
assign du_dat_o = dbg_dat_i;
225 
assign du_read = dbg_stb_i && !dbg_we_i;
226 
assign du_write = dbg_stb_i && dbg_we_i;
227 
 
228 
//
229 
// Generate acknowledge -- just delay stb signal
230 
//
231 
reg dbg_ack_o;
232 
always @(posedge clk or posedge rst)
233 
        if (rst)
234 
                dbg_ack_o <=  1'b0;
235 
        else
236 
                dbg_ack_o <=  dbg_stb_i;
237 
 
238 
`ifdef OR1200_DU_IMPLEMENTED
239 
 
240 
//
241 
// Debug Mode Register 1
242 
//
243 
`ifdef OR1200_DU_DMR1
244 
reg     [24:0]                   dmr1;           // DMR1 implemented
245 
`else
246 
wire    [24:0]                   dmr1;           // DMR1 not implemented
247 
`endif
248 
 
249 
//
250 
// Debug Mode Register 2
251 
//
252 
`ifdef OR1200_DU_DMR2
253 
reg     [23:0]                   dmr2;           // DMR2 implemented
254 
`else
255 
wire    [23:0]                   dmr2;           // DMR2 not implemented
256 
`endif
257 
 
258 
//
259 
// Debug Stop Register
260 
//
261 
`ifdef OR1200_DU_DSR
262 
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
263 
`else
264 
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
265 
`endif
266 
 
267 
//
268 
// Debug Reason Register
269 
//
270 
`ifdef OR1200_DU_DRR
271 
reg     [13:0]                   drr;            // DRR implemented
272 
`else
273 
wire    [13:0]                   drr;            // DRR not implemented
274 
`endif
275 
 
276 
//
277 
// Debug Value Register N
278 
//
279 
`ifdef OR1200_DU_DVR0
280 
reg     [31:0]                   dvr0;
281 
`else
282 
wire    [31:0]                   dvr0;
283 
`endif
284 
 
285 
//
286 
// Debug Value Register N
287 
//
288 
`ifdef OR1200_DU_DVR1
289 
reg     [31:0]                   dvr1;
290 
`else
291 
wire    [31:0]                   dvr1;
292 
`endif
293 
 
294 
//
295 
// Debug Value Register N
296 
//
297 
`ifdef OR1200_DU_DVR2
298 
reg     [31:0]                   dvr2;
299 
`else
300 
wire    [31:0]                   dvr2;
301 
`endif
302 
 
303 
//
304 
// Debug Value Register N
305 
//
306 
`ifdef OR1200_DU_DVR3
307 
reg     [31:0]                   dvr3;
308 
`else
309 
wire    [31:0]                   dvr3;
310 
`endif
311 
 
312 
//
313 
// Debug Value Register N
314 
//
315 
`ifdef OR1200_DU_DVR4
316 
reg     [31:0]                   dvr4;
317 
`else
318 
wire    [31:0]                   dvr4;
319 
`endif
320 
 
321 
//
322 
// Debug Value Register N
323 
//
324 
`ifdef OR1200_DU_DVR5
325 
reg     [31:0]                   dvr5;
326 
`else
327 
wire    [31:0]                   dvr5;
328 
`endif
329 
 
330 
//
331 
// Debug Value Register N
332 
//
333 
`ifdef OR1200_DU_DVR6
334 
reg     [31:0]                   dvr6;
335 
`else
336 
wire    [31:0]                   dvr6;
337 
`endif
338 
 
339 
//
340 
// Debug Value Register N
341 
//
342 
`ifdef OR1200_DU_DVR7
343 
reg     [31:0]                   dvr7;
344 
`else
345 
wire    [31:0]                   dvr7;
346 
`endif
347 
 
348 
//
349 
// Debug Control Register N
350 
//
351 
`ifdef OR1200_DU_DCR0
352 
reg     [7:0]                    dcr0;
353 
`else
354 
wire    [7:0]                    dcr0;
355 
`endif
356 
 
357 
//
358 
// Debug Control Register N
359 
//
360 
`ifdef OR1200_DU_DCR1
361 
reg     [7:0]                    dcr1;
362 
`else
363 
wire    [7:0]                    dcr1;
364 
`endif
365 
 
366 
//
367 
// Debug Control Register N
368 
//
369 
`ifdef OR1200_DU_DCR2
370 
reg     [7:0]                    dcr2;
371 
`else
372 
wire    [7:0]                    dcr2;
373 
`endif
374 
 
375 
//
376 
// Debug Control Register N
377 
//
378 
`ifdef OR1200_DU_DCR3
379 
reg     [7:0]                    dcr3;
380 
`else
381 
wire    [7:0]                    dcr3;
382 
`endif
383 
 
384 
//
385 
// Debug Control Register N
386 
//
387 
`ifdef OR1200_DU_DCR4
388 
reg     [7:0]                    dcr4;
389 
`else
390 
wire    [7:0]                    dcr4;
391 
`endif
392 
 
393 
//
394 
// Debug Control Register N
395 
//
396 
`ifdef OR1200_DU_DCR5
397 
reg     [7:0]                    dcr5;
398 
`else
399 
wire    [7:0]                    dcr5;
400 
`endif
401 
 
402 
//
403 
// Debug Control Register N
404 
//
405 
`ifdef OR1200_DU_DCR6
406 
reg     [7:0]                    dcr6;
407 
`else
408 
wire    [7:0]                    dcr6;
409 
`endif
410 
 
411 
//
412 
// Debug Control Register N
413 
//
414 
`ifdef OR1200_DU_DCR7
415 
reg     [7:0]                    dcr7;
416 
`else
417 
wire    [7:0]                    dcr7;
418 
`endif
419 
 
420 
//
421 
// Debug Watchpoint Counter Register 0
422 
//
423 
`ifdef OR1200_DU_DWCR0
424 
reg     [31:0]                   dwcr0;
425 
`else
426 
wire    [31:0]                   dwcr0;
427 
`endif
428 
 
429 
//
430 
// Debug Watchpoint Counter Register 1
431 
//
432 
`ifdef OR1200_DU_DWCR1
433 
reg     [31:0]                   dwcr1;
434 
`else
435 
wire    [31:0]                   dwcr1;
436 
`endif
437 
 
438 
//
439 
// Internal wires
440 
//
441 
wire                            dmr1_sel;       // DMR1 select
442 
wire                            dmr2_sel;       // DMR2 select
443 
wire                            dsr_sel;        // DSR select
444 
wire                            drr_sel;        // DRR select
445 
wire                            dvr0_sel,
446 
                                dvr1_sel,
447 
                                dvr2_sel,
448 
                                dvr3_sel,
449 
                                dvr4_sel,
450 
                                dvr5_sel,
451 
                                dvr6_sel,
452 
                                dvr7_sel;       // DVR selects
453 
wire                            dcr0_sel,
454 
                                dcr1_sel,
455 
                                dcr2_sel,
456 
                                dcr3_sel,
457 
                                dcr4_sel,
458 
                                dcr5_sel,
459 
                                dcr6_sel,
460 
                                dcr7_sel;       // DCR selects
461 
wire                            dwcr0_sel,
462 
                                dwcr1_sel;      // DWCR selects
463 
reg                             dbg_bp_r;
464 
`ifdef OR1200_DU_HWBKPTS
465 
reg     [31:0]                   match_cond0_ct;
466 
reg     [31:0]                   match_cond1_ct;
467 
reg     [31:0]                   match_cond2_ct;
468 
reg     [31:0]                   match_cond3_ct;
469 
reg     [31:0]                   match_cond4_ct;
470 
reg     [31:0]                   match_cond5_ct;
471 
reg     [31:0]                   match_cond6_ct;
472 
reg     [31:0]                   match_cond7_ct;
473 
reg                             match_cond0_stb;
474 
reg                             match_cond1_stb;
475 
reg                             match_cond2_stb;
476 
reg                             match_cond3_stb;
477 
reg                             match_cond4_stb;
478 
reg                             match_cond5_stb;
479 
reg                             match_cond6_stb;
480 
reg                             match_cond7_stb;
481 
reg                             match0;
482 
reg                             match1;
483 
reg                             match2;
484 
reg                             match3;
485 
reg                             match4;
486 
reg                             match5;
487 
reg                             match6;
488 
reg                             match7;
489 
reg                             wpcntr0_match;
490 
reg                             wpcntr1_match;
491 
reg                             incr_wpcntr0;
492 
reg                             incr_wpcntr1;
493 
reg     [10:0]                   wp;
494 
`endif
495 
wire                            du_hwbkpt;
496 
`ifdef OR1200_DU_READREGS
497 
reg     [31:0]                   spr_dat_o;
498 
`endif
499 
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
500 
`ifdef OR1200_DU_TB_IMPLEMENTED
501 
wire                            tb_enw;
502 
reg     [7:0]                    tb_wadr;
503 
reg [31:0]                       tb_timstmp;
504 
`endif
505 
wire    [31:0]                   tbia_dat_o;
506 
wire    [31:0]                   tbim_dat_o;
507 
wire    [31:0]                   tbar_dat_o;
508 
wire    [31:0]                   tbts_dat_o;
509 
 
510 
//
511 
// DU registers address decoder
512 
//
513 
`ifdef OR1200_DU_DMR1
514 
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
515 
`endif
516 
`ifdef OR1200_DU_DMR2
517 
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
518 
`endif
519 
`ifdef OR1200_DU_DSR
520 
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
521 
`endif
522 
`ifdef OR1200_DU_DRR
523 
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
524 
`endif
525 
`ifdef OR1200_DU_DVR0
526 
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
527 
`endif
528 
`ifdef OR1200_DU_DVR1
529 
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
530 
`endif
531 
`ifdef OR1200_DU_DVR2
532 
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
533 
`endif
534 
`ifdef OR1200_DU_DVR3
535 
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
536 
`endif
537 
`ifdef OR1200_DU_DVR4
538 
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
539 
`endif
540 
`ifdef OR1200_DU_DVR5
541 
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
542 
`endif
543 
`ifdef OR1200_DU_DVR6
544 
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
545 
`endif
546 
`ifdef OR1200_DU_DVR7
547 
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
548 
`endif
549 
`ifdef OR1200_DU_DCR0
550 
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
551 
`endif
552 
`ifdef OR1200_DU_DCR1
553 
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
554 
`endif
555 
`ifdef OR1200_DU_DCR2
556 
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
557 
`endif
558 
`ifdef OR1200_DU_DCR3
559 
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
560 
`endif
561 
`ifdef OR1200_DU_DCR4
562 
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
563 
`endif
564 
`ifdef OR1200_DU_DCR5
565 
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
566 
`endif
567 
`ifdef OR1200_DU_DCR6
568 
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
569 
`endif
570 
`ifdef OR1200_DU_DCR7
571 
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
572 
`endif
573 
`ifdef OR1200_DU_DWCR0
574 
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
575 
`endif
576 
`ifdef OR1200_DU_DWCR1
577 
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
578 
`endif
579 
 
580 
//
581 
// Decode started exception
582 
//
583 
always @(du_except) begin
584 
        except_stop = 14'b0000_0000_0000;
585 
        casex (du_except)
586 
                13'b1_xxxx_xxxx_xxxx:
587 
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
588 
                13'b0_1xxx_xxxx_xxxx: begin
589 
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
590 
                end
591 
                13'b0_01xx_xxxx_xxxx: begin
592 
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
593 
                end
594 
                13'b0_001x_xxxx_xxxx:
595 
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
596 
                13'b0_0001_xxxx_xxxx: begin
597 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
598 
                end
599 
                13'b0_0000_1xxx_xxxx:
600 
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
601 
                13'b0_0000_01xx_xxxx: begin
602 
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
603 
                end
604 
                13'b0_0000_001x_xxxx: begin
605 
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
606 
                end
607 
                13'b0_0000_0001_xxxx:
608 
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
609 
                13'b0_0000_0000_1xxx:
610 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
611 
                13'b0_0000_0000_01xx: begin
612 
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
613 
                end
614 
                13'b0_0000_0000_001x: begin
615 
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
616 
                end
617 
                13'b0_0000_0000_0001:
618 
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
619 
                default:
620 
                        except_stop = 14'b0000_0000_0000;
621 
        endcase
622 
end
623 
 
624 
//
625 
// dbg_bp_o is registered
626 
//
627 
assign dbg_bp_o = dbg_bp_r;
628 
 
629 
//
630 
// Breakpoint activation register
631 
//
632 
always @(posedge clk or posedge rst)
633 
        if (rst)
634 
                dbg_bp_r <=  1'b0;
635 
        else if (!ex_freeze)
636 
                dbg_bp_r <=  |except_stop
637 
`ifdef OR1200_DU_DMR1_ST
638 
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
639 
`endif
640 
`ifdef OR1200_DU_DMR1_BT
641 
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
642 
`endif
643 
                        ;
644 
        else
645 
                dbg_bp_r <=  |except_stop;
646 
 
647 
//
648 
// Write to DMR1
649 
//
650 
`ifdef OR1200_DU_DMR1
651 
always @(posedge clk or posedge rst)
652 
        if (rst)
653 
                dmr1 <= 25'h000_0000;
654 
        else if (dmr1_sel && spr_write)
655 
`ifdef OR1200_DU_HWBKPTS
656 
                dmr1 <=  spr_dat_i[24:0];
657 
`else
658 
                dmr1 <=  {1'b0, spr_dat_i[23:22], 22'h00_0000};
659 
`endif
660 
`else
661 
assign dmr1 = 25'h000_0000;
662 
`endif
663 
 
664 
//
665 
// Write to DMR2
666 
//
667 
`ifdef OR1200_DU_DMR2
668 
always @(posedge clk or posedge rst)
669 
        if (rst)
670 
                dmr2 <= 24'h00_0000;
671 
        else if (dmr2_sel && spr_write)
672 
                dmr2 <=  spr_dat_i[23:0];
673 
`else
674 
assign dmr2 = 24'h00_0000;
675 
`endif
676 
 
677 
//
678 
// Write to DSR
679 
//
680 
`ifdef OR1200_DU_DSR
681 
always @(posedge clk or posedge rst)
682 
        if (rst)
683 
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
684 
        else if (dsr_sel && spr_write)
685 
                dsr <=  spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
686 
`else
687 
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
688 
`endif
689 
 
690 
//
691 
// Write to DRR
692 
//
693 
`ifdef OR1200_DU_DRR
694 
always @(posedge clk or posedge rst)
695 
        if (rst)
696 
                drr <= 14'b0;
697 
        else if (drr_sel && spr_write)
698 
                drr <=  spr_dat_i[13:0];
699 
        else
700 
                drr <=  drr | except_stop;
701 
`else
702 
assign drr = 14'b0;
703 
`endif
704 
 
705 
//
706 
// Write to DVR0
707 
//
708 
`ifdef OR1200_DU_DVR0
709 
always @(posedge clk or posedge rst)
710 
        if (rst)
711 
                dvr0 <= 32'h0000_0000;
712 
        else if (dvr0_sel && spr_write)
713 
                dvr0 <=  spr_dat_i[31:0];
714 
`else
715 
assign dvr0 = 32'h0000_0000;
716 
`endif
717 
 
718 
//
719 
// Write to DVR1
720 
//
721 
`ifdef OR1200_DU_DVR1
722 
always @(posedge clk or posedge rst)
723 
        if (rst)
724 
                dvr1 <= 32'h0000_0000;
725 
        else if (dvr1_sel && spr_write)
726 
                dvr1 <=  spr_dat_i[31:0];
727 
`else
728 
assign dvr1 = 32'h0000_0000;
729 
`endif
730 
 
731 
//
732 
// Write to DVR2
733 
//
734 
`ifdef OR1200_DU_DVR2
735 
always @(posedge clk or posedge rst)
736 
        if (rst)
737 
                dvr2 <= 32'h0000_0000;
738 
        else if (dvr2_sel && spr_write)
739 
                dvr2 <=  spr_dat_i[31:0];
740 
`else
741 
assign dvr2 = 32'h0000_0000;
742 
`endif
743 
 
744 
//
745 
// Write to DVR3
746 
//
747 
`ifdef OR1200_DU_DVR3
748 
always @(posedge clk or posedge rst)
749 
        if (rst)
750 
                dvr3 <= 32'h0000_0000;
751 
        else if (dvr3_sel && spr_write)
752 
                dvr3 <=  spr_dat_i[31:0];
753 
`else
754 
assign dvr3 = 32'h0000_0000;
755 
`endif
756 
 
757 
//
758 
// Write to DVR4
759 
//
760 
`ifdef OR1200_DU_DVR4
761 
always @(posedge clk or posedge rst)
762 
        if (rst)
763 
                dvr4 <= 32'h0000_0000;
764 
        else if (dvr4_sel && spr_write)
765 
                dvr4 <=  spr_dat_i[31:0];
766 
`else
767 
assign dvr4 = 32'h0000_0000;
768 
`endif
769 
 
770 
//
771 
// Write to DVR5
772 
//
773 
`ifdef OR1200_DU_DVR5
774 
always @(posedge clk or posedge rst)
775 
        if (rst)
776 
                dvr5 <= 32'h0000_0000;
777 
        else if (dvr5_sel && spr_write)
778 
                dvr5 <=  spr_dat_i[31:0];
779 
`else
780 
assign dvr5 = 32'h0000_0000;
781 
`endif
782 
 
783 
//
784 
// Write to DVR6
785 
//
786 
`ifdef OR1200_DU_DVR6
787 
always @(posedge clk or posedge rst)
788 
        if (rst)
789 
                dvr6 <= 32'h0000_0000;
790 
        else if (dvr6_sel && spr_write)
791 
                dvr6 <=  spr_dat_i[31:0];
792 
`else
793 
assign dvr6 = 32'h0000_0000;
794 
`endif
795 
 
796 
//
797 
// Write to DVR7
798 
//
799 
`ifdef OR1200_DU_DVR7
800 
always @(posedge clk or posedge rst)
801 
        if (rst)
802 
                dvr7 <= 32'h0000_0000;
803 
        else if (dvr7_sel && spr_write)
804 
                dvr7 <=  spr_dat_i[31:0];
805 
`else
806 
assign dvr7 = 32'h0000_0000;
807 
`endif
808 
 
809 
//
810 
// Write to DCR0
811 
//
812 
`ifdef OR1200_DU_DCR0
813 
always @(posedge clk or posedge rst)
814 
        if (rst)
815 
                dcr0 <= 8'h00;
816 
        else if (dcr0_sel && spr_write)
817 
                dcr0 <=  spr_dat_i[7:0];
818 
`else
819 
assign dcr0 = 8'h00;
820 
`endif
821 
 
822 
//
823 
// Write to DCR1
824 
//
825 
`ifdef OR1200_DU_DCR1
826 
always @(posedge clk or posedge rst)
827 
        if (rst)
828 
                dcr1 <= 8'h00;
829 
        else if (dcr1_sel && spr_write)
830 
                dcr1 <=  spr_dat_i[7:0];
831 
`else
832 
assign dcr1 = 8'h00;
833 
`endif
834 
 
835 
//
836 
// Write to DCR2
837 
//
838 
`ifdef OR1200_DU_DCR2
839 
always @(posedge clk or posedge rst)
840 
        if (rst)
841 
                dcr2 <= 8'h00;
842 
        else if (dcr2_sel && spr_write)
843 
                dcr2 <=  spr_dat_i[7:0];
844 
`else
845 
assign dcr2 = 8'h00;
846 
`endif
847 
 
848 
//
849 
// Write to DCR3
850 
//
851 
`ifdef OR1200_DU_DCR3
852 
always @(posedge clk or posedge rst)
853 
        if (rst)
854 
                dcr3 <= 8'h00;
855 
        else if (dcr3_sel && spr_write)
856 
                dcr3 <=  spr_dat_i[7:0];
857 
`else
858 
assign dcr3 = 8'h00;
859 
`endif
860 
 
861 
//
862 
// Write to DCR4
863 
//
864 
`ifdef OR1200_DU_DCR4
865 
always @(posedge clk or posedge rst)
866 
        if (rst)
867 
                dcr4 <= 8'h00;
868 
        else if (dcr4_sel && spr_write)
869 
                dcr4 <=  spr_dat_i[7:0];
870 
`else
871 
assign dcr4 = 8'h00;
872 
`endif
873 
 
874 
//
875 
// Write to DCR5
876 
//
877 
`ifdef OR1200_DU_DCR5
878 
always @(posedge clk or posedge rst)
879 
        if (rst)
880 
                dcr5 <= 8'h00;
881 
        else if (dcr5_sel && spr_write)
882 
                dcr5 <=  spr_dat_i[7:0];
883 
`else
884 
assign dcr5 = 8'h00;
885 
`endif
886 
 
887 
//
888 
// Write to DCR6
889 
//
890 
`ifdef OR1200_DU_DCR6
891 
always @(posedge clk or posedge rst)
892 
        if (rst)
893 
                dcr6 <= 8'h00;
894 
        else if (dcr6_sel && spr_write)
895 
                dcr6 <=  spr_dat_i[7:0];
896 
`else
897 
assign dcr6 = 8'h00;
898 
`endif
899 
 
900 
//
901 
// Write to DCR7
902 
//
903 
`ifdef OR1200_DU_DCR7
904 
always @(posedge clk or posedge rst)
905 
        if (rst)
906 
                dcr7 <= 8'h00;
907 
        else if (dcr7_sel && spr_write)
908 
                dcr7 <=  spr_dat_i[7:0];
909 
`else
910 
assign dcr7 = 8'h00;
911 
`endif
912 
 
913 
//
914 
// Write to DWCR0
915 
//
916 
`ifdef OR1200_DU_DWCR0
917 
always @(posedge clk or posedge rst)
918 
        if (rst)
919 
                dwcr0 <= 32'h0000_0000;
920 
        else if (dwcr0_sel && spr_write)
921 
                dwcr0 <=  spr_dat_i[31:0];
922 
        else if (incr_wpcntr0)
923 
                dwcr0[`OR1200_DU_DWCR_COUNT] <=  dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
924 
`else
925 
assign dwcr0 = 32'h0000_0000;
926 
`endif
927 
 
928 
//
929 
// Write to DWCR1
930 
//
931 
`ifdef OR1200_DU_DWCR1
932 
always @(posedge clk or posedge rst)
933 
        if (rst)
934 
                dwcr1 <= 32'h0000_0000;
935 
        else if (dwcr1_sel && spr_write)
936 
                dwcr1 <=  spr_dat_i[31:0];
937 
        else if (incr_wpcntr1)
938 
                dwcr1[`OR1200_DU_DWCR_COUNT] <=  dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
939 
`else
940 
assign dwcr1 = 32'h0000_0000;
941 
`endif
942 
 
943 
//
944 
// Read DU registers
945 
//
946 
`ifdef OR1200_DU_READREGS
947 
always @(spr_addr or dsr or drr or dmr1 or dmr2
948 
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
949 
        or dvr5 or dvr6 or dvr7
950 
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
951 
        or dcr5 or dcr6 or dcr7
952 
        or dwcr0 or dwcr1
953 
`ifdef OR1200_DU_TB_IMPLEMENTED
954 
        or tb_wadr or tbia_dat_o or tbim_dat_o
955 
        or tbar_dat_o or tbts_dat_o
956 
`endif
957 
        )
958 
        casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
959 
`ifdef OR1200_DU_DVR0
960 
                `OR1200_DU_DVR0:
961 
                        spr_dat_o = dvr0;
962 
`endif
963 
`ifdef OR1200_DU_DVR1
964 
                `OR1200_DU_DVR1:
965 
                        spr_dat_o = dvr1;
966 
`endif
967 
`ifdef OR1200_DU_DVR2
968 
                `OR1200_DU_DVR2:
969 
                        spr_dat_o = dvr2;
970 
`endif
971 
`ifdef OR1200_DU_DVR3
972 
                `OR1200_DU_DVR3:
973 
                        spr_dat_o = dvr3;
974 
`endif
975 
`ifdef OR1200_DU_DVR4
976 
                `OR1200_DU_DVR4:
977 
                        spr_dat_o = dvr4;
978 
`endif
979 
`ifdef OR1200_DU_DVR5
980 
                `OR1200_DU_DVR5:
981 
                        spr_dat_o = dvr5;
982 
`endif
983 
`ifdef OR1200_DU_DVR6
984 
                `OR1200_DU_DVR6:
985 
                        spr_dat_o = dvr6;
986 
`endif
987 
`ifdef OR1200_DU_DVR7
988 
                `OR1200_DU_DVR7:
989 
                        spr_dat_o = dvr7;
990 
`endif
991 
`ifdef OR1200_DU_DCR0
992 
                `OR1200_DU_DCR0:
993 
                        spr_dat_o = {24'h00_0000, dcr0};
994 
`endif
995 
`ifdef OR1200_DU_DCR1
996 
                `OR1200_DU_DCR1:
997 
                        spr_dat_o = {24'h00_0000, dcr1};
998 
`endif
999 
`ifdef OR1200_DU_DCR2
1000 
                `OR1200_DU_DCR2:
1001 
                        spr_dat_o = {24'h00_0000, dcr2};
1002 
`endif
1003 
`ifdef OR1200_DU_DCR3
1004 
                `OR1200_DU_DCR3:
1005 
                        spr_dat_o = {24'h00_0000, dcr3};
1006 
`endif
1007 
`ifdef OR1200_DU_DCR4
1008 
                `OR1200_DU_DCR4:
1009 
                        spr_dat_o = {24'h00_0000, dcr4};
1010 
`endif
1011 
`ifdef OR1200_DU_DCR5
1012 
                `OR1200_DU_DCR5:
1013 
                        spr_dat_o = {24'h00_0000, dcr5};
1014 
`endif
1015 
`ifdef OR1200_DU_DCR6
1016 
                `OR1200_DU_DCR6:
1017 
                        spr_dat_o = {24'h00_0000, dcr6};
1018 
`endif
1019 
`ifdef OR1200_DU_DCR7
1020 
                `OR1200_DU_DCR7:
1021 
                        spr_dat_o = {24'h00_0000, dcr7};
1022 
`endif
1023 
`ifdef OR1200_DU_DMR1
1024 
                `OR1200_DU_DMR1:
1025 
                        spr_dat_o = {7'h00, dmr1};
1026 
`endif
1027 
`ifdef OR1200_DU_DMR2
1028 
                `OR1200_DU_DMR2:
1029 
                        spr_dat_o = {8'h00, dmr2};
1030 
`endif
1031 
`ifdef OR1200_DU_DWCR0
1032 
                `OR1200_DU_DWCR0:
1033 
                        spr_dat_o = dwcr0;
1034 
`endif
1035 
`ifdef OR1200_DU_DWCR1
1036 
                `OR1200_DU_DWCR1:
1037 
                        spr_dat_o = dwcr1;
1038 
`endif
1039 
`ifdef OR1200_DU_DSR
1040 
                `OR1200_DU_DSR:
1041 
                        spr_dat_o = {18'b0, dsr};
1042 
`endif
1043 
`ifdef OR1200_DU_DRR
1044 
                `OR1200_DU_DRR:
1045 
                        spr_dat_o = {18'b0, drr};
1046 
`endif
1047 
`ifdef OR1200_DU_TB_IMPLEMENTED
1048 
                `OR1200_DU_TBADR:
1049 
                        spr_dat_o = {24'h000000, tb_wadr};
1050 
                `OR1200_DU_TBIA:
1051 
                        spr_dat_o = tbia_dat_o;
1052 
                `OR1200_DU_TBIM:
1053 
                        spr_dat_o = tbim_dat_o;
1054 
                `OR1200_DU_TBAR:
1055 
                        spr_dat_o = tbar_dat_o;
1056 
                `OR1200_DU_TBTS:
1057 
                        spr_dat_o = tbts_dat_o;
1058 
`endif
1059 
                default:
1060 
                        spr_dat_o = 32'h0000_0000;
1061 
        endcase
1062 
`endif
1063 
 
1064 
//
1065 
// DSR alias
1066 
//
1067 
assign du_dsr = dsr;
1068 
 
1069 
`ifdef OR1200_DU_HWBKPTS
1070 
 
1071 
//
1072 
// Compare To What (Match Condition 0)
1073 
//
1074 
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1075 
        or dcpu_dat_lsu or dcpu_we_i)
1076 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1077 
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1078 
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1079 
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1080 
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1081 
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1082 
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1083 
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1084 
        endcase
1085 
 
1086 
//
1087 
// When To Compare (Match Condition 0)
1088 
//
1089 
always @(dcr0 or dcpu_cycstb_i)
1090 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1091 
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1092 
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1093 
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1094 
        endcase
1095 
 
1096 
//
1097 
// Match Condition 0
1098 
//
1099 
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1100 
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1101 
                4'b0_xxx,
1102 
                4'b1_000,
1103 
                4'b1_111: match0 = 1'b0;
1104 
                4'b1_001: match0 =
1105 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
1106 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1107 
                4'b1_010: match0 =
1108 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
1109 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1110 
                4'b1_011: match0 =
1111 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
1112 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1113 
                4'b1_100: match0 =
1114 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
1115 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1116 
                4'b1_101: match0 =
1117 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
1118 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1119 
                4'b1_110: match0 =
1120 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
1121 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1122 
        endcase
1123 
 
1124 
//
1125 
// Watchpoint 0
1126 
//
1127 
always @(dmr1 or match0)
1128 
        case (dmr1[`OR1200_DU_DMR1_CW0])
1129 
                2'b00: wp[0] = match0;
1130 
                2'b01: wp[0] = match0;
1131 
                2'b10: wp[0] = match0;
1132 
                2'b11: wp[0] = 1'b0;
1133 
        endcase
1134 
 
1135 
//
1136 
// Compare To What (Match Condition 1)
1137 
//
1138 
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1139 
        or dcpu_dat_lsu or dcpu_we_i)
1140 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1141 
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1142 
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1143 
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1144 
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1145 
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1146 
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1147 
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1148 
        endcase
1149 
 
1150 
//
1151 
// When To Compare (Match Condition 1)
1152 
//
1153 
always @(dcr1 or dcpu_cycstb_i)
1154 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1155 
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1156 
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1157 
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1158 
        endcase
1159 
 
1160 
//
1161 
// Match Condition 1
1162 
//
1163 
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1164 
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1165 
                4'b0_xxx,
1166 
                4'b1_000,
1167 
                4'b1_111: match1 = 1'b0;
1168 
                4'b1_001: match1 =
1169 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
1170 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1171 
                4'b1_010: match1 =
1172 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
1173 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1174 
                4'b1_011: match1 =
1175 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
1176 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1177 
                4'b1_100: match1 =
1178 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
1179 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1180 
                4'b1_101: match1 =
1181 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
1182 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1183 
                4'b1_110: match1 =
1184 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
1185 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1186 
        endcase
1187 
 
1188 
//
1189 
// Watchpoint 1
1190 
//
1191 
always @(dmr1 or match1 or wp)
1192 
        case (dmr1[`OR1200_DU_DMR1_CW1])
1193 
                2'b00: wp[1] = match1;
1194 
                2'b01: wp[1] = match1 & wp[0];
1195 
                2'b10: wp[1] = match1 | wp[0];
1196 
                2'b11: wp[1] = 1'b0;
1197 
        endcase
1198 
 
1199 
//
1200 
// Compare To What (Match Condition 2)
1201 
//
1202 
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1203 
        or dcpu_dat_lsu or dcpu_we_i)
1204 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1205 
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1206 
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1207 
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1208 
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1209 
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1210 
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1211 
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1212 
        endcase
1213 
 
1214 
//
1215 
// When To Compare (Match Condition 2)
1216 
//
1217 
always @(dcr2 or dcpu_cycstb_i)
1218 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1219 
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1220 
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1221 
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1222 
        endcase
1223 
 
1224 
//
1225 
// Match Condition 2
1226 
//
1227 
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1228 
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1229 
                4'b0_xxx,
1230 
                4'b1_000,
1231 
                4'b1_111: match2 = 1'b0;
1232 
                4'b1_001: match2 =
1233 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
1234 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1235 
                4'b1_010: match2 =
1236 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
1237 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1238 
                4'b1_011: match2 =
1239 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
1240 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1241 
                4'b1_100: match2 =
1242 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
1243 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1244 
                4'b1_101: match2 =
1245 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
1246 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1247 
                4'b1_110: match2 =
1248 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
1249 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1250 
        endcase
1251 
 
1252 
//
1253 
// Watchpoint 2
1254 
//
1255 
always @(dmr1 or match2 or wp)
1256 
        case (dmr1[`OR1200_DU_DMR1_CW2])
1257 
                2'b00: wp[2] = match2;
1258 
                2'b01: wp[2] = match2 & wp[1];
1259 
                2'b10: wp[2] = match2 | wp[1];
1260 
                2'b11: wp[2] = 1'b0;
1261 
        endcase
1262 
 
1263 
//
1264 
// Compare To What (Match Condition 3)
1265 
//
1266 
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1267 
        or dcpu_dat_lsu or dcpu_we_i)
1268 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1269 
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1270 
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1271 
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1272 
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1273 
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1274 
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1275 
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1276 
        endcase
1277 
 
1278 
//
1279 
// When To Compare (Match Condition 3)
1280 
//
1281 
always @(dcr3 or dcpu_cycstb_i)
1282 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1283 
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1284 
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1285 
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1286 
        endcase
1287 
 
1288 
//
1289 
// Match Condition 3
1290 
//
1291 
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1292 
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1293 
                4'b0_xxx,
1294 
                4'b1_000,
1295 
                4'b1_111: match3 = 1'b0;
1296 
                4'b1_001: match3 =
1297 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
1298 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1299 
                4'b1_010: match3 =
1300 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
1301 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1302 
                4'b1_011: match3 =
1303 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
1304 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1305 
                4'b1_100: match3 =
1306 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
1307 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1308 
                4'b1_101: match3 =
1309 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
1310 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1311 
                4'b1_110: match3 =
1312 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
1313 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1314 
        endcase
1315 
 
1316 
//
1317 
// Watchpoint 3
1318 
//
1319 
always @(dmr1 or match3 or wp)
1320 
        case (dmr1[`OR1200_DU_DMR1_CW3])
1321 
                2'b00: wp[3] = match3;
1322 
                2'b01: wp[3] = match3 & wp[2];
1323 
                2'b10: wp[3] = match3 | wp[2];
1324 
                2'b11: wp[3] = 1'b0;
1325 
        endcase
1326 
 
1327 
//
1328 
// Compare To What (Match Condition 4)
1329 
//
1330 
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1331 
        or dcpu_dat_lsu or dcpu_we_i)
1332 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1333 
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1334 
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1335 
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1336 
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1337 
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1338 
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1339 
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1340 
        endcase
1341 
 
1342 
//
1343 
// When To Compare (Match Condition 4)
1344 
//
1345 
always @(dcr4 or dcpu_cycstb_i)
1346 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1347 
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1348 
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1349 
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1350 
        endcase
1351 
 
1352 
//
1353 
// Match Condition 4
1354 
//
1355 
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1356 
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1357 
                4'b0_xxx,
1358 
                4'b1_000,
1359 
                4'b1_111: match4 = 1'b0;
1360 
                4'b1_001: match4 =
1361 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
1362 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1363 
                4'b1_010: match4 =
1364 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
1365 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1366 
                4'b1_011: match4 =
1367 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
1368 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1369 
                4'b1_100: match4 =
1370 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
1371 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1372 
                4'b1_101: match4 =
1373 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
1374 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1375 
                4'b1_110: match4 =
1376 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
1377 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1378 
        endcase
1379 
 
1380 
//
1381 
// Watchpoint 4
1382 
//
1383 
always @(dmr1 or match4 or wp)
1384 
        case (dmr1[`OR1200_DU_DMR1_CW4])
1385 
                2'b00: wp[4] = match4;
1386 
                2'b01: wp[4] = match4 & wp[3];
1387 
                2'b10: wp[4] = match4 | wp[3];
1388 
                2'b11: wp[4] = 1'b0;
1389 
        endcase
1390 
 
1391 
//
1392 
// Compare To What (Match Condition 5)
1393 
//
1394 
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1395 
        or dcpu_dat_lsu or dcpu_we_i)
1396 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1397 
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1398 
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1399 
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1400 
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1401 
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1402 
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1403 
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1404 
        endcase
1405 
 
1406 
//
1407 
// When To Compare (Match Condition 5)
1408 
//
1409 
always @(dcr5 or dcpu_cycstb_i)
1410 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1411 
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1412 
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1413 
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1414 
        endcase
1415 
 
1416 
//
1417 
// Match Condition 5
1418 
//
1419 
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1420 
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1421 
                4'b0_xxx,
1422 
                4'b1_000,
1423 
                4'b1_111: match5 = 1'b0;
1424 
                4'b1_001: match5 =
1425 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
1426 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1427 
                4'b1_010: match5 =
1428 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
1429 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1430 
                4'b1_011: match5 =
1431 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
1432 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1433 
                4'b1_100: match5 =
1434 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
1435 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1436 
                4'b1_101: match5 =
1437 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
1438 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1439 
                4'b1_110: match5 =
1440 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
1441 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1442 
        endcase
1443 
 
1444 
//
1445 
// Watchpoint 5
1446 
//
1447 
always @(dmr1 or match5 or wp)
1448 
        case (dmr1[`OR1200_DU_DMR1_CW5])
1449 
                2'b00: wp[5] = match5;
1450 
                2'b01: wp[5] = match5 & wp[4];
1451 
                2'b10: wp[5] = match5 | wp[4];
1452 
                2'b11: wp[5] = 1'b0;
1453 
        endcase
1454 
 
1455 
//
1456 
// Compare To What (Match Condition 6)
1457 
//
1458 
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1459 
        or dcpu_dat_lsu or dcpu_we_i)
1460 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1461 
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1462 
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1463 
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1464 
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1465 
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1466 
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1467 
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1468 
        endcase
1469 
 
1470 
//
1471 
// When To Compare (Match Condition 6)
1472 
//
1473 
always @(dcr6 or dcpu_cycstb_i)
1474 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1475 
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1476 
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1477 
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1478 
        endcase
1479 
 
1480 
//
1481 
// Match Condition 6
1482 
//
1483 
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1484 
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1485 
                4'b0_xxx,
1486 
                4'b1_000,
1487 
                4'b1_111: match6 = 1'b0;
1488 
                4'b1_001: match6 =
1489 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
1490 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1491 
                4'b1_010: match6 =
1492 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
1493 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1494 
                4'b1_011: match6 =
1495 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
1496 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1497 
                4'b1_100: match6 =
1498 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
1499 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1500 
                4'b1_101: match6 =
1501 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
1502 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1503 
                4'b1_110: match6 =
1504 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
1505 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1506 
        endcase
1507 
 
1508 
//
1509 
// Watchpoint 6
1510 
//
1511 
always @(dmr1 or match6 or wp)
1512 
        case (dmr1[`OR1200_DU_DMR1_CW6])
1513 
                2'b00: wp[6] = match6;
1514 
                2'b01: wp[6] = match6 & wp[5];
1515 
                2'b10: wp[6] = match6 | wp[5];
1516 
                2'b11: wp[6] = 1'b0;
1517 
        endcase
1518 
 
1519 
//
1520 
// Compare To What (Match Condition 7)
1521 
//
1522 
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1523 
        or dcpu_dat_lsu or dcpu_we_i)
1524 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1525 
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1526 
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1527 
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1528 
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1529 
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1530 
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1531 
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1532 
        endcase
1533 
 
1534 
//
1535 
// When To Compare (Match Condition 7)
1536 
//
1537 
always @(dcr7 or dcpu_cycstb_i)
1538 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1539 
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1540 
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1541 
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1542 
        endcase
1543 
 
1544 
//
1545 
// Match Condition 7
1546 
//
1547 
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1548 
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1549 
                4'b0_xxx,
1550 
                4'b1_000,
1551 
                4'b1_111: match7 = 1'b0;
1552 
                4'b1_001: match7 =
1553 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
1554 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1555 
                4'b1_010: match7 =
1556 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
1557 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1558 
                4'b1_011: match7 =
1559 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
1560 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1561 
                4'b1_100: match7 =
1562 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
1563 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1564 
                4'b1_101: match7 =
1565 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
1566 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1567 
                4'b1_110: match7 =
1568 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
1569 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1570 
        endcase
1571 
 
1572 
//
1573 
// Watchpoint 7
1574 
//
1575 
always @(dmr1 or match7 or wp)
1576 
        case (dmr1[`OR1200_DU_DMR1_CW7])
1577 
                2'b00: wp[7] = match7;
1578 
                2'b01: wp[7] = match7 & wp[6];
1579 
                2'b10: wp[7] = match7 | wp[6];
1580 
                2'b11: wp[7] = 1'b0;
1581 
        endcase
1582 
 
1583 
//
1584 
// Increment Watchpoint Counter 0
1585 
//
1586 
always @(wp or dmr2)
1587 
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1588 
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1589 
        else
1590 
                incr_wpcntr0 = 1'b0;
1591 
 
1592 
//
1593 
// Match Condition Watchpoint Counter 0
1594 
//
1595 
always @(dwcr0)
1596 
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1597 
                wpcntr0_match = 1'b1;
1598 
        else
1599 
                wpcntr0_match = 1'b0;
1600 
 
1601 
 
1602 
//
1603 
// Watchpoint 8
1604 
//
1605 
always @(dmr1 or wpcntr0_match or wp)
1606 
        case (dmr1[`OR1200_DU_DMR1_CW8])
1607 
                2'b00: wp[8] = wpcntr0_match;
1608 
                2'b01: wp[8] = wpcntr0_match & wp[7];
1609 
                2'b10: wp[8] = wpcntr0_match | wp[7];
1610 
                2'b11: wp[8] = 1'b0;
1611 
        endcase
1612 
 
1613 
 
1614 
//
1615 
// Increment Watchpoint Counter 1
1616 
//
1617 
always @(wp or dmr2)
1618 
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1619 
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1620 
        else
1621 
                incr_wpcntr1 = 1'b0;
1622 
 
1623 
//
1624 
// Match Condition Watchpoint Counter 1
1625 
//
1626 
always @(dwcr1)
1627 
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1628 
                wpcntr1_match = 1'b1;
1629 
        else
1630 
                wpcntr1_match = 1'b0;
1631 
 
1632 
//
1633 
// Watchpoint 9
1634 
//
1635 
always @(dmr1 or wpcntr1_match or wp)
1636 
        case (dmr1[`OR1200_DU_DMR1_CW9])
1637 
                2'b00: wp[9] = wpcntr1_match;
1638 
                2'b01: wp[9] = wpcntr1_match & wp[8];
1639 
                2'b10: wp[9] = wpcntr1_match | wp[8];
1640 
                2'b11: wp[9] = 1'b0;
1641 
        endcase
1642 
 
1643 
//
1644 
// Watchpoint 10
1645 
//
1646 
always @(dmr1 or dbg_ewt_i or wp)
1647 
        case (dmr1[`OR1200_DU_DMR1_CW10])
1648 
                2'b00: wp[10] = dbg_ewt_i;
1649 
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1650 
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1651 
                2'b11: wp[10] = 1'b0;
1652 
        endcase
1653 
 
1654 
`endif
1655 
 
1656 
//
1657 
// Watchpoints can cause trap exception
1658 
//
1659 
`ifdef OR1200_DU_HWBKPTS
1660 
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
1661 
`else
1662 
assign du_hwbkpt = 1'b0;
1663 
`endif
1664 
 
1665 
`ifdef OR1200_DU_TB_IMPLEMENTED
1666 
//
1667 
// Simple trace buffer
1668 
// (right now hardcoded for Xilinx Virtex FPGAs)
1669 
//
1670 
// Stores last 256 instruction addresses, instruction
1671 
// machine words and ALU results
1672 
//
1673 
 
1674 
//
1675 
// Trace buffer write enable
1676 
//
1677 
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1678 
 
1679 
//
1680 
// Trace buffer write address pointer
1681 
//
1682 
always @(posedge clk or posedge rst)
1683 
        if (rst)
1684 
                tb_wadr <=  8'h00;
1685 
        else if (tb_enw)
1686 
                tb_wadr <=  tb_wadr + 8'd1;
1687 
 
1688 
//
1689 
// Free running counter (time stamp)
1690 
//
1691 
always @(posedge clk or posedge rst)
1692 
        if (rst)
1693 
                tb_timstmp <=  32'h00000000;
1694 
        else if (!dbg_bp_r)
1695 
                tb_timstmp <=  tb_timstmp + 32'd1;
1696 
 
1697 
//
1698 
// Trace buffer RAMs
1699 
//
1700 
RAMB4_S16_S16 tbia_ramb4_s16_0(
1701 
        .CLKA(clk),
1702 
        .RSTA(rst),
1703 
        .ADDRA(tb_wadr),
1704 
        .DIA(spr_dat_npc[15:0]),
1705 
        .ENA(1'b1),
1706 
        .WEA(tb_enw),
1707 
        .DOA(),
1708 
 
1709 
        .CLKB(clk),
1710 
        .RSTB(rst),
1711 
        .ADDRB(spr_addr[7:0]),
1712 
        .DIB(16'h0000),
1713 
        .ENB(1'b1),
1714 
        .WEB(1'b0),
1715 
        .DOB(tbia_dat_o[15:0])
1716 
);
1717 
 
1718 
RAMB4_S16_S16 tbia_ramb4_s16_1(
1719 
        .CLKA(clk),
1720 
        .RSTA(rst),
1721 
        .ADDRA(tb_wadr),
1722 
        .DIA(spr_dat_npc[31:16]),
1723 
        .ENA(1'b1),
1724 
        .WEA(tb_enw),
1725 
        .DOA(),
1726 
 
1727 
        .CLKB(clk),
1728 
        .RSTB(rst),
1729 
        .ADDRB(spr_addr[7:0]),
1730 
        .DIB(16'h0000),
1731 
        .ENB(1'b1),
1732 
        .WEB(1'b0),
1733 
        .DOB(tbia_dat_o[31:16])
1734 
);
1735 
 
1736 
RAMB4_S16_S16 tbim_ramb4_s16_0(
1737 
        .CLKA(clk),
1738 
        .RSTA(rst),
1739 
        .ADDRA(tb_wadr),
1740 
        .DIA(ex_insn[15:0]),
1741 
        .ENA(1'b1),
1742 
        .WEA(tb_enw),
1743 
        .DOA(),
1744 
 
1745 
        .CLKB(clk),
1746 
        .RSTB(rst),
1747 
        .ADDRB(spr_addr[7:0]),
1748 
        .DIB(16'h0000),
1749 
        .ENB(1'b1),
1750 
        .WEB(1'b0),
1751 
        .DOB(tbim_dat_o[15:0])
1752 
);
1753 
 
1754 
RAMB4_S16_S16 tbim_ramb4_s16_1(
1755 
        .CLKA(clk),
1756 
        .RSTA(rst),
1757 
        .ADDRA(tb_wadr),
1758 
        .DIA(ex_insn[31:16]),
1759 
        .ENA(1'b1),
1760 
        .WEA(tb_enw),
1761 
        .DOA(),
1762 
 
1763 
        .CLKB(clk),
1764 
        .RSTB(rst),
1765 
        .ADDRB(spr_addr[7:0]),
1766 
        .DIB(16'h0000),
1767 
        .ENB(1'b1),
1768 
        .WEB(1'b0),
1769 
        .DOB(tbim_dat_o[31:16])
1770 
);
1771 
 
1772 
RAMB4_S16_S16 tbar_ramb4_s16_0(
1773 
        .CLKA(clk),
1774 
        .RSTA(rst),
1775 
        .ADDRA(tb_wadr),
1776 
        .DIA(rf_dataw[15:0]),
1777 
        .ENA(1'b1),
1778 
        .WEA(tb_enw),
1779 
        .DOA(),
1780 
 
1781 
        .CLKB(clk),
1782 
        .RSTB(rst),
1783 
        .ADDRB(spr_addr[7:0]),
1784 
        .DIB(16'h0000),
1785 
        .ENB(1'b1),
1786 
        .WEB(1'b0),
1787 
        .DOB(tbar_dat_o[15:0])
1788 
);
1789 
 
1790 
RAMB4_S16_S16 tbar_ramb4_s16_1(
1791 
        .CLKA(clk),
1792 
        .RSTA(rst),
1793 
        .ADDRA(tb_wadr),
1794 
        .DIA(rf_dataw[31:16]),
1795 
        .ENA(1'b1),
1796 
        .WEA(tb_enw),
1797 
        .DOA(),
1798 
 
1799 
        .CLKB(clk),
1800 
        .RSTB(rst),
1801 
        .ADDRB(spr_addr[7:0]),
1802 
        .DIB(16'h0000),
1803 
        .ENB(1'b1),
1804 
        .WEB(1'b0),
1805 
        .DOB(tbar_dat_o[31:16])
1806 
);
1807 
 
1808 
RAMB4_S16_S16 tbts_ramb4_s16_0(
1809 
        .CLKA(clk),
1810 
        .RSTA(rst),
1811 
        .ADDRA(tb_wadr),
1812 
        .DIA(tb_timstmp[15:0]),
1813 
        .ENA(1'b1),
1814 
        .WEA(tb_enw),
1815 
        .DOA(),
1816 
 
1817 
        .CLKB(clk),
1818 
        .RSTB(rst),
1819 
        .ADDRB(spr_addr[7:0]),
1820 
        .DIB(16'h0000),
1821 
        .ENB(1'b1),
1822 
        .WEB(1'b0),
1823 
        .DOB(tbts_dat_o[15:0])
1824 
);
1825 
 
1826 
RAMB4_S16_S16 tbts_ramb4_s16_1(
1827 
        .CLKA(clk),
1828 
        .RSTA(rst),
1829 
        .ADDRA(tb_wadr),
1830 
        .DIA(tb_timstmp[31:16]),
1831 
        .ENA(1'b1),
1832 
        .WEA(tb_enw),
1833 
        .DOA(),
1834 
 
1835 
        .CLKB(clk),
1836 
        .RSTB(rst),
1837 
        .ADDRB(spr_addr[7:0]),
1838 
        .DIB(16'h0000),
1839 
        .ENB(1'b1),
1840 
        .WEB(1'b0),
1841 
        .DOB(tbts_dat_o[31:16])
1842 
);
1843 
 
1844 
`else
1845 
assign tbia_dat_o = 32'h0000_0000;
1846 
assign tbim_dat_o = 32'h0000_0000;
1847 
assign tbar_dat_o = 32'h0000_0000;
1848 
assign tbts_dat_o = 32'h0000_0000;
1849 
 
1850 
`endif  // OR1200_DU_TB_IMPLEMENTED
1851 
 
1852 
`else   // OR1200_DU_IMPLEMENTED
1853 
 
1854 
//
1855 
// When DU is not implemented, drive all outputs as would when DU is disabled
1856 
//
1857 
assign dbg_bp_o = 1'b0;
1858 
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1859 
 
1860 
//
1861 
// Read DU registers
1862 
//
1863 
`ifdef OR1200_DU_READREGS
1864 
assign spr_dat_o = 32'h0000_0000;
1865 
`ifdef OR1200_DU_UNUSED_ZERO
1866 
`endif
1867 
`endif
1868 
 
1869 
`endif
1870 
 
1871 
endmodule

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