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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_if.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////  Updated by:                                                 ////
////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
////  Advisor:                                                    ////
////      - Dr. Tom Conte                                         ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.2  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_if(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
 
        // Internal i/f
        if_freeze, if_insn,if_insn2, if_pc, flushpipe,
        if_stall, no_more_dslot, genpc_refetch, rfe,
        except_itlbmiss, except_immufault, except_ibuserr, thread_in,
        thread_out
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
 
// bviyer: changed the size ofhte bus from 32 to 64
input   [63:0]                   icpu_dat_i;
input                           icpu_ack_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
input   [3:0]                    icpu_tag_i;
 
//
// Internal i/f
//
input                           if_freeze;
output  [31:0]                   if_insn;
output  [31:0]                   if_insn2;               // by bviyer.
output  [31:0]                   if_pc;
input                           flushpipe;
output                          if_stall;
input                           no_more_dslot;
output                          genpc_refetch;
input                           rfe;
output                          except_itlbmiss;
output                          except_immufault;
output                          except_ibuserr;
input [2:0]                      thread_in;
output[2:0]                      thread_out;
//
// Internal wires and regs
//
reg     [31:0]                   insn_saved;
 
// added by bviyer: this wil be use to save an additional instruction
reg     [31:0]                   insn_saved2;
reg     [31:0]                   addr_saved;
reg                             saved;
 
//
// IF stage insn
//
assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i[31:0] : {`OR1200_OR32_NOP, 26'h061_0000};
 
// added by bviyer: used to supply an additional instrucion
assign if_insn2 = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved2 : icpu_ack_i ? icpu_dat_i[63:32] : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : icpu_adr_i;
// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
 
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
        if (rst)
                saved <=  1'b0;
        else if (flushpipe)
                saved <=  1'b0;
        else if (icpu_ack_i & if_freeze & !saved)
                saved <=  1'b1;
        else if (!if_freeze)
                saved <=  1'b0;
 
//
// Store fetched instruction
//
 
// added by bviyer: the additional insn_saved register to hold the saved NOp or the data
always @(posedge clk or posedge rst)
        if (rst)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (flushpipe)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (icpu_ack_i & if_freeze & !saved)
                insn_saved <=  icpu_dat_i[31:0];
        else if (!if_freeze)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
 
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
        if (rst)
                insn_saved2 <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (flushpipe)
                insn_saved2 <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (icpu_ack_i & if_freeze & !saved)
                insn_saved2 <=  icpu_dat_i[63:32];
        else if (!if_freeze)
                insn_saved2 <=  {`OR1200_OR32_NOP, 26'h041_0000};
 
 
 
 
always @(posedge clk or posedge rst)
        if (rst)
                addr_saved <=  32'h00000000;
 
        else if (flushpipe)
                addr_saved <=  32'h00000000;
        else if (icpu_ack_i & if_freeze & !saved)
                addr_saved <=  icpu_adr_i;
        else if (!if_freeze)
                addr_saved <=  icpu_adr_i;
 
assign thread_out = thread_in;
endmodule

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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_if.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	conte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's instruction fetch ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, instruction fetch, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// Updated by: ////`
17			`//// - Balaji V. Iyer, bviyer@ncsu.edu ////`
18			`//// Advisor: ////`
19			`//// - Dr. Tom Conte ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.5 2004/04/05 08:29:57 lampret`
52			`// Merged branch_qmem into main tree.`
53			`//`
54			`// Revision 1.3 2002/03/29 15:16:56 lampret`
55			`// Some of the warnings fixed.`
56			`//`
57			`// Revision 1.2 2002/01/28 01:16:00 lampret`
58			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
59			`//`
60			`// Revision 1.1 2002/01/03 08:16:15 lampret`
61			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
62			`//`
63			`// Revision 1.10 2001/11/20 18:46:15 simons`
64			`// Break point bug fixed`
65			`//`
66			`// Revision 1.9 2001/11/18 09:58:28 lampret`
67			`// Fixed some l.trap typos.`
68			`//`
69			`// Revision 1.8 2001/11/18 08:36:28 lampret`
70			`// For GDB changed single stepping and disabled trap exception.`
71			`//`
72			`// Revision 1.7 2001/10/21 17:57:16 lampret`
73			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
74			`//`
75			`// Revision 1.6 2001/10/14 13:12:09 lampret`
76			`// MP3 version.`
77			`//`
78			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
79			`// no message`
80			`//`
81			`// Revision 1.1 2001/08/09 13:39:33 lampret`
82			`// Major clean-up.`
83			`//`
84			`//`
85
86			`// synopsys translate_off`
87			`include "timescale.v"
88			`// synopsys translate_on`
89			`include "or1200_defines.v"
90
91			`module or1200_if(`
92			`// Clock and reset`
93			`clk, rst,`
94
95			`// External i/f to IC`
96			`icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,`
97
98			`// Internal i/f`
99			`if_freeze, if_insn,if_insn2, if_pc, flushpipe,`
100			`if_stall, no_more_dslot, genpc_refetch, rfe,`
101			`except_itlbmiss, except_immufault, except_ibuserr, thread_in,`
102			`thread_out`
103			`);`
104
105			`//`
106			`// I/O`
107			`//`
108
109			`//`
110			`// Clock and reset`
111			`//`
112			`input clk;`
113			`input rst;`
114
115			`//`
116			`// External i/f to IC`
117			`//`
118
119			`// bviyer: changed the size ofhte bus from 32 to 64`
120			`input [63:0] icpu_dat_i;`
121			`input icpu_ack_i;`
122			`input icpu_err_i;`
123			`input [31:0] icpu_adr_i;`
124			`input [3:0] icpu_tag_i;`
125
126			`//`
127			`// Internal i/f`
128			`//`
129			`input if_freeze;`
130			`output [31:0] if_insn;`
131			`output [31:0] if_insn2; // by bviyer.`
132			`output [31:0] if_pc;`
133			`input flushpipe;`
134			`output if_stall;`
135			`input no_more_dslot;`
136			`output genpc_refetch;`
137			`input rfe;`
138			`output except_itlbmiss;`
139			`output except_immufault;`
140			`output except_ibuserr;`
141			`input [2:0] thread_in;`
142			`output[2:0] thread_out;`
143			`//`
144			`// Internal wires and regs`
145			`//`
146			`reg [31:0] insn_saved;`
147
148			`// added by bviyer: this wil be use to save an additional instruction`
149			`reg [31:0] insn_saved2;`
150			`reg [31:0] addr_saved;`
151			`reg saved;`
152
153			`//`
154			`// IF stage insn`
155			`//`
156			assign if_insn = icpu_err_i \| no_more_dslot \| rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i[31:0] : {`OR1200_OR32_NOP, 26'h061_0000};
157
158			`// added by bviyer: used to supply an additional instrucion`
159			assign if_insn2 = icpu_err_i \| no_more_dslot \| rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved2 : icpu_ack_i ? icpu_dat_i[63:32] : {`OR1200_OR32_NOP, 26'h061_0000};
160			`assign if_pc = saved ? addr_saved : icpu_adr_i;`
161			`// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;`
162			`assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;`
163			`assign genpc_refetch = saved & icpu_ack_i;`
164			assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
165			assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
166			assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
167
168			`//`
169			`// Flag for saved insn/address`
170			`//`
171			`always @(posedge clk or posedge rst)`
172			`if (rst)`
173			`saved <= 1'b0;`
174			`else if (flushpipe)`
175			`saved <= 1'b0;`
176			`else if (icpu_ack_i & if_freeze & !saved)`
177			`saved <= 1'b1;`
178			`else if (!if_freeze)`
179			`saved <= 1'b0;`
180
181			`//`
182			`// Store fetched instruction`
183			`//`
184
185			`// added by bviyer: the additional insn_saved register to hold the saved NOp or the data`
186			`always @(posedge clk or posedge rst)`
187			`if (rst)`
188			insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
189			`else if (flushpipe)`
190			insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
191			`else if (icpu_ack_i & if_freeze & !saved)`
192			`insn_saved <= icpu_dat_i[31:0];`
193			`else if (!if_freeze)`
194			insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
195
196			`//`
197			`// Store fetched instruction's address`
198			`//`
199			`always @(posedge clk or posedge rst)`
200			`if (rst)`
201			insn_saved2 <= {`OR1200_OR32_NOP, 26'h041_0000};
202			`else if (flushpipe)`
203			insn_saved2 <= {`OR1200_OR32_NOP, 26'h041_0000};
204			`else if (icpu_ack_i & if_freeze & !saved)`
205			`insn_saved2 <= icpu_dat_i[63:32];`
206			`else if (!if_freeze)`
207			insn_saved2 <= {`OR1200_OR32_NOP, 26'h041_0000};
208
209
210
211
212			`always @(posedge clk or posedge rst)`
213			`if (rst)`
214			`addr_saved <= 32'h00000000;`
215
216			`else if (flushpipe)`
217			`addr_saved <= 32'h00000000;`
218			`else if (icpu_ack_i & if_freeze & !saved)`
219			`addr_saved <= icpu_adr_i;`
220			`else if (!if_freeze)`
221			`addr_saved <= icpu_adr_i;`
222
223			`assign thread_out = thread_in;`
224			`endmodule`