URL https://opencores.org/ocsvn/claw/claw/trunk

Subversion Repositories claw

[/] [claw/] [trunk/] [or1200_cpu/] [or1200_spram_1024x32_bw.v] - Blame information for rev 4

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2003/10/17 07:59:44  markom
// mbist signals updated according to newest convention
//
// Revision 1.1  2003/08/27 08:38:36  simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_1024x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                  mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [9:0]           addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          do;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x32_bw_bist artisan_ssp(
`else
art_hssp_1024x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_0(
`else
vs_hdsp_1024x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_0),
        .mbist_so_o(mbist_so_o_ram_0),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[7:0])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_1(
`else
vs_hdsp_1024x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_1),
        .mbist_so_o(mbist_so_o_ram_1),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[15:8])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_2(
`else
vs_hdsp_1024x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_2),
        .mbist_so_o(mbist_so_o_ram_2),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[23:16])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_3(
`else
vs_hdsp_1024x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_3),
        .mbist_so_o(mbist_so_o_ram_3),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[19:16])
);
 
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[23:20])
);
 
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[27:24])
);
 
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[31:28])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [31:0]        mem_0 [9:0];              // RAM content
reg     [31:0]        mem_1 [9:0];              // RAM content
reg     [31:0]        mem_2 [9:0];              // RAM content
reg     [31:0]        mem_3 [9:0];              // RAM content
reg     [31:0]        do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {32{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we) begin
                do_reg[7:0]   <= #1 mem_0[addr];
                do_reg[15:8]  <= #1 mem_1[addr];
                do_reg[23:16] <= #1 mem_2[addr];
                do_reg[31:24] <= #1 mem_3[addr];
        end
        else if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
        else if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
        else if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
        else if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Browse

Tools

Subversion Repositories claw

[/] [claw/] [trunk/] [or1200_cpu/] [or1200_spram_1024x32_bw.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	conte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// - Altera LPM ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`// Revision 1.2 2003/10/17 07:59:44 markom`
67			`// mbist signals updated according to newest convention`
68			`//`
69			`// Revision 1.1 2003/08/27 08:38:36 simons`
70			`// Added support for rams with byte write access.`
71			`//`
72			`//`
73
74			`// synopsys translate_off`
75			`include "timescale.v"
76			`// synopsys translate_on`
77			`include "or1200_defines.v"
78
79			`module or1200_spram_1024x32_bw(`
80			`ifdef OR1200_BIST
81			`// RAM BIST`
82			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
83			`endif
84			`// Generic synchronous single-port RAM interface`
85			`clk, rst, ce, we, oe, addr, di, do`
86			`);`
87
88			`ifdef OR1200_BIST
89			`//`
90			`// RAM BIST`
91			`//`
92			`input mbist_si_i;`
93			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
94			`output mbist_so_o;`
95			`endif
96
97			`//`
98			`// Generic synchronous single-port RAM interface`
99			`//`
100			`input clk; // Clock`
101			`input rst; // Reset`
102			`input ce; // Chip enable input`
103			`input [3:0] we; // Write enable input`
104			`input oe; // Output enable input`
105			`input [9:0] addr; // address bus inputs`
106			`input [31:0] di; // input data bus`
107			`output [31:0] do; // output data bus`
108
109			`//`
110			`// Internal wires and registers`
111			`//`
112
113			`ifdef OR1200_ARTISAN_SSP
114			`else
115			`ifdef OR1200_VIRTUALSILICON_SSP
116			`else
117			`ifdef OR1200_BIST
118			`assign mbist_so_o = mbist_si_i;`
119			`endif
120			`endif
121			`endif
122
123
124			`ifdef OR1200_ARTISAN_SSP
125
126			`//`
127			`// Instantiation of ASIC memory:`
128			`//`
129			`// Artisan Synchronous Single-Port RAM (ra1sh)`
130			`//`
131			`ifdef UNUSED
132			`art_hssp_1024x32_bw artisan_ssp(`
133			`else
134			`ifdef OR1200_BIST
135			`art_hssp_1024x32_bw_bist artisan_ssp(`
136			`else
137			`art_hssp_1024x32_bw artisan_ssp(`
138			`endif
139			`endif
140			`ifdef OR1200_BIST
141			`// RAM BIST`
142			`.mbist_si_i(mbist_si_i),`
143			`.mbist_so_o(mbist_so_o),`
144			`.mbist_ctrl_i(mbist_ctrl_i),`
145			`endif
146			`.CLK(clk),`
147			`.CEN(~ce),`
148			`.WEN(~we),`
149			`.A(addr),`
150			`.D(di),`
151			`.OEN(~oe),`
152			`.Q(do)`
153			`);`
154
155			`else
156
157			`ifdef OR1200_AVANT_ATP
158
159			`//`
160			`// Instantiation of ASIC memory:`
161			`//`
162			`// Avant! Asynchronous Two-Port RAM`
163			`//`
164			`avant_atp avant_atp(`
165			`.web(~we),`
166			`.reb(),`
167			`.oeb(~oe),`
168			`.rcsb(),`
169			`.wcsb(),`
170			`.ra(addr),`
171			`.wa(addr),`
172			`.di(di),`
173			`.do(do)`
174			`);`
175
176			`else
177
178			`ifdef OR1200_VIRAGE_SSP
179
180			`//`
181			`// Instantiation of ASIC memory:`
182			`//`
183			`// Virage Synchronous 1-port R/W RAM`
184			`//`
185			`virage_ssp virage_ssp(`
186			`.clk(clk),`
187			`.adr(addr),`
188			`.d(di),`
189			`.we(we),`
190			`.oe(oe),`
191			`.me(ce),`
192			`.q(do)`
193			`);`
194
195			`else
196
197			`ifdef OR1200_VIRTUALSILICON_SSP
198
199			`//`
200			`// Instantiation of ASIC memory:`
201			`//`
202			`// Virtual Silicon Single-Port Synchronous SRAM`
203			`//`
204			`ifdef OR1200_BIST
205			`wire mbist_si_i_ram_0;`
206			`wire mbist_si_i_ram_1;`
207			`wire mbist_si_i_ram_2;`
208			`wire mbist_si_i_ram_3;`
209			`wire mbist_so_o_ram_0;`
210			`wire mbist_so_o_ram_1;`
211			`wire mbist_so_o_ram_2;`
212			`wire mbist_so_o_ram_3;`
213			`assign mbist_si_i_ram_0 = mbist_si_i;`
214			`assign mbist_si_i_ram_1 = mbist_so_o_ram_0;`
215			`assign mbist_si_i_ram_2 = mbist_so_o_ram_1;`
216			`assign mbist_si_i_ram_3 = mbist_so_o_ram_2;`
217			`assign mbist_so_o = mbist_so_o_ram_3;`
218			`endif
219
220			`ifdef UNUSED
221			`vs_hdsp_1024x8 vs_ssp_0(`
222			`else
223			`ifdef OR1200_BIST
224			`vs_hdsp_1024x8_bist vs_ssp_0(`
225			`else
226			`vs_hdsp_1024x8 vs_ssp_0(`
227			`endif
228			`endif
229			`ifdef OR1200_BIST
230			`// RAM BIST`
231			`.mbist_si_i(mbist_si_i_ram_0),`
232			`.mbist_so_o(mbist_so_o_ram_0),`
233			`.mbist_ctrl_i(mbist_ctrl_i),`
234			`endif
235			`.CK(clk),`
236			`.ADR(addr),`
237			`.DI(di[7:0]),`
238			`.WEN(~we[0]),`
239			`.CEN(~ce),`
240			`.OEN(~oe),`
241			`.DOUT(do[7:0])`
242			`);`
243
244			`ifdef UNUSED
245			`vs_hdsp_1024x8 vs_ssp_1(`
246			`else
247			`ifdef OR1200_BIST
248			`vs_hdsp_1024x8_bist vs_ssp_1(`
249			`else
250			`vs_hdsp_1024x8 vs_ssp_1(`
251			`endif
252			`endif
253			`ifdef OR1200_BIST
254			`// RAM BIST`
255			`.mbist_si_i(mbist_si_i_ram_1),`
256			`.mbist_so_o(mbist_so_o_ram_1),`
257			`.mbist_ctrl_i(mbist_ctrl_i),`
258			`endif
259			`.CK(clk),`
260			`.ADR(addr),`
261			`.DI(di[15:8]),`
262			`.WEN(~we[1]),`
263			`.CEN(~ce),`
264			`.OEN(~oe),`
265			`.DOUT(do[15:8])`
266			`);`
267
268			`ifdef UNUSED
269			`vs_hdsp_1024x8 vs_ssp_2(`
270			`else
271			`ifdef OR1200_BIST
272			`vs_hdsp_1024x8_bist vs_ssp_2(`
273			`else
274			`vs_hdsp_1024x8 vs_ssp_2(`
275			`endif
276			`endif
277			`ifdef OR1200_BIST
278			`// RAM BIST`
279			`.mbist_si_i(mbist_si_i_ram_2),`
280			`.mbist_so_o(mbist_so_o_ram_2),`
281			`.mbist_ctrl_i(mbist_ctrl_i),`
282			`endif
283			`.CK(clk),`
284			`.ADR(addr),`
285			`.DI(di[23:16]),`
286			`.WEN(~we[2]),`
287			`.CEN(~ce),`
288			`.OEN(~oe),`
289			`.DOUT(do[23:16])`
290			`);`
291
292			`ifdef UNUSED
293			`vs_hdsp_1024x8 vs_ssp_3(`
294			`else
295			`ifdef OR1200_BIST
296			`vs_hdsp_1024x8_bist vs_ssp_3(`
297			`else
298			`vs_hdsp_1024x8 vs_ssp_3(`
299			`endif
300			`endif
301			`ifdef OR1200_BIST
302			`// RAM BIST`
303			`.mbist_si_i(mbist_si_i_ram_3),`
304			`.mbist_so_o(mbist_so_o_ram_3),`
305			`.mbist_ctrl_i(mbist_ctrl_i),`
306			`endif
307			`.CK(clk),`
308			`.ADR(addr),`
309			`.DI(di[31:24]),`
310			`.WEN(~we[3]),`
311			`.CEN(~ce),`
312			`.OEN(~oe),`
313			`.DOUT(do[31:24])`
314			`);`
315
316			`else
317
318			`ifdef OR1200_XILINX_RAMB4
319
320			`//`
321			`// Instantiation of FPGA memory:`
322			`//`
323			`// Virtex/Spartan2`
324			`//`
325
326			`//`
327			`// Block 0`
328			`//`
329			`RAMB4_S4 ramb4_s4_0(`
330			`.CLK(clk),`
331			`.RST(rst),`
332			`.ADDR(addr),`
333			`.DI(di[3:0]),`
334			`.EN(ce),`
335			`.WE(we[0]),`
336			`.DO(do[3:0])`
337			`);`
338
339			`//`
340			`// Block 1`
341			`//`
342			`RAMB4_S4 ramb4_s4_1(`
343			`.CLK(clk),`
344			`.RST(rst),`
345			`.ADDR(addr),`
346			`.DI(di[7:4]),`
347			`.EN(ce),`
348			`.WE(we[0]),`
349			`.DO(do[7:4])`
350			`);`
351
352			`//`
353			`// Block 2`
354			`//`
355			`RAMB4_S4 ramb4_s4_2(`
356			`.CLK(clk),`
357			`.RST(rst),`
358			`.ADDR(addr),`
359			`.DI(di[11:8]),`
360			`.EN(ce),`
361			`.WE(we[1]),`
362			`.DO(do[11:8])`
363			`);`
364
365			`//`
366			`// Block 3`
367			`//`
368			`RAMB4_S4 ramb4_s4_3(`
369			`.CLK(clk),`
370			`.RST(rst),`
371			`.ADDR(addr),`
372			`.DI(di[15:12]),`
373			`.EN(ce),`
374			`.WE(we[1]),`
375			`.DO(do[15:12])`
376			`);`
377
378			`//`
379			`// Block 4`
380			`//`
381			`RAMB4_S4 ramb4_s4_4(`
382			`.CLK(clk),`
383			`.RST(rst),`
384			`.ADDR(addr),`
385			`.DI(di[19:16]),`
386			`.EN(ce),`
387			`.WE(we[2]),`
388			`.DO(do[19:16])`
389			`);`
390
391			`//`
392			`// Block 5`
393			`//`
394			`RAMB4_S4 ramb4_s4_5(`
395			`.CLK(clk),`
396			`.RST(rst),`
397			`.ADDR(addr),`
398			`.DI(di[23:20]),`
399			`.EN(ce),`
400			`.WE(we[2]),`
401			`.DO(do[23:20])`
402			`);`
403
404			`//`
405			`// Block 6`
406			`//`
407			`RAMB4_S4 ramb4_s4_6(`
408			`.CLK(clk),`
409			`.RST(rst),`
410			`.ADDR(addr),`
411			`.DI(di[27:24]),`
412			`.EN(ce),`
413			`.WE(we[3]),`
414			`.DO(do[27:24])`
415			`);`
416
417			`//`
418			`// Block 7`
419			`//`
420			`RAMB4_S4 ramb4_s4_7(`
421			`.CLK(clk),`
422			`.RST(rst),`
423			`.ADDR(addr),`
424			`.DI(di[31:28]),`
425			`.EN(ce),`
426			`.WE(we[3]),`
427			`.DO(do[31:28])`
428			`);`
429
430			`else
431
432			`//`
433			`// Generic single-port synchronous RAM model`
434			`//`
435
436			`//`
437			`// Generic RAM's registers and wires`
438			`//`
439			`reg [31:0] mem_0 [9:0]; // RAM content`
440			`reg [31:0] mem_1 [9:0]; // RAM content`
441			`reg [31:0] mem_2 [9:0]; // RAM content`
442			`reg [31:0] mem_3 [9:0]; // RAM content`
443			`reg [31:0] do_reg; // RAM data output register`
444
445			`//`
446			`// Data output drivers`
447			`//`
448			`assign do = (oe) ? do_reg : {32{1'b0}};`
449
450			`//`
451			`// RAM read and write`
452			`//`
453			`always @(posedge clk)`
454			`if (ce && !we) begin`
455			`do_reg[7:0] <= #1 mem_0[addr];`
456			`do_reg[15:8] <= #1 mem_1[addr];`
457			`do_reg[23:16] <= #1 mem_2[addr];`
458			`do_reg[31:24] <= #1 mem_3[addr];`
459			`end`
460			`else if (ce && we[0])`
461			`mem_0[addr] <= #1 di[7:0];`
462			`else if (ce && we[1])`
463			`mem_1[addr] <= #1 di[15:8];`
464			`else if (ce && we[2])`
465			`mem_2[addr] <= #1 di[23:16];`
466			`else if (ce && we[3])`
467			`mem_3[addr] <= #1 di[31:24];`
468
469			`endif // !OR1200_XILINX_RAMB4_S16
470			`endif // !OR1200_VIRTUALSILICON_SSP
471			`endif // !OR1200_VIRAGE_SSP
472			`endif // !OR1200_AVANT_ATP
473			`endif // !OR1200_ARTISAN_SSP
474
475			`endmodule`