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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_spram_2048x32_bw.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/10/17 07:59:44  markom
// mbist signals updated according to newest convention
//
// Revision 1.2  2003/09/12 09:03:54  dries
// correct all the syntax errors
//
// Revision 1.1  2003/08/26 09:37:02  simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_2048x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                  mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [10:0]          addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          do;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bw_bist artisan_ssp(
`else
art_hssp_2048x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_0(
`else
vs_hdsp_2048x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_0),
        .mbist_so_o(mbist_so_o_ram_0),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[7:0])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_1(
`else
vs_hdsp_2048x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_1),
        .mbist_so_o(mbist_so_o_ram_1),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[15:8])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_2(
`else
vs_hdsp_2048x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_2),
        .mbist_so_o(mbist_so_o_ram_2),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[23:16])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_3(
`else
vs_hdsp_2048x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_3),
        .mbist_so_o(mbist_so_o_ram_3),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[9:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[9:8])
);
 
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:10]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[11:10])
);
 
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[13:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[13:12])
);
 
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:14]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[17:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[17:16])
);
 
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:18]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[19:18])
);
 
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[21:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[21:20])
);
 
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:22]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[25:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[25:24])
);
 
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:26]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[27:26])
);
 
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[29:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[29:28])
);
 
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:30]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[31:30])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [31:0]        mem_0 [10:0];              // RAM content
reg     [31:0]        mem_1 [10:0];              // RAM content
reg     [31:0]        mem_2 [10:0];              // RAM content
reg     [31:0]        mem_3 [10:0];              // RAM content
reg     [31:0]        do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {32{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we) begin
                do_reg[7:0]   <= #1 mem_0[addr];
                do_reg[15:8]  <= #1 mem_1[addr];
                do_reg[23:16] <= #1 mem_2[addr];
                do_reg[31:24] <= #1 mem_3[addr];
        end
        else if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
        else if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
        else if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
        else if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_spram_2048x32_bw.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	conte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// - Altera LPM ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`// Revision 1.3 2003/10/17 07:59:44 markom`
67			`// mbist signals updated according to newest convention`
68			`//`
69			`// Revision 1.2 2003/09/12 09:03:54 dries`
70			`// correct all the syntax errors`
71			`//`
72			`// Revision 1.1 2003/08/26 09:37:02 simons`
73			`// Added support for rams with byte write access.`
74			`//`
75			`//`
76
77			`// synopsys translate_off`
78			`include "timescale.v"
79			`// synopsys translate_on`
80			`include "or1200_defines.v"
81
82			`module or1200_spram_2048x32_bw(`
83			`ifdef OR1200_BIST
84			`// RAM BIST`
85			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
86			`endif
87			`// Generic synchronous single-port RAM interface`
88			`clk, rst, ce, we, oe, addr, di, do`
89			`);`
90
91			`ifdef OR1200_BIST
92			`//`
93			`// RAM BIST`
94			`//`
95			`input mbist_si_i;`
96			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
97			`output mbist_so_o;`
98			`endif
99
100			`//`
101			`// Generic synchronous single-port RAM interface`
102			`//`
103			`input clk; // Clock`
104			`input rst; // Reset`
105			`input ce; // Chip enable input`
106			`input [3:0] we; // Write enable input`
107			`input oe; // Output enable input`
108			`input [10:0] addr; // address bus inputs`
109			`input [31:0] di; // input data bus`
110			`output [31:0] do; // output data bus`
111
112			`//`
113			`// Internal wires and registers`
114			`//`
115
116			`ifdef OR1200_ARTISAN_SSP
117			`else
118			`ifdef OR1200_VIRTUALSILICON_SSP
119			`else
120			`ifdef OR1200_BIST
121			`assign mbist_so_o = mbist_si_i;`
122			`endif
123			`endif
124			`endif
125
126
127			`ifdef OR1200_ARTISAN_SSP
128
129			`//`
130			`// Instantiation of ASIC memory:`
131			`//`
132			`// Artisan Synchronous Single-Port RAM (ra1sh)`
133			`//`
134			`ifdef UNUSED
135			`art_hssp_2048x32_bw artisan_ssp(`
136			`else
137			`ifdef OR1200_BIST
138			`art_hssp_2048x32_bw_bist artisan_ssp(`
139			`else
140			`art_hssp_2048x32_bw artisan_ssp(`
141			`endif
142			`endif
143			`ifdef OR1200_BIST
144			`// RAM BIST`
145			`.mbist_si_i(mbist_si_i),`
146			`.mbist_so_o(mbist_so_o),`
147			`.mbist_ctrl_i(mbist_ctrl_i),`
148			`endif
149			`.CLK(clk),`
150			`.CEN(~ce),`
151			`.WEN(~we),`
152			`.A(addr),`
153			`.D(di),`
154			`.OEN(~oe),`
155			`.Q(do)`
156			`);`
157
158			`else
159
160			`ifdef OR1200_AVANT_ATP
161
162			`//`
163			`// Instantiation of ASIC memory:`
164			`//`
165			`// Avant! Asynchronous Two-Port RAM`
166			`//`
167			`avant_atp avant_atp(`
168			`.web(~we),`
169			`.reb(),`
170			`.oeb(~oe),`
171			`.rcsb(),`
172			`.wcsb(),`
173			`.ra(addr),`
174			`.wa(addr),`
175			`.di(di),`
176			`.do(do)`
177			`);`
178
179			`else
180
181			`ifdef OR1200_VIRAGE_SSP
182
183			`//`
184			`// Instantiation of ASIC memory:`
185			`//`
186			`// Virage Synchronous 1-port R/W RAM`
187			`//`
188			`virage_ssp virage_ssp(`
189			`.clk(clk),`
190			`.adr(addr),`
191			`.d(di),`
192			`.we(we),`
193			`.oe(oe),`
194			`.me(ce),`
195			`.q(do)`
196			`);`
197
198			`else
199
200			`ifdef OR1200_VIRTUALSILICON_SSP
201
202			`//`
203			`// Instantiation of ASIC memory:`
204			`//`
205			`// Virtual Silicon Single-Port Synchronous SRAM`
206			`//`
207			`ifdef OR1200_BIST
208			`wire mbist_si_i_ram_0;`
209			`wire mbist_si_i_ram_1;`
210			`wire mbist_si_i_ram_2;`
211			`wire mbist_si_i_ram_3;`
212			`wire mbist_so_o_ram_0;`
213			`wire mbist_so_o_ram_1;`
214			`wire mbist_so_o_ram_2;`
215			`wire mbist_so_o_ram_3;`
216			`assign mbist_si_i_ram_0 = mbist_si_i;`
217			`assign mbist_si_i_ram_1 = mbist_so_o_ram_0;`
218			`assign mbist_si_i_ram_2 = mbist_so_o_ram_1;`
219			`assign mbist_si_i_ram_3 = mbist_so_o_ram_2;`
220			`assign mbist_so_o = mbist_so_o_ram_3;`
221			`endif
222
223			`ifdef UNUSED
224			`vs_hdsp_2048x8 vs_ssp_0(`
225			`else
226			`ifdef OR1200_BIST
227			`vs_hdsp_2048x8_bist vs_ssp_0(`
228			`else
229			`vs_hdsp_2048x8 vs_ssp_0(`
230			`endif
231			`endif
232			`ifdef OR1200_BIST
233			`// RAM BIST`
234			`.mbist_si_i(mbist_si_i_ram_0),`
235			`.mbist_so_o(mbist_so_o_ram_0),`
236			`.mbist_ctrl_i(mbist_ctrl_i),`
237			`endif
238			`.CK(clk),`
239			`.ADR(addr),`
240			`.DI(di[7:0]),`
241			`.WEN(~we[0]),`
242			`.CEN(~ce),`
243			`.OEN(~oe),`
244			`.DOUT(do[7:0])`
245			`);`
246
247			`ifdef UNUSED
248			`vs_hdsp_2048x8 vs_ssp_1(`
249			`else
250			`ifdef OR1200_BIST
251			`vs_hdsp_2048x8_bist vs_ssp_1(`
252			`else
253			`vs_hdsp_2048x8 vs_ssp_1(`
254			`endif
255			`endif
256			`ifdef OR1200_BIST
257			`// RAM BIST`
258			`.mbist_si_i(mbist_si_i_ram_1),`
259			`.mbist_so_o(mbist_so_o_ram_1),`
260			`.mbist_ctrl_i(mbist_ctrl_i),`
261			`endif
262			`.CK(clk),`
263			`.ADR(addr),`
264			`.DI(di[15:8]),`
265			`.WEN(~we[1]),`
266			`.CEN(~ce),`
267			`.OEN(~oe),`
268			`.DOUT(do[15:8])`
269			`);`
270
271			`ifdef UNUSED
272			`vs_hdsp_2048x8 vs_ssp_2(`
273			`else
274			`ifdef OR1200_BIST
275			`vs_hdsp_2048x8_bist vs_ssp_2(`
276			`else
277			`vs_hdsp_2048x8 vs_ssp_2(`
278			`endif
279			`endif
280			`ifdef OR1200_BIST
281			`// RAM BIST`
282			`.mbist_si_i(mbist_si_i_ram_2),`
283			`.mbist_so_o(mbist_so_o_ram_2),`
284			`.mbist_ctrl_i(mbist_ctrl_i),`
285			`endif
286			`.CK(clk),`
287			`.ADR(addr),`
288			`.DI(di[23:16]),`
289			`.WEN(~we[2]),`
290			`.CEN(~ce),`
291			`.OEN(~oe),`
292			`.DOUT(do[23:16])`
293			`);`
294
295			`ifdef UNUSED
296			`vs_hdsp_2048x8 vs_ssp_3(`
297			`else
298			`ifdef OR1200_BIST
299			`vs_hdsp_2048x8_bist vs_ssp_3(`
300			`else
301			`vs_hdsp_2048x8 vs_ssp_3(`
302			`endif
303			`endif
304			`ifdef OR1200_BIST
305			`// RAM BIST`
306			`.mbist_si_i(mbist_si_i_ram_3),`
307			`.mbist_so_o(mbist_so_o_ram_3),`
308			`.mbist_ctrl_i(mbist_ctrl_i),`
309			`endif
310			`.CK(clk),`
311			`.ADR(addr),`
312			`.DI(di[31:24]),`
313			`.WEN(~we[3]),`
314			`.CEN(~ce),`
315			`.OEN(~oe),`
316			`.DOUT(do[31:24])`
317			`);`
318
319			`else
320
321			`ifdef OR1200_XILINX_RAMB4
322
323			`//`
324			`// Instantiation of FPGA memory:`
325			`//`
326			`// Virtex/Spartan2`
327			`//`
328
329			`//`
330			`// Block 0`
331			`//`
332			`RAMB4_S2 ramb4_s2_0(`
333			`.CLK(clk),`
334			`.RST(rst),`
335			`.ADDR(addr),`
336			`.DI(di[1:0]),`
337			`.EN(ce),`
338			`.WE(we[0]),`
339			`.DO(do[1:0])`
340			`);`
341
342			`//`
343			`// Block 1`
344			`//`
345			`RAMB4_S2 ramb4_s2_1(`
346			`.CLK(clk),`
347			`.RST(rst),`
348			`.ADDR(addr),`
349			`.DI(di[3:2]),`
350			`.EN(ce),`
351			`.WE(we[0]),`
352			`.DO(do[3:2])`
353			`);`
354
355			`//`
356			`// Block 2`
357			`//`
358			`RAMB4_S2 ramb4_s2_2(`
359			`.CLK(clk),`
360			`.RST(rst),`
361			`.ADDR(addr),`
362			`.DI(di[5:4]),`
363			`.EN(ce),`
364			`.WE(we[0]),`
365			`.DO(do[5:4])`
366			`);`
367
368			`//`
369			`// Block 3`
370			`//`
371			`RAMB4_S2 ramb4_s2_3(`
372			`.CLK(clk),`
373			`.RST(rst),`
374			`.ADDR(addr),`
375			`.DI(di[7:6]),`
376			`.EN(ce),`
377			`.WE(we[0]),`
378			`.DO(do[7:6])`
379			`);`
380			`//`
381			`// Block 4`
382			`//`
383			`RAMB4_S2 ramb4_s2_4(`
384			`.CLK(clk),`
385			`.RST(rst),`
386			`.ADDR(addr),`
387			`.DI(di[9:8]),`
388			`.EN(ce),`
389			`.WE(we[1]),`
390			`.DO(do[9:8])`
391			`);`
392
393			`//`
394			`// Block 5`
395			`//`
396			`RAMB4_S2 ramb4_s2_5(`
397			`.CLK(clk),`
398			`.RST(rst),`
399			`.ADDR(addr),`
400			`.DI(di[11:10]),`
401			`.EN(ce),`
402			`.WE(we[1]),`
403			`.DO(do[11:10])`
404			`);`
405
406			`//`
407			`// Block 6`
408			`//`
409			`RAMB4_S2 ramb4_s2_6(`
410			`.CLK(clk),`
411			`.RST(rst),`
412			`.ADDR(addr),`
413			`.DI(di[13:12]),`
414			`.EN(ce),`
415			`.WE(we[1]),`
416			`.DO(do[13:12])`
417			`);`
418
419			`//`
420			`// Block 7`
421			`//`
422			`RAMB4_S2 ramb4_s2_7(`
423			`.CLK(clk),`
424			`.RST(rst),`
425			`.ADDR(addr),`
426			`.DI(di[15:14]),`
427			`.EN(ce),`
428			`.WE(we[1]),`
429			`.DO(do[15:14])`
430			`);`
431			`//`
432			`// Block 8`
433			`//`
434			`RAMB4_S2 ramb4_s2_8(`
435			`.CLK(clk),`
436			`.RST(rst),`
437			`.ADDR(addr),`
438			`.DI(di[17:16]),`
439			`.EN(ce),`
440			`.WE(we[2]),`
441			`.DO(do[17:16])`
442			`);`
443
444			`//`
445			`// Block 9`
446			`//`
447			`RAMB4_S2 ramb4_s2_9(`
448			`.CLK(clk),`
449			`.RST(rst),`
450			`.ADDR(addr),`
451			`.DI(di[19:18]),`
452			`.EN(ce),`
453			`.WE(we[2]),`
454			`.DO(do[19:18])`
455			`);`
456
457			`//`
458			`// Block 10`
459			`//`
460			`RAMB4_S2 ramb4_s2_10(`
461			`.CLK(clk),`
462			`.RST(rst),`
463			`.ADDR(addr),`
464			`.DI(di[21:20]),`
465			`.EN(ce),`
466			`.WE(we[2]),`
467			`.DO(do[21:20])`
468			`);`
469
470			`//`
471			`// Block 11`
472			`//`
473			`RAMB4_S2 ramb4_s2_11(`
474			`.CLK(clk),`
475			`.RST(rst),`
476			`.ADDR(addr),`
477			`.DI(di[23:22]),`
478			`.EN(ce),`
479			`.WE(we[2]),`
480			`.DO(do[23:22])`
481			`);`
482			`//`
483			`// Block 12`
484			`//`
485			`RAMB4_S2 ramb4_s2_12(`
486			`.CLK(clk),`
487			`.RST(rst),`
488			`.ADDR(addr),`
489			`.DI(di[25:24]),`
490			`.EN(ce),`
491			`.WE(we[3]),`
492			`.DO(do[25:24])`
493			`);`
494
495			`//`
496			`// Block 13`
497			`//`
498			`RAMB4_S2 ramb4_s2_13(`
499			`.CLK(clk),`
500			`.RST(rst),`
501			`.ADDR(addr),`
502			`.DI(di[27:26]),`
503			`.EN(ce),`
504			`.WE(we[3]),`
505			`.DO(do[27:26])`
506			`);`
507
508			`//`
509			`// Block 14`
510			`//`
511			`RAMB4_S2 ramb4_s2_14(`
512			`.CLK(clk),`
513			`.RST(rst),`
514			`.ADDR(addr),`
515			`.DI(di[29:28]),`
516			`.EN(ce),`
517			`.WE(we[3]),`
518			`.DO(do[29:28])`
519			`);`
520
521			`//`
522			`// Block 15`
523			`//`
524			`RAMB4_S2 ramb4_s2_15(`
525			`.CLK(clk),`
526			`.RST(rst),`
527			`.ADDR(addr),`
528			`.DI(di[31:30]),`
529			`.EN(ce),`
530			`.WE(we[3]),`
531			`.DO(do[31:30])`
532			`);`
533
534			`else
535
536			`//`
537			`// Generic single-port synchronous RAM model`
538			`//`
539
540			`//`
541			`// Generic RAM's registers and wires`
542			`//`
543			`reg [31:0] mem_0 [10:0]; // RAM content`
544			`reg [31:0] mem_1 [10:0]; // RAM content`
545			`reg [31:0] mem_2 [10:0]; // RAM content`
546			`reg [31:0] mem_3 [10:0]; // RAM content`
547			`reg [31:0] do_reg; // RAM data output register`
548
549			`//`
550			`// Data output drivers`
551			`//`
552			`assign do = (oe) ? do_reg : {32{1'b0}};`
553
554			`//`
555			`// RAM read and write`
556			`//`
557			`always @(posedge clk)`
558			`if (ce && !we) begin`
559			`do_reg[7:0] <= #1 mem_0[addr];`
560			`do_reg[15:8] <= #1 mem_1[addr];`
561			`do_reg[23:16] <= #1 mem_2[addr];`
562			`do_reg[31:24] <= #1 mem_3[addr];`
563			`end`
564			`else if (ce && we[0])`
565			`mem_0[addr] <= #1 di[7:0];`
566			`else if (ce && we[1])`
567			`mem_1[addr] <= #1 di[15:8];`
568			`else if (ce && we[2])`
569			`mem_2[addr] <= #1 di[23:16];`
570			`else if (ce && we[3])`
571			`mem_3[addr] <= #1 di[31:24];`
572
573			`endif // !OR1200_XILINX_RAMB4_S16
574			`endif // !OR1200_VIRTUALSILICON_SSP
575			`endif // !OR1200_VIRAGE_SSP
576			`endif // !OR1200_AVANT_ATP
577			`endif // !OR1200_ARTISAN_SSP
578
579			`endmodule`