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[/] [claw/] [trunk/] [or1200_cpu/] [work/] [or1200_cfgr/] [_primary.vhd] - Blame information for rev 4

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library verilog;
use verilog.vl_types.all;
entity or1200_cfgr is
    port(
        spr_addr        : in     vl_logic_vector(31 downto 0);
        spr_dat_o       : out    vl_logic_vector(31 downto 0)
    );
end or1200_cfgr;

Line No.	Rev	Author	Line
1	2	conte	`library verilog;`
2			`use verilog.vl_types.all;`
3			`entity or1200_cfgr is`
4			`port(`
5			`spr_addr : in vl_logic_vector(31 downto 0);`
6			`spr_dat_o : out vl_logic_vector(31 downto 0)`
7			`);`
8			`end or1200_cfgr;`

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[/] [claw/] [trunk/] [or1200_cpu/] [work/] [or1200_cfgr/] [_primary.vhd] - Blame information for rev 4