OpenCores
URL https://opencores.org/ocsvn/claw/claw/trunk

Subversion Repositories claw

[/] [claw/] [trunk/] [or1200_cpu/] [work/] [or1200_qmem_top/] [_primary.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 conte
library verilog;
2
use verilog.vl_types.all;
3
entity or1200_qmem_top is
4
    generic(
5
        dw              : integer := 64
6
    );
7
    port(
8
        clk             : in     vl_logic;
9
        rst             : in     vl_logic;
10
        qmemimmu_adr_i  : in     vl_logic_vector(31 downto 0);
11
        qmemimmu_cycstb_i: in     vl_logic;
12
        qmemimmu_ci_i   : in     vl_logic;
13
        qmemicpu_sel_i  : in     vl_logic_vector(3 downto 0);
14
        qmemicpu_tag_i  : in     vl_logic_vector(3 downto 0);
15
        qmemicpu_dat_o  : out    vl_logic_vector(31 downto 0);
16
        qmemicpu_ack_o  : out    vl_logic;
17
        qmemimmu_rty_o  : out    vl_logic;
18
        qmemimmu_err_o  : out    vl_logic;
19
        qmemimmu_tag_o  : out    vl_logic_vector(3 downto 0);
20
        icqmem_adr_o    : out    vl_logic_vector(31 downto 0);
21
        icqmem_cycstb_o : out    vl_logic;
22
        icqmem_ci_o     : out    vl_logic;
23
        icqmem_sel_o    : out    vl_logic_vector(3 downto 0);
24
        icqmem_tag_o    : out    vl_logic_vector(3 downto 0);
25
        icqmem_dat_i    : in     vl_logic_vector(31 downto 0);
26
        icqmem_ack_i    : in     vl_logic;
27
        icqmem_rty_i    : in     vl_logic;
28
        icqmem_err_i    : in     vl_logic;
29
        icqmem_tag_i    : in     vl_logic_vector(3 downto 0);
30
        qmemdmmu_adr_i  : in     vl_logic_vector(31 downto 0);
31
        qmemdmmu_cycstb_i: in     vl_logic;
32
        qmemdmmu_ci_i   : in     vl_logic;
33
        qmemdcpu_we_i   : in     vl_logic;
34
        qmemdcpu_sel_i  : in     vl_logic_vector(3 downto 0);
35
        qmemdcpu_tag_i  : in     vl_logic_vector(3 downto 0);
36
        qmemdcpu_dat_i  : in     vl_logic_vector(31 downto 0);
37
        qmemdcpu_dat_o  : out    vl_logic_vector(31 downto 0);
38
        qmemdcpu_ack_o  : out    vl_logic;
39
        qmemdcpu_rty_o  : out    vl_logic;
40
        qmemdmmu_err_o  : out    vl_logic;
41
        qmemdmmu_tag_o  : out    vl_logic_vector(3 downto 0);
42
        dcqmem_adr_o    : out    vl_logic_vector(31 downto 0);
43
        dcqmem_cycstb_o : out    vl_logic;
44
        dcqmem_ci_o     : out    vl_logic;
45
        dcqmem_we_o     : out    vl_logic;
46
        dcqmem_sel_o    : out    vl_logic_vector(3 downto 0);
47
        dcqmem_tag_o    : out    vl_logic_vector(3 downto 0);
48
        dcqmem_dat_o    : out    vl_logic_vector;
49
        dcqmem_dat_i    : in     vl_logic_vector;
50
        dcqmem_ack_i    : in     vl_logic;
51
        dcqmem_rty_i    : in     vl_logic;
52
        dcqmem_err_i    : in     vl_logic;
53
        dcqmem_tag_i    : in     vl_logic_vector(3 downto 0)
54
    );
55
end or1200_qmem_top;

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.