URL https://opencores.org/ocsvn/color_converter/color_converter/trunk

Subversion Repositories color_converter

[/] [color_converter/] [trunk/] [rtl/] [vhdl/] [colorconv_wb.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log


-- ***** BEGIN LICENSE BLOCK *****
----------------------------------------------------------------------
----                                                              ----
----  Color Converter IP Core                                                     ----
----                                                              ----
---- This file is part of the matrix 3x3 multiplier project       ----
---- http://www.opencores.org/projects.cgi/web/color_converter/   ----
----                                                              ----
---- Description                                                  ----
---- True matrix 3x3 color converter                                                      ----
----                                                                  ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Michael Tsvetkov, michland@opencores.org                   ----
---- - Vyacheslav Gulyaev, vv_gulyaev@opencores.org               ----  
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2006 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/lgpl.txt or  write to the   ----
---- Free Software Foundation, Inc., 51 Franklin Street,          ----
---- Fifth Floor, Boston, MA  02110-1301  USA                     ----
----                                                              ----
----------------------------------------------------------------------
-- * ***** END LICENSE BLOCK ***** */
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
use work.ccfactors_pkg.all;
 
entity colorconv_wb is
generic( DATA_WIDTH      : INTEGER:=16);
port    (
        -- Data Bus (piped stream, our own bus) - x input and y output
        x_clk                           :       IN STD_LOGIC;
        x_rstn                          :       IN STD_LOGIC;
 
        x_we_i                          :       IN STD_LOGIC;
        y_rdy_o                         :       OUT STD_LOGIC;
 
        -- input vector
        x1_i                        :   IN UNSIGNED( data_width-1 downto 0 );
        x2_i                        :   IN UNSIGNED( data_width-1 downto 0 );
        x3_i                        :   IN UNSIGNED( data_width-1 downto 0 );
 
        -- output vector
        y1c_o                       :   OUT SIGNED( int_factors_part-1 downto 0 );
        y2c_o                       :   OUT SIGNED( int_factors_part-1 downto 0 );
        y3c_o                   :       OUT SIGNED( int_factors_part-1 downto 0 );
 
        y1_o                    :       OUT UNSIGNED( data_width-1 downto 0 );
        y2_o                :   OUT UNSIGNED( data_width-1 downto 0 );
        y3_o                :   OUT UNSIGNED( data_width-1 downto 0 );
 
        -- Control Bus (WishBone Bus slave) - set factors and shifts regs for mult3x3
        wb_clk_i                        :       IN STD_LOGIC;
        wb_rst_i                        :       IN STD_LOGIC;
        wb_stb_i                        :       IN STD_LOGIC;
        wb_we_i                         :       IN STD_LOGIC;
 
        -- data bus
        wb_adr_i                        : IN  STD_LOGIC_VECTOR (3 downto 0);
        wb_dat_i                        : IN  STD_LOGIC_VECTOR (f_factors_part+int_factors_part-1 downto 0);
        wb_dat_o                        : OUT STD_LOGIC_VECTOR (f_factors_part+int_factors_part-1 downto 0)
);
end colorconv_wb;
 
architecture a of colorconv_wb is
 
constant        factors_width   : integer := (f_factors_part + int_factors_part); -- one sign bit
--factors for rgb2ycbcr conversion
SIGNAL    a11           :       signed(factors_width-1 downto 0);
SIGNAL    a12           :       signed(factors_width-1 downto 0);
SIGNAL    a13           :       signed(factors_width-1 downto 0);
SIGNAL    a21           :       signed(factors_width-1 downto 0);
SIGNAL    a22           :       signed(factors_width-1 downto 0);
SIGNAL    a23           :       signed(factors_width-1 downto 0);
SIGNAL    a31           :       signed(factors_width-1 downto 0);
SIGNAL    a32           :       signed(factors_width-1 downto 0);
SIGNAL    a33           :       signed(factors_width-1 downto 0);
 
--shift vectors for rgb2ycbcr conversion
SIGNAL  b1x             :       signed(factors_width-1 downto 0);
SIGNAL  b2x             :       signed(factors_width-1 downto 0);
SIGNAL  b3x             :       signed(factors_width-1 downto 0);
SIGNAL  b1y             :       signed(factors_width-1 downto 0);
SIGNAL  b2y             :       signed(factors_width-1 downto 0);
SIGNAL  b3y             :       signed(factors_width-1 downto 0);
 
COMPONENT colorconv
 
generic( DATA_WIDTH      : INTEGER := 8);
port    (
        clk                        :    IN STD_LOGIC;
        rstn               :    IN STD_LOGIC;
 
        DATA_ENA           :    IN STD_LOGIC;
        DOUT_RDY           :    OUT STD_LOGIC;
 
        -- input vector
        x1                         :    IN UNSIGNED( data_width-1 downto 0 );
        x2                         :    IN UNSIGNED( data_width-1 downto 0 );
        x3                         :    IN UNSIGNED( data_width-1 downto 0 );
 
        -- matrix factors
        a11,a12,a13     :       IN SIGNED( factors_width-1 downto 0 );
        a21,a22,a23     :       IN SIGNED( factors_width-1 downto 0 );
        a31,a32,a33     :       IN SIGNED( factors_width-1 downto 0 );
 
        --shift vectors
        b1x,b2x,b3x :   IN SIGNED( factors_width-1 downto 0 );
        b1y,b2y,b3y :   IN SIGNED( factors_width-1 downto 0 );
 
        -- output vector
        y1c           :         OUT SIGNED( int_factors_part-1 downto 0 );
        y2c           :         OUT SIGNED( int_factors_part-1 downto 0 );
        y3c           :         OUT SIGNED( int_factors_part-1 downto 0 );
 
        y1             :        OUT UNSIGNED( data_width-1 downto 0 );
        y2             :        OUT UNSIGNED( data_width-1 downto 0 );
        y3             :        OUT UNSIGNED( data_width-1 downto 0 )
);
END COMPONENT ;
 
begin
 
        -- WB address decoder
        process(wb_clk_i, wb_rst_i)
        begin
                if wb_rst_i='1' then
                        a11             <= (others=>'0');
                        a12             <= (others=>'0');
                        a13             <= (others=>'0');
                        a21             <= (others=>'0');
                        a22             <= (others=>'0');
                        a23             <= (others=>'0');
                        a31             <= (others=>'0');
                        a32             <= (others=>'0');
                        a33             <= (others=>'0');
                        b1x             <= (others=>'0');
                        b2x             <= (others=>'0');
                        b3x             <= (others=>'0');
                        b1y             <= (others=>'0');
                        b2y             <= (others=>'0');
                        b3y             <= (others=>'0');
 
                elsif rising_edge(wb_clk_i) then
                        if wb_stb_i='1' then
                                if wb_we_i='1' then
 
                                        case wb_adr_i is
                                                when x"0" =>
                                                        a11             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"1" =>
                                                        a12             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"2" =>
                                                        a13             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"3" =>
                                                        a21             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"4" =>
                                                        a22             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"5" =>
                                                        a23             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"6" =>
                                                        a31             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"7" =>
                                                        a32             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"8" =>
                                                        a33             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"9" =>
                                                        b1x             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"A" =>
                                                        b2x             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"B" =>
                                                        b3x             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"C" =>
                                                        b1y             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"D" =>
                                                        b2y             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when x"E" =>
                                                        b3y             <= SIGNED(wb_dat_i(factors_width-1 downto 0));
                                                when others => null;
                                        end case;
 
                                else
 
                                        case wb_adr_i is
                                                when x"0" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a11);
                                                when x"1" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a12);
                                                when x"2" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a13);
                                                when x"3" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a21);
                                                when x"4" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a22);
                                                when x"5" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a23);
                                                when x"6" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a31);
                                                when x"7" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a32);
                                                when x"8" =>
                                                        wb_dat_o        <= STD_LOGIC_VECTOR(a33);
                                                when x"9" =>
                                                        wb_dat_o(factors_width-1 downto 0)       <= STD_LOGIC_VECTOR(b1x);
                                                when x"A" =>
                                                        wb_dat_o(factors_width-1 downto 0)       <= STD_LOGIC_VECTOR(b2x);
                                                when x"B" =>
                                                        wb_dat_o(factors_width-1 downto 0)       <= STD_LOGIC_VECTOR(b3x);
                                                when x"C" =>
                                                        wb_dat_o(factors_width-1 downto 0)       <= STD_LOGIC_VECTOR(b1y);
                                                when x"D" =>
                                                        wb_dat_o(factors_width-1 downto 0)       <= STD_LOGIC_VECTOR(b2y);
                                                when x"E" =>
                                                        wb_dat_o(factors_width-1 downto 0)       <= STD_LOGIC_VECTOR(b3y);
                                                when others => null;
                                        end case;
                                end if;
                        end if;
                end if;
        end process;
 
        converter:colorconv
        GENERIC MAP( DATA_WIDTH)
        PORT MAP (x_clk, x_rstn, x_we_i, y_rdy_o,
                                x1_i, x2_i, x3_i,
                                a11, a12, a13,
                                a21, a22, a23,
                                a31, a32, a33,
                                b1x, b2x, b3x,
                                b1y, b2y, b3y,
                                y1c_o, y2c_o, y3c_o,
                                y1_o, y2_o, y3_o
                                );
 
end a;

Browse

Tools

Subversion Repositories color_converter

[/] [color_converter/] [trunk/] [rtl/] [vhdl/] [colorconv_wb.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	michland	`-- *** BEGIN LICENSE BLOCK ***`
2			`----------------------------------------------------------------------`
3			`---- ----`
4			`---- Color Converter IP Core ----`
5			`---- ----`
6			`---- This file is part of the matrix 3x3 multiplier project ----`
7			`---- http://www.opencores.org/projects.cgi/web/color_converter/ ----`
8			`---- ----`
9			`---- Description ----`
10			`---- True matrix 3x3 color converter ----`
11			`---- ----`
12			`---- To Do: ----`
13			`---- - ----`
14			`---- ----`
15			`---- Author(s): ----`
16			`---- - Michael Tsvetkov, michland@opencores.org ----`
17			`---- - Vyacheslav Gulyaev, vv_gulyaev@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2006 Authors and OPENCORES.ORG ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.gnu.org/licenses/lgpl.txt or write to the ----`
43			`---- Free Software Foundation, Inc., 51 Franklin Street, ----`
44			`---- Fifth Floor, Boston, MA 02110-1301 USA ----`
45			`---- ----`
46			`----------------------------------------------------------------------`
47			`-- * *** END LICENSE BLOCK *** */`
48
49
50			`library IEEE;`
51			`use IEEE.std_logic_1164.all;`
52			`use IEEE.std_logic_arith.all;`
53
54			`use work.ccfactors_pkg.all;`
55
56			`entity colorconv_wb is`
57			`generic( DATA_WIDTH : INTEGER:=16);`
58			`port (`
59			`-- Data Bus (piped stream, our own bus) - x input and y output`
60			`x_clk : IN STD_LOGIC;`
61			`x_rstn : IN STD_LOGIC;`
62
63			`x_we_i : IN STD_LOGIC;`
64			`y_rdy_o : OUT STD_LOGIC;`
65
66			`-- input vector`
67			`x1_i : IN UNSIGNED( data_width-1 downto 0 );`
68			`x2_i : IN UNSIGNED( data_width-1 downto 0 );`
69			`x3_i : IN UNSIGNED( data_width-1 downto 0 );`
70
71			`-- output vector`
72			`y1c_o : OUT SIGNED( int_factors_part-1 downto 0 );`
73			`y2c_o : OUT SIGNED( int_factors_part-1 downto 0 );`
74			`y3c_o : OUT SIGNED( int_factors_part-1 downto 0 );`
75
76			`y1_o : OUT UNSIGNED( data_width-1 downto 0 );`
77			`y2_o : OUT UNSIGNED( data_width-1 downto 0 );`
78			`y3_o : OUT UNSIGNED( data_width-1 downto 0 );`
79
80			`-- Control Bus (WishBone Bus slave) - set factors and shifts regs for mult3x3`
81			`wb_clk_i : IN STD_LOGIC;`
82			`wb_rst_i : IN STD_LOGIC;`
83			`wb_stb_i : IN STD_LOGIC;`
84			`wb_we_i : IN STD_LOGIC;`
85
86			`-- data bus`
87			`wb_adr_i : IN STD_LOGIC_VECTOR (3 downto 0);`
88			`wb_dat_i : IN STD_LOGIC_VECTOR (f_factors_part+int_factors_part-1 downto 0);`
89			`wb_dat_o : OUT STD_LOGIC_VECTOR (f_factors_part+int_factors_part-1 downto 0)`
90			`);`
91			`end colorconv_wb;`
92
93			`architecture a of colorconv_wb is`
94
95			`constant factors_width : integer := (f_factors_part + int_factors_part); -- one sign bit`
96			`--factors for rgb2ycbcr conversion`
97			`SIGNAL a11 : signed(factors_width-1 downto 0);`
98			`SIGNAL a12 : signed(factors_width-1 downto 0);`
99			`SIGNAL a13 : signed(factors_width-1 downto 0);`
100			`SIGNAL a21 : signed(factors_width-1 downto 0);`
101			`SIGNAL a22 : signed(factors_width-1 downto 0);`
102			`SIGNAL a23 : signed(factors_width-1 downto 0);`
103			`SIGNAL a31 : signed(factors_width-1 downto 0);`
104			`SIGNAL a32 : signed(factors_width-1 downto 0);`
105			`SIGNAL a33 : signed(factors_width-1 downto 0);`
106
107			`--shift vectors for rgb2ycbcr conversion`
108			`SIGNAL b1x : signed(factors_width-1 downto 0);`
109			`SIGNAL b2x : signed(factors_width-1 downto 0);`
110			`SIGNAL b3x : signed(factors_width-1 downto 0);`
111			`SIGNAL b1y : signed(factors_width-1 downto 0);`
112			`SIGNAL b2y : signed(factors_width-1 downto 0);`
113			`SIGNAL b3y : signed(factors_width-1 downto 0);`
114
115			`COMPONENT colorconv`
116
117			`generic( DATA_WIDTH : INTEGER := 8);`
118			`port (`
119			`clk : IN STD_LOGIC;`
120			`rstn : IN STD_LOGIC;`
121
122			`DATA_ENA : IN STD_LOGIC;`
123			`DOUT_RDY : OUT STD_LOGIC;`
124
125			`-- input vector`
126			`x1 : IN UNSIGNED( data_width-1 downto 0 );`
127			`x2 : IN UNSIGNED( data_width-1 downto 0 );`
128			`x3 : IN UNSIGNED( data_width-1 downto 0 );`
129
130			`-- matrix factors`
131			`a11,a12,a13 : IN SIGNED( factors_width-1 downto 0 );`
132			`a21,a22,a23 : IN SIGNED( factors_width-1 downto 0 );`
133			`a31,a32,a33 : IN SIGNED( factors_width-1 downto 0 );`
134
135			`--shift vectors`
136			`b1x,b2x,b3x : IN SIGNED( factors_width-1 downto 0 );`
137			`b1y,b2y,b3y : IN SIGNED( factors_width-1 downto 0 );`
138
139			`-- output vector`
140			`y1c : OUT SIGNED( int_factors_part-1 downto 0 );`
141			`y2c : OUT SIGNED( int_factors_part-1 downto 0 );`
142			`y3c : OUT SIGNED( int_factors_part-1 downto 0 );`
143
144			`y1 : OUT UNSIGNED( data_width-1 downto 0 );`
145			`y2 : OUT UNSIGNED( data_width-1 downto 0 );`
146			`y3 : OUT UNSIGNED( data_width-1 downto 0 )`
147			`);`
148			`END COMPONENT ;`
149
150			`begin`
151
152			`-- WB address decoder`
153			`process(wb_clk_i, wb_rst_i)`
154			`begin`
155			`if wb_rst_i='1' then`
156			`a11 <= (others=>'0');`
157			`a12 <= (others=>'0');`
158			`a13 <= (others=>'0');`
159			`a21 <= (others=>'0');`
160			`a22 <= (others=>'0');`
161			`a23 <= (others=>'0');`
162			`a31 <= (others=>'0');`
163			`a32 <= (others=>'0');`
164			`a33 <= (others=>'0');`
165			`b1x <= (others=>'0');`
166			`b2x <= (others=>'0');`
167			`b3x <= (others=>'0');`
168			`b1y <= (others=>'0');`
169			`b2y <= (others=>'0');`
170			`b3y <= (others=>'0');`
171
172			`elsif rising_edge(wb_clk_i) then`
173			`if wb_stb_i='1' then`
174			`if wb_we_i='1' then`
175
176			`case wb_adr_i is`
177			`when x"0" =>`
178			`a11 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
179			`when x"1" =>`
180			`a12 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
181			`when x"2" =>`
182			`a13 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
183			`when x"3" =>`
184			`a21 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
185			`when x"4" =>`
186			`a22 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
187			`when x"5" =>`
188			`a23 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
189			`when x"6" =>`
190			`a31 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
191			`when x"7" =>`
192			`a32 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
193			`when x"8" =>`
194			`a33 <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
195			`when x"9" =>`
196			`b1x <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
197			`when x"A" =>`
198			`b2x <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
199			`when x"B" =>`
200			`b3x <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
201			`when x"C" =>`
202			`b1y <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
203			`when x"D" =>`
204			`b2y <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
205			`when x"E" =>`
206			`b3y <= SIGNED(wb_dat_i(factors_width-1 downto 0));`
207			`when others => null;`
208			`end case;`
209
210			`else`
211
212			`case wb_adr_i is`
213			`when x"0" =>`
214			`wb_dat_o <= STD_LOGIC_VECTOR(a11);`
215			`when x"1" =>`
216			`wb_dat_o <= STD_LOGIC_VECTOR(a12);`
217			`when x"2" =>`
218			`wb_dat_o <= STD_LOGIC_VECTOR(a13);`
219			`when x"3" =>`
220			`wb_dat_o <= STD_LOGIC_VECTOR(a21);`
221			`when x"4" =>`
222			`wb_dat_o <= STD_LOGIC_VECTOR(a22);`
223			`when x"5" =>`
224			`wb_dat_o <= STD_LOGIC_VECTOR(a23);`
225			`when x"6" =>`
226			`wb_dat_o <= STD_LOGIC_VECTOR(a31);`
227			`when x"7" =>`
228			`wb_dat_o <= STD_LOGIC_VECTOR(a32);`
229			`when x"8" =>`
230			`wb_dat_o <= STD_LOGIC_VECTOR(a33);`
231			`when x"9" =>`
232			`wb_dat_o(factors_width-1 downto 0) <= STD_LOGIC_VECTOR(b1x);`
233			`when x"A" =>`
234			`wb_dat_o(factors_width-1 downto 0) <= STD_LOGIC_VECTOR(b2x);`
235			`when x"B" =>`
236			`wb_dat_o(factors_width-1 downto 0) <= STD_LOGIC_VECTOR(b3x);`
237			`when x"C" =>`
238			`wb_dat_o(factors_width-1 downto 0) <= STD_LOGIC_VECTOR(b1y);`
239			`when x"D" =>`
240			`wb_dat_o(factors_width-1 downto 0) <= STD_LOGIC_VECTOR(b2y);`
241			`when x"E" =>`
242			`wb_dat_o(factors_width-1 downto 0) <= STD_LOGIC_VECTOR(b3y);`
243			`when others => null;`
244			`end case;`
245			`end if;`
246			`end if;`
247			`end if;`
248			`end process;`
249
250			`converter:colorconv`
251			`GENERIC MAP( DATA_WIDTH)`
252			`PORT MAP (x_clk, x_rstn, x_we_i, y_rdy_o,`
253			`x1_i, x2_i, x3_i,`
254			`a11, a12, a13,`
255			`a21, a22, a23,`
256			`a31, a32, a33,`
257			`b1x, b2x, b3x,`
258			`b1y, b2y, b3y,`
259			`y1c_o, y2c_o, y3c_o,`
260			`y1_o, y2_o, y3_o`
261			`);`
262
263			`end a;`