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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides a behavioral model of generic    ////
////  single-port synchronous RAM.                                ////
////  It also contains a synthesizeable model for FPGAs.          ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Generic FPGA (VENDOR_FPGA)                                ////
////    Tested RAMs: Altera, Xilinx                               ////
////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
////  - Xilinx (VENDOR_XILINX)                                    ////
////  - Altera (VENDOR_ALTERA)                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Richard Herveille, richard@asics.ws                   ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
`include "timescale.v"
 
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
 
module generic_spram(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
        //
        // Default address and data buses width
        //
        parameter aw = 6; //number of address-bits
        parameter dw = 8; //number of data-bits
 
        //
        // Generic synchronous single-port RAM interface
        //
        input           clk;  // Clock, rising edge
        input           rst;  // Reset, active high
        input           ce;   // Chip enable input, active high
        input           we;   // Write enable input, active high
        input           oe;   // Output enable input, active high
        input  [aw-1:0] addr; // address bus inputs
        input  [dw-1:0] di;   // input data bus
        output [dw-1:0] do;   // output data bus
 
        //
        // Module body
        //
 
`ifdef VENDOR_FPGA
        //
        // Instantiation synthesizeable FPGA memory
        //
        // This code has been tested using LeonardoSpectrum and Synplicity.
        // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
        //
        reg [dw-1 :0] mem [(1<<aw) -1:0];
        reg [aw-1:0] raddr;
 
        always@(posedge clk)
        begin
                // read operation
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
                // write operation
                if (we && ce)
                        mem[addr] <= #1 di;
        end
 
        assign #1 do = mem[raddr];
 
`else
 
`ifdef VENDOR_XILINX
 
        wire [dw-1:0] q;  // output from xilinx ram
        //
        // Instantiation of FPGA memory:
        //
        // Virtex/Spartan2 BlockRAMs
        //
        xilinx_ram_sp xilinx_ram(
                .clk(clk),
                .rst(rst),
                .addr(addr),
                .di(di),
                .en(ce),
                .we(we),
                .do(do)
        );
 
        defparam
                xilinx_ram.dwidth = dw,
                xilinx_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ALTERA
 
        //
        // Instantiation of FPGA memory:
        //
        // Altera FLEX EABs
        //
 
        altera_ram_sp altera_ram(
                .inclock(clk),
                .address(addr),
                .data(di),
                .we(we && ce),
                .q(do)
        );
 
        defparam
                altera_ram.dwidth = dw,
                altera_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ARTISAN
 
        //
        // Instantiation of ASIC memory:
        //
        // Artisan Synchronous Single-Port RAM (ra1sh)
        //
        artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(
                .CLK(clk),
                .CEN(~ce),
                .WEN(~we),
                .A(addr),
                .D(di),
                .OEN(~oe),
                .Q(do)
        );
 
`else
 
`ifdef VENDOR_AVANT
 
        //
        // Instantiation of ASIC memory:
        //
        // Avant! Asynchronous Two-Port RAM
        //
        avant_atp avant_atp(
                .web(~we),
                .reb(),
                .oeb(~oe),
                .rcsb(),
                .wcsb(),
                .ra(addr),
                .wa(addr),
                .di(di),
                .do(do)
        );
 
`else
 
`ifdef VENDOR_VIRAGE
 
        //
        // Instantiation of ASIC memory:
        //
        // Virage Synchronous 1-port R/W RAM
        //
        virage_ssp virage_ssp(
                .clk(clk),
                .adr(addr),
                .d(di),
                .we(we),
                .oe(oe),
                .me(ce),
                .q(do)
        );
 
`else
 
`ifdef VENDOR_VIRTUALSILICON
 
        //
        // Instantiation of ASIC memory:
        //
        // Virtual Silicon Single-Port Synchronous SRAM
        //
        virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(
                .CK(clk),
                .ADR(addr),
                .DI(di),
                .WEN(~we),
                .CEN(~ce),
                .OEN(~oe),
                .DOUT(do)
        );
 
`else
 
        //
        // Generic single-port synchronous RAM model
        //
 
        //
        // Generic RAM's registers and wires
        //
        reg  [dw-1:0] mem [(1<<aw)-1:0];  // RAM content
        wire [dw-1:0] q;                 // RAM output
        reg  [aw-1:0] raddr;             // RAM read address
        //
        // Data output drivers
        //
        assign do = (oe) ? q : {dw{1'bz}};
 
        //
        // RAM read and write
        //
 
        // read operation
        always@(posedge clk)
        if (ce) // && !we)
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
        assign #1 q = rst ? {dw{1'b0}} : mem[raddr];
 
        // write operation
        always@(posedge clk)
                if (ce && we)
                        mem[addr] <= #1 di;
 
 
`endif // !VIRTUALSILICON_SSP
`endif // !VIRAGE_SSP
`endif // !AVANT_ATP
`endif // !ARTISAN_SSP
`endif // !VENDOR_ALTERA
`endif // !VENDOR_XILINX
`endif // !VENDOR_FPGA
 
endmodule
 
 
//
// Black-box modules
//
 
`ifdef VENDOR_ALTERA
        module altera_ram_sp (
                address,
                inclock,
                we,
                data,
                q) /* synthesis black_box */;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input  [awidth -1:0] address;
                input                inclock;
                input                we;
                input  [dwidth -1:0] data;
                output [dwidth -1:0] q;
 
                // synopsis translate_off
                // exemplar translate_off
 
                syn_ram_irou #(
                        "UNUSED",
                        dwidth,
                        awidth,
                        1 << awidth
                )
                altera_spram_model (
                        .Inclock(inclock),
                        .Address(address),
                        .Data(data),
                        .WE(we),
                        .Q(q)
                );
 
                // exemplar translate_on
                // synopsis translate_on
 
        endmodule
`endif // VENDOR_ALTERA
 
`ifdef VENDOR_XILINX
        module xilinx_ram_sp (
                        clk,
                        rst,
                        addr,
                        di,
                        en,
                        we,
                        do) /* synthesis black_box */ ;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input                clk;
                input                rst;
                input  [awidth -1:0] addr;
                input  [dwidth -1:0] di;
                input                en;
                input                we;
                output [dwidth -1:0] do;
 
                // insert simulation model
 
 
                // synopsys translate_off
                // exemplar translate_off
 
                C_MEM_SP_BLOCK_V1_0 #(
                        awidth,
                        1,
                        "0",
                        1 << awidth,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        "",
                        16,
                        0,
                        0,
                        1,
                        1,
                        dwidth
                )
                xilinx_spram_model (
                        .CLK(clk),
                        .RST(rst),
                        .ADDR(addr),
                        .DI(di),
                        .EN(en),
                        .WE(we),
                        .DO(do)
                );
 
                // exemplar translate_on
                // synopsys translate_on
 
        endmodule
`endif // VENDOR_XILINX
 

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[/] [common/] [tags/] [initial/] [generic_memories/] [rtl/] [verilog/] [generic_spram.v] - Blame information for rev 47

Line No.	Rev	Author	Line
1	12	rherveille	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides a behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It also contains a synthesizeable model for FPGAs. ////`
15			`//// It should be used in all OPENCORES designs that want to be ////`
16			`//// portable accross different target technologies and ////`
17			`//// independent of target memory. ////`
18			`//// ////`
19			`//// Supported ASIC RAMs are: ////`
20			`//// - Artisan Single-Port Sync RAM ////`
21			`//// - Avant! Two-Port Sync RAM (*) ////`
22			`//// - Virage Single-Port Sync RAM ////`
23			`//// - Virtual Silicon Single-Port Sync RAM ////`
24			`//// ////`
25			`//// Supported FPGA RAMs are: ////`
26			`//// - Generic FPGA (VENDOR_FPGA) ////`
27			`//// Tested RAMs: Altera, Xilinx ////`
28			`//// Synthesis tools: LeonardoSpectrum, Synplicity ////`
29			`//// - Xilinx (VENDOR_XILINX) ////`
30			`//// - Altera (VENDOR_ALTERA) ////`
31			`//// ////`
32			`//// To Do: ////`
33			`//// - fix avant! two-port ram ////`
34			`//// - add additional RAMs ////`
35			`//// ////`
36			`//// Author(s): ////`
37			`//// - Richard Herveille, richard@asics.ws ////`
38			`//// - Damjan Lampret, lampret@opencores.org ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//// ////`
42			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
43			`//// ////`
44			`//// This source file may be used and distributed without ////`
45			`//// restriction provided that this copyright statement is not ////`
46			`//// removed from the file and that any derivative work contains ////`
47			`//// the original copyright notice and the associated disclaimer. ////`
48			`//// ////`
49			`//// This source file is free software; you can redistribute it ////`
50			`//// and/or modify it under the terms of the GNU Lesser General ////`
51			`//// Public License as published by the Free Software Foundation; ////`
52			`//// either version 2.1 of the License, or (at your option) any ////`
53			`//// later version. ////`
54			`//// ////`
55			`//// This source is distributed in the hope that it will be ////`
56			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
57			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
58			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
59			`//// details. ////`
60			`//// ////`
61			`//// You should have received a copy of the GNU Lesser General ////`
62			`//// Public License along with this source; if not, download it ////`
63			`//// from http://www.opencores.org/lgpl.shtml ////`
64			`//// ////`
65			`//////////////////////////////////////////////////////////////////////`
66			`//`
67			`// CVS Revision History`
68			`//`
69			`// $Log: not supported by cvs2svn $`
70			`// Revision 1.2 2001/07/30 05:38:02 lampret`
71			`// Adding empty directories required by HDL coding guidelines`
72			`//`
73			`//`
74
75			`include "timescale.v"
76
77			//`define VENDOR_XILINX
78			//`define VENDOR_ALTERA
79			`define VENDOR_FPGA
80
81			`module generic_spram(`
82			`// Generic synchronous single-port RAM interface`
83			`clk, rst, ce, we, oe, addr, di, do`
84			`);`
85
86			`//`
87			`// Default address and data buses width`
88			`//`
89			`parameter aw = 6; //number of address-bits`
90			`parameter dw = 8; //number of data-bits`
91
92			`//`
93			`// Generic synchronous single-port RAM interface`
94			`//`
95			`input clk; // Clock, rising edge`
96			`input rst; // Reset, active high`
97			`input ce; // Chip enable input, active high`
98			`input we; // Write enable input, active high`
99			`input oe; // Output enable input, active high`
100			`input [aw-1:0] addr; // address bus inputs`
101			`input [dw-1:0] di; // input data bus`
102			`output [dw-1:0] do; // output data bus`
103
104			`//`
105			`// Module body`
106			`//`
107
108			`ifdef VENDOR_FPGA
109			`//`
110			`// Instantiation synthesizeable FPGA memory`
111			`//`
112			`// This code has been tested using LeonardoSpectrum and Synplicity.`
113			`// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.`
114			`//`
115			`reg [dw-1 :0] mem [(1<<aw) -1:0];`
116			`reg [aw-1:0] raddr;`
117
118			`always@(posedge clk)`
119			`begin`
120			`// read operation`
121			`raddr <= #1 addr; // read address needs to be registered to read clock`
122
123			`// write operation`
124			`if (we && ce)`
125			`mem[addr] <= #1 di;`
126			`end`
127
128			`assign #1 do = mem[raddr];`
129
130			`else
131
132			`ifdef VENDOR_XILINX
133
134			`wire [dw-1:0] q; // output from xilinx ram`
135			`//`
136			`// Instantiation of FPGA memory:`
137			`//`
138			`// Virtex/Spartan2 BlockRAMs`
139			`//`
140			`xilinx_ram_sp xilinx_ram(`
141			`.clk(clk),`
142			`.rst(rst),`
143			`.addr(addr),`
144			`.di(di),`
145			`.en(ce),`
146			`.we(we),`
147			`.do(do)`
148			`);`
149
150			`defparam`
151			`xilinx_ram.dwidth = dw,`
152			`xilinx_ram.awidth = aw;`
153
154			`else
155
156			`ifdef VENDOR_ALTERA
157
158			`//`
159			`// Instantiation of FPGA memory:`
160			`//`
161			`// Altera FLEX EABs`
162			`//`
163
164			`altera_ram_sp altera_ram(`
165			`.inclock(clk),`
166			`.address(addr),`
167			`.data(di),`
168			`.we(we && ce),`
169			`.q(do)`
170			`);`
171
172			`defparam`
173			`altera_ram.dwidth = dw,`
174			`altera_ram.awidth = aw;`
175
176			`else
177
178			`ifdef VENDOR_ARTISAN
179
180			`//`
181			`// Instantiation of ASIC memory:`
182			`//`
183			`// Artisan Synchronous Single-Port RAM (ra1sh)`
184			`//`
185			`artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(`
186			`.CLK(clk),`
187			`.CEN(~ce),`
188			`.WEN(~we),`
189			`.A(addr),`
190			`.D(di),`
191			`.OEN(~oe),`
192			`.Q(do)`
193			`);`
194
195			`else
196
197			`ifdef VENDOR_AVANT
198
199			`//`
200			`// Instantiation of ASIC memory:`
201			`//`
202			`// Avant! Asynchronous Two-Port RAM`
203			`//`
204			`avant_atp avant_atp(`
205			`.web(~we),`
206			`.reb(),`
207			`.oeb(~oe),`
208			`.rcsb(),`
209			`.wcsb(),`
210			`.ra(addr),`
211			`.wa(addr),`
212			`.di(di),`
213			`.do(do)`
214			`);`
215
216			`else
217
218			`ifdef VENDOR_VIRAGE
219
220			`//`
221			`// Instantiation of ASIC memory:`
222			`//`
223			`// Virage Synchronous 1-port R/W RAM`
224			`//`
225			`virage_ssp virage_ssp(`
226			`.clk(clk),`
227			`.adr(addr),`
228			`.d(di),`
229			`.we(we),`
230			`.oe(oe),`
231			`.me(ce),`
232			`.q(do)`
233			`);`
234
235			`else
236
237			`ifdef VENDOR_VIRTUALSILICON
238
239			`//`
240			`// Instantiation of ASIC memory:`
241			`//`
242			`// Virtual Silicon Single-Port Synchronous SRAM`
243			`//`
244			`virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(`
245			`.CK(clk),`
246			`.ADR(addr),`
247			`.DI(di),`
248			`.WEN(~we),`
249			`.CEN(~ce),`
250			`.OEN(~oe),`
251			`.DOUT(do)`
252			`);`
253
254			`else
255
256			`//`
257			`// Generic single-port synchronous RAM model`
258			`//`
259
260			`//`
261			`// Generic RAM's registers and wires`
262			`//`
263			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
264			`wire [dw-1:0] q; // RAM output`
265			`reg [aw-1:0] raddr; // RAM read address`
266			`//`
267			`// Data output drivers`
268			`//`
269			`assign do = (oe) ? q : {dw{1'bz}};`
270
271			`//`
272			`// RAM read and write`
273			`//`
274
275			`// read operation`
276			`always@(posedge clk)`
277			`if (ce) // && !we)`
278			`raddr <= #1 addr; // read address needs to be registered to read clock`
279
280			`assign #1 q = rst ? {dw{1'b0}} : mem[raddr];`
281
282			`// write operation`
283			`always@(posedge clk)`
284			`if (ce && we)`
285			`mem[addr] <= #1 di;`
286
287
288			`endif // !VIRTUALSILICON_SSP
289			`endif // !VIRAGE_SSP
290			`endif // !AVANT_ATP
291			`endif // !ARTISAN_SSP
292			`endif // !VENDOR_ALTERA
293			`endif // !VENDOR_XILINX
294			`endif // !VENDOR_FPGA
295
296			`endmodule`
297
298
299			`//`
300			`// Black-box modules`
301			`//`
302
303			`ifdef VENDOR_ALTERA
304			`module altera_ram_sp (`
305			`address,`
306			`inclock,`
307			`we,`
308			`data,`
309			`q) /* synthesis black_box */;`
310
311			`parameter awidth = 7;`
312			`parameter dwidth = 8;`
313
314			`input [awidth -1:0] address;`
315			`input inclock;`
316			`input we;`
317			`input [dwidth -1:0] data;`
318			`output [dwidth -1:0] q;`
319
320			`// synopsis translate_off`
321			`// exemplar translate_off`
322
323			`syn_ram_irou #(`
324			`"UNUSED",`
325			`dwidth,`
326			`awidth,`
327			`1 << awidth`
328			`)`
329			`altera_spram_model (`
330			`.Inclock(inclock),`
331			`.Address(address),`
332			`.Data(data),`
333			`.WE(we),`
334			`.Q(q)`
335			`);`
336
337			`// exemplar translate_on`
338			`// synopsis translate_on`
339
340			`endmodule`
341			`endif // VENDOR_ALTERA
342
343			`ifdef VENDOR_XILINX
344			`module xilinx_ram_sp (`
345			`clk,`
346			`rst,`
347			`addr,`
348			`di,`
349			`en,`
350			`we,`
351			`do) /* synthesis black_box */ ;`
352
353			`parameter awidth = 7;`
354			`parameter dwidth = 8;`
355
356			`input clk;`
357			`input rst;`
358			`input [awidth -1:0] addr;`
359			`input [dwidth -1:0] di;`
360			`input en;`
361			`input we;`
362			`output [dwidth -1:0] do;`
363
364			`// insert simulation model`
365
366
367			`// synopsys translate_off`
368			`// exemplar translate_off`
369
370			`C_MEM_SP_BLOCK_V1_0 #(`
371			`awidth,`
372			`1,`
373			`"0",`
374			`1 << awidth,`
375			`1,`
376			`1,`
377			`1,`
378			`1,`
379			`1,`
380			`1,`
381			`1,`
382			`"",`
383			`16,`
384			`0,`
385			`0,`
386			`1,`
387			`1,`
388			`dwidth`
389			`)`
390			`xilinx_spram_model (`
391			`.CLK(clk),`
392			`.RST(rst),`
393			`.ADDR(addr),`
394			`.DI(di),`
395			`.EN(en),`
396			`.WE(we),`
397			`.DO(do)`
398			`);`
399
400			`// exemplar translate_on`
401			`// synopsys translate_on`
402
403			`endmodule`
404			`endif // VENDOR_XILINX
405