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[/] [common/] [trunk/] [LPM_pads.v] - Blame information for rev 48

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1 14 bbeaver
//------------------------------------------------------------------------
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//   This Verilog file was developed by Altera Corporation.  It may be
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// freely copied and/or distributed at no cost.  Any persons using this
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// file for any purpose do so at their own risk, and are responsible for
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// the results of such use.  Altera Corporation does not guarantee that
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// this file is complete, correct, or fit for any particular purpose.
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// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED.  This notice must
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// accompany any copy of this file.
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//
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//------------------------------------------------------------------------
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// Imported to Opencores directory.   Date Sept 10, 2001
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// Split related modules into separate files, as the manual splits them.
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// Added example instantiations to the beginning of each file.
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//
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/* EXAMPLE INSTANTIATIONS:
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lpm_inpad
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#( 1                          // lpm_width (width of input)
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 ) lpm_inpad_example (
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  .pad                        (data_in[lpm_width-1:0]),
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  .result                     (data_out[lpm_width-1:0])
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);
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lpm_outpad
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#( 1                          // lpm_width (width of input)
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 ) lpm_outpad_example (
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  .pad                        (data_out[lpm_width-1:0]),
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  .data                       (data_in[lpm_width-1:0])
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);
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lpm_bipad
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#( 1                          // lpm_width (width of input)
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 ) lpm_bipad_example (
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  .pad                        (data_bi[lpm_width-1:0]),
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  .result                     (data_out[lpm_width-1:0]),
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  .data                       (data_in[lpm_width-1:0]),
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  .enable                     (oe_data_to_pad)
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);
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*/
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//------------------------------------------------------------------------
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// LPM Synthesizable Models
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//------------------------------------------------------------------------
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// Version 1.5 (lpm 220)      Date 12/17/99
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//
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// Modified LPM_ADD_SUB and LPM_MULT to accomodate LPM_WIDTH = 1.
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//   Default values for LPM_WIDTH* are changed back to 1.
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// Added LPM_HINT to LPM_DIVIDE.
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// Rewritten LPM_FIFO_DC to output correctly.
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// Modified LPM_FIFO to output 0s before first read, output correct
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//   values after aclr and sclr, and output LPM_NUMWORDS mod
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//   exp(2, LPM_WIDTHU) when FIFO is full.
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//
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//------------------------------------------------------------------------
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// Version 1.4.1 (lpm 220)    Date 10/29/99
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//
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// Default values for LPM_WIDTH* of LPM_ADD_SUB and LPM_MULT are changed
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//   from 1 to 2.
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//
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//------------------------------------------------------------------------
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// Version 1.4 (lpm 220)      Date 10/18/99
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//
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// Default values for each optional inputs for ALL modules are added.
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// Some LPM_PVALUE implementations were missing, and now implemented.
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//
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//------------------------------------------------------------------------
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// Version 1.3 (lpm 220)      Date 06/23/99
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//
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// Corrected LPM_FIFO and LPM_FIFO_DC cout and empty/full flags.
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// Implemented LPM_COUNTER cin/cout, and LPM_MODULUS is now working.
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//
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//------------------------------------------------------------------------
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// Version 1.2 (lpm 220)      Date 06/16/99
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//
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// Added LPM_RAM_DP, LPM_RAM_DQ, LPM_IO, LPM_ROM, LPM_FIFO, LPM_FIFO_DC.
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// Parameters and ports are added/discarded according to the spec.
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//
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//------------------------------------------------------------------------
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// Version 1.1 (lpm 220)      Date 02/05/99
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//
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// Added LPM_DIVIDE module.
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//
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//------------------------------------------------------------------------
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// Version 1.0                Date 07/09/97
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//
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//------------------------------------------------------------------------
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// Excluded Functions:
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//
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//  LPM_FSM and LPM_TTABLE.
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//
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//------------------------------------------------------------------------
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// Assumptions:
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//
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// 1. LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS,
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//    LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE  default value is
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//    string UNUSED.
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//
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//------------------------------------------------------------------------
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// Verilog Language Issues:
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//
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// Two dimensional ports are not supported. Modules with two dimensional
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// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH)
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// bits wide.
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//
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//------------------------------------------------------------------------
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// Synthesis Issues:
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//
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// 1. LPM_COUNTER
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//
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// Currently synthesis tools do not allow mixing of level and edge
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// sensetive signals. To overcome that problem the "data" signal is
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// removed from the clock always block of lpm_counter, however the
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// synthesis result is accurate. For correct simulation add the "data"
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// pin to the sensetivity list as follows:
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//
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//  always @(posedge clock or posedge aclr or posedge aset or
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//           posedge aload or data)
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//------------------------------------------------------------------------
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module lpm_inpad ( result, pad );
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// NOTE: Parameters must be declared in the same order as the Properties
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//       are specified in the Cell Specification document.
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        parameter lpm_width = 1;
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        parameter lpm_type = "lpm_inpad";
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        parameter lpm_hint = "UNUSED";
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        parameter lpm_source_version = "lpm 220 version 1.6";
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        input  [lpm_width-1:0] pad;
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        output [lpm_width-1:0] result;
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        reg    [lpm_width-1:0] result;
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        always @(pad)
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        begin
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                result = pad;
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        end
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_inpad") || (lpm_type !== "lpm_inpad"))
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  begin
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    $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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    $finish;
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  end
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endmodule // lpm_inpad
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//------------------------------------------------------------------------
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module lpm_outpad ( data, pad );
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// NOTE: Parameters must be declared in the same order as the Properties
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//       are specified in the Cell Specification document.
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        parameter lpm_width = 1;
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        parameter lpm_type = "lpm_outpad";
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        parameter lpm_hint = "UNUSED";
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        parameter lpm_source_version = "lpm 220 version 1.6";
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        input [lpm_width-1:0] data;
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        output  [lpm_width-1:0] pad;
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        reg   [lpm_width-1:0] pad;
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        always @(data)
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        begin
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                pad = data;
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        end
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_outpad") || (lpm_type !== "lpm_outpad"))
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  begin
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    $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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    $finish;
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  end
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endmodule // lpm_outpad
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//------------------------------------------------------------------------
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module lpm_bipad ( result, pad, data, enable );
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// NOTE: Parameters must be declared in the same order as the Properties
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//       are specified in the Cell Specification document.
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        parameter lpm_width = 1;
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        parameter lpm_type = "lpm_bipad";
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        parameter lpm_hint = "UNUSED";
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        parameter lpm_source_version = "lpm 220 version 1.6";
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        input  [lpm_width-1:0] data;
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        input  enable;
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        inout  [lpm_width-1:0] pad;
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        output [lpm_width-1:0] result;
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        reg    [lpm_width-1:0] tmp_pad;
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        reg    [lpm_width-1:0] result;
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        always @(data or pad or enable)
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        begin
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                if (enable == 1)
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                begin
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                        tmp_pad = data;
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                        result = 'bz;
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                end
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                else if (enable == 0)
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                begin
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                        result = pad;
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                        tmp_pad = 'bz;
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                end
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        end
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        assign pad = tmp_pad;
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_bipad") || (lpm_type !== "lpm_bipad"))
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  begin
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    $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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    $finish;
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  end
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endmodule // lpm_bipad

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