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//////////////////////////////////////////////////////////////////////
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//// ////
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bbeaver |
//// ddr_2_dram #(frequency, latency, ////
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//// num_addr_bits, num_col_bits, ////
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//// num_data_bits, num_words_in_test_memory) ////
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//// ////
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//// This file is part of the general opencores effort. ////
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//// <http://www.opencores.org/cores/misc/> ////
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//// ////
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//// Module Description: ////
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//// A fake DDR DRAM with a small amount of memory. Useful in ////
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//// getting a DDR DRAM controller working. ////
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//// ////
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//// The DDR DRAM uses a tricky clocking scheme. Unfortunately, ////
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//// this will require a tricky controller. ////
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//// ////
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//// The CLK_P and CLK_N signals provide a time-base for the ////
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//// external IO pins on the DRAM, and may or may not be used ////
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//// as a timebase for internal DRAM activity. ////
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//// ////
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//// The DDR DRAM transfers data on both edges of the CLK_*. ////
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//// However, in order to make the design insensitive to layout ////
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//// and loading concerns, the data is NOT latched by the CLK_P ////
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//// activity. ////
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//// ////
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//// Instead the new signal DQS is used as a clock which runs in ////
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//// parallel with, and uses the same loading as, the Data ////
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//// wires DQ. ////
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//// ////
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//// In the case of writes from a controller to the DDR DRAM, the ////
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//// controller is responsible for placing the edges of DQS so ////
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//// that the edges arrive in the MIDDLE of the data valid ////
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//// period at the DRAMs. ////
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//// ////
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//// The DDR DRAM specs seem to call out that the controller will ////
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//// place the DQS transitions between 0.75 and 1.25 of a clock ////
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//// period after the rising edge of CLK_* which initiates a ////
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//// write. The obvious place to put the DQS signal is right ////
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//// at that edge. This means that the DATA for the write must ////
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//// be sent 1/4 clock EARLIER! ////
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//// ////
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//// In the case of reads from a DDR DRAM to a controller, the ////
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//// DRAM sends out data and data clock (DQ and DQS) with the ////
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//// same timing. The edges for these signals should be at the ////
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//// same time. The Controller has to internally delay the DQS ////
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//// signal by 1/2 of a bit time, and then use the INTERNAL ////
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//// DELAYED DQS signal to latch the DQ wires. ////
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//// ////
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//// The DDR DRAM specs seem to call out that the DRAM will drive ////
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//// DQS between -0.75 and +0.75 nSec of the edges of CLK_*. ////
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//// Of course, it will get to the controller some time later ////
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//// than that. ////
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//// ////
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//// To provide bad timing, this DRAM model will measure the ////
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//// period of the CLK_P clock (assuming that it is 50% duty ////
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//// cycle). It will then deliver data from 0.75 nSec AFTER ////
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//// the clock changes till 0.75 nSec BEFORE it changes again. ////
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//// This will prevent the controller from using the CLK_* ////
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//// signal to latch the data. ////
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//// ////
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//// Author(s): ////
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//// - Anonymous ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Anonymous and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: ddr_2_dram_for_debugging.v,v 1.8 2001-11-06 12:33:15 bbeaver Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2001/11/06 12:41:27 Blue Beaver
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// no message
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//
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// Revision 1.9 2001/11/02 11:59:30 Blue Beaver
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// no message
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//
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// Revision 1.8 2001/11/01 13:33:03 Blue Beaver
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// no message
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//
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// Revision 1.7 2001/11/01 12:44:03 Blue Beaver
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// no message
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//
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// Revision 1.6 2001/11/01 11:33:04 Blue Beaver
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// no message
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//
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// Revision 1.5 2001/11/01 09:38:43 Blue Beaver
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// no message
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//
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// Revision 1.4 2001/10/31 12:30:01 Blue Beaver
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// no message
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//
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// Revision 1.3 2001/10/30 12:44:03 Blue Beaver
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// no message
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//
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// Revision 1.2 2001/10/30 08:56:18 Blue Beaver
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// no message
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//
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// Revision 1.1 2001/10/29 13:45:02 Blue Beaver
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// no message
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//
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`timescale 1ns / 1ps
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module ddr_2_dram (
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DQ, DQS,
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DM,
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A, BA,
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RAS_L,
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CAS_L,
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WE_L,
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CS_L,
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CKE,
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CLK_P, CLK_N
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);
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// Constant Parameters
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parameter FREQUENCY = 133.0; // might be 100, 125, 166, any other frequency
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parameter LATENCY = 2.0; // might be 2.0, 2.5, 3.0, 3.5, 4.0
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parameter NUM_ADDR_BITS = 13;
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parameter NUM_COL_BITS = 11;
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parameter NUM_DATA_BITS = 4;
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parameter NUM_WORDS_IN_TEST_MEMORY = 32;
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parameter ENABLE_TIMING_CHECKS = 1;
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inout [NUM_DATA_BITS - 1 : 0] DQ;
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inout DQS;
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input DM;
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input [NUM_ADDR_BITS - 1 : 0] A;
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input [1 : 0] BA;
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input RAS_L;
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input CAS_L;
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input WE_L;
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input CS_L;
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input CKE;
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input CLK_P, CLK_N;
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// These signals can be accessed by upper scopes to detect chip-to-chip OE conflicts.
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wire DEBUG_DQ_OE, DEBUG_DQS_OE;
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// Try to measure the input clock, to correctly apply X's on
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// the data wires near when the outputs change.
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// I have to try to make X's BEFORE the next clock edge!
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168 |
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// This measurement is irrespective of the frequency parameter,
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// which is used only to set the number of cycles between events.
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time present_rising_time, high_period;
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time present_falling_time, low_period;
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reg data_delay1, data_delay2;
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initial
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176 |
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begin
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present_rising_time = 0;
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present_falling_time = 0;
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high_period = 0;
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low_period = 0;
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data_delay1 = 1'b0;
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182 |
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data_delay2 = 1'b0;
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183 |
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end
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184 |
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185 |
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always @(CLK_P)
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begin
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187 |
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if (CLK_P === 1'b1) // rising edge
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188 |
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begin
|
189 |
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present_rising_time = $time;
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190 |
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if ((present_rising_time !== 0) & (present_falling_time !== 0))
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191 |
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begin
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192 |
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high_period = present_rising_time - present_falling_time - (2 * 750);
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193 |
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end
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194 |
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end
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195 |
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if (CLK_P === 1'b0) // falling edge
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196 |
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begin
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197 |
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present_falling_time = $time;
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198 |
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if ((present_rising_time !== 0) & (present_falling_time !== 0))
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199 |
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begin
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200 |
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low_period = present_falling_time - present_rising_time - (2 * 750);
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201 |
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end
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202 |
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end
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203 |
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end
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204 |
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205 |
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// Once the period of the clock is known, start making X's whenever possible
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206 |
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always @(posedge CLK_P)
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begin
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208 |
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if (high_period !== 0)
|
209 |
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bbeaver |
begin // Make X's after rising edge, and before falling edge
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210 |
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bbeaver |
#750 data_delay1 = 1'b1;
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211 |
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#high_period data_delay2 = 1'b1;
|
212 |
|
|
end
|
213 |
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else
|
214 |
|
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begin
|
215 |
|
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data_delay1 = 1'b1;
|
216 |
|
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data_delay2 = 1'b1;
|
217 |
|
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end
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218 |
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if (CLK_N !== 1'b0)
|
219 |
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begin
|
220 |
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$display ("*** %m DDR DRAM needs to have CLK_N transition with CLK_P at time %t", $time);
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end
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end
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223 |
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224 |
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always @(negedge CLK_P)
|
225 |
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begin
|
226 |
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if (low_period !== 0)
|
227 |
26 |
bbeaver |
begin // Make X's after falling edge, and before rising edge
|
228 |
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bbeaver |
#750 data_delay1 = 1'b0;
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229 |
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#low_period data_delay2 = 1'b0;
|
230 |
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end
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231 |
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else
|
232 |
|
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begin
|
233 |
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data_delay1 = 1'b0;
|
234 |
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data_delay2 = 1'b0;
|
235 |
|
|
end
|
236 |
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if (CLK_N !== 1'b1)
|
237 |
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begin
|
238 |
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$display ("*** %m DDR DRAM needs to have CLK_N transition with CLK_P at time %t", $time);
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239 |
|
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end
|
240 |
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end
|
241 |
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|
242 |
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wire force_x = (data_delay1 == data_delay2);
|
243 |
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|
244 |
27 |
bbeaver |
// Watch for cases where both banks are driving the Data bus at once.
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245 |
|
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// Normally, the second read would terminate the first read. This
|
246 |
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// module, since it is only for debugging, only understands complete
|
247 |
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// 4-word burst transfers.
|
248 |
26 |
bbeaver |
|
249 |
27 |
bbeaver |
wire [NUM_DATA_BITS - 1 : 0] DQ_E_out_0;
|
250 |
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wire [NUM_DATA_BITS - 1 : 0] DQ_O_out_0;
|
251 |
30 |
bbeaver |
wire DQ_E_oe_0, DQS_E_out_0, DQS_E_oe_0, Timing_Error_0;
|
252 |
|
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wire DQ_O_oe_0, DQS_O_out_0, DQS_O_oe_0;
|
253 |
26 |
bbeaver |
|
254 |
27 |
bbeaver |
wire [NUM_DATA_BITS - 1 : 0] DQ_E_out_1;
|
255 |
|
|
wire [NUM_DATA_BITS - 1 : 0] DQ_O_out_1;
|
256 |
30 |
bbeaver |
wire DQ_E_oe_1, DQS_E_out_1, DQS_E_oe_1, Timing_Error_1;
|
257 |
|
|
wire DQ_O_oe_1, DQS_O_out_1, DQS_O_oe_1;
|
258 |
26 |
bbeaver |
|
259 |
27 |
bbeaver |
wire [NUM_DATA_BITS - 1 : 0] DQ_E_out_2;
|
260 |
|
|
wire [NUM_DATA_BITS - 1 : 0] DQ_O_out_2;
|
261 |
30 |
bbeaver |
wire DQ_E_oe_2, DQS_E_out_2, DQS_E_oe_2, Timing_Error_2;
|
262 |
|
|
wire DQ_O_oe_2, DQS_O_out_2, DQS_O_oe_2;
|
263 |
26 |
bbeaver |
|
264 |
27 |
bbeaver |
wire [NUM_DATA_BITS - 1 : 0] DQ_E_out_3;
|
265 |
|
|
wire [NUM_DATA_BITS - 1 : 0] DQ_O_out_3;
|
266 |
30 |
bbeaver |
wire DQ_E_oe_3, DQS_E_out_3, DQS_E_oe_3, Timing_Error_3;
|
267 |
|
|
wire DQ_O_oe_3, DQS_O_out_3, DQS_O_oe_3;
|
268 |
27 |
bbeaver |
|
269 |
30 |
bbeaver |
always @( DQ_E_oe_0 or DQ_E_oe_1 or DQ_E_oe_2 or DQ_E_oe_3
|
270 |
|
|
or DQS_E_out_0 or DQS_E_out_1 or DQS_E_out_2 or DQS_E_out_3
|
271 |
|
|
or DQS_E_oe_0 or DQS_E_oe_1 or DQS_E_oe_2 or DQS_E_oe_3
|
272 |
|
|
or DQ_O_oe_0 or DQ_O_oe_1 or DQ_O_oe_2 or DQ_O_oe_3
|
273 |
|
|
or DQS_O_out_0 or DQS_O_out_1 or DQS_O_out_2 or DQS_O_out_3
|
274 |
|
|
or DQS_O_oe_0 or DQS_O_oe_1 or DQS_O_oe_2 or DQS_O_oe_3 )
|
275 |
|
|
|
276 |
26 |
bbeaver |
begin
|
277 |
30 |
bbeaver |
if ( (DQ_E_oe_0 & DQ_E_oe_1) | (DQ_E_oe_0 & DQ_E_oe_2) | (DQ_E_oe_0 & DQ_E_oe_3)
|
278 |
|
|
| (DQ_E_oe_1 & DQ_E_oe_2) | (DQ_E_oe_1 & DQ_E_oe_3) | (DQ_E_oe_2 & DQ_E_oe_3)
|
279 |
|
|
| (DQ_O_oe_0 & DQ_O_oe_1) | (DQ_O_oe_0 & DQ_O_oe_2) | (DQ_O_oe_0 & DQ_O_oe_3)
|
280 |
|
|
| (DQ_O_oe_1 & DQ_O_oe_2) | (DQ_O_oe_1 & DQ_O_oe_3) | (DQ_O_oe_2 & DQ_O_oe_3) )
|
281 |
|
|
|
282 |
26 |
bbeaver |
begin
|
283 |
|
|
$display ("*** %m DDR DRAM has multiple banks driving DQ at the same time at %x %t",
|
284 |
30 |
bbeaver |
{DQ_E_oe_3, DQ_O_oe_3, DQ_E_oe_2, DQ_O_oe_2, DQ_E_oe_1, DQ_O_oe_1, DQ_E_oe_0, DQ_O_oe_0}, $time);
|
285 |
26 |
bbeaver |
end
|
286 |
30 |
bbeaver |
if ( ((DQS_E_oe_0 & DQS_E_oe_1) & ((DQS_E_out_0 != 1'b0) | (DQS_E_out_1 != 1'b0)))
|
287 |
|
|
| ((DQS_E_oe_0 & DQS_E_oe_2) & ((DQS_E_out_0 != 1'b0) | (DQS_E_out_2 != 1'b0)))
|
288 |
|
|
| ((DQS_E_oe_0 & DQS_E_oe_3) & ((DQS_E_out_0 != 1'b0) | (DQS_E_out_3 != 1'b0)))
|
289 |
|
|
| ((DQS_E_oe_1 & DQS_E_oe_2) & ((DQS_E_out_1 != 1'b0) | (DQS_E_out_2 != 1'b0)))
|
290 |
|
|
| ((DQS_E_oe_1 & DQS_E_oe_3) & ((DQS_E_out_1 != 1'b0) | (DQS_E_out_3 != 1'b0)))
|
291 |
|
|
| ((DQS_E_oe_2 & DQS_E_oe_3) & ((DQS_E_out_2 != 1'b0) | (DQS_E_out_3 != 1'b0))) )
|
292 |
26 |
bbeaver |
begin
|
293 |
30 |
bbeaver |
$display ("*** %m DDR DRAM Even has multiple banks driving DQS at the same time at %x %x %t",
|
294 |
|
|
{DQS_E_oe_3, DQS_E_oe_2, DQS_E_oe_1, DQS_E_oe_0},
|
295 |
|
|
{DQS_E_out_3, DQS_E_out_2, DQS_E_out_1, DQS_E_out_0}, $time);
|
296 |
26 |
bbeaver |
end
|
297 |
30 |
bbeaver |
if ( ((DQS_O_oe_0 & DQS_O_oe_1) & ((DQS_O_out_0 != 1'b0) | (DQS_O_out_1 != 1'b0)))
|
298 |
|
|
| ((DQS_O_oe_0 & DQS_O_oe_2) & ((DQS_O_out_0 != 1'b0) | (DQS_O_out_2 != 1'b0)))
|
299 |
|
|
| ((DQS_O_oe_0 & DQS_O_oe_3) & ((DQS_O_out_0 != 1'b0) | (DQS_O_out_3 != 1'b0)))
|
300 |
|
|
| ((DQS_O_oe_1 & DQS_O_oe_2) & ((DQS_O_out_1 != 1'b0) | (DQS_O_out_2 != 1'b0)))
|
301 |
|
|
| ((DQS_O_oe_1 & DQS_O_oe_3) & ((DQS_O_out_1 != 1'b0) | (DQS_O_out_3 != 1'b0)))
|
302 |
|
|
| ((DQS_O_oe_2 & DQS_O_oe_3) & ((DQS_O_out_2 != 1'b0) | (DQS_O_out_3 != 1'b0))) )
|
303 |
|
|
begin
|
304 |
|
|
$display ("*** %m DDR DRAM Odd has multiple banks driving DQS at the same time at %x %x %t",
|
305 |
|
|
{DQS_O_oe_3, DQS_O_oe_2, DQS_O_oe_1, DQS_O_oe_0},
|
306 |
|
|
{DQS_O_out_3, DQS_O_out_2, DQS_O_out_1, DQS_O_out_0}, $time);
|
307 |
|
|
end
|
308 |
26 |
bbeaver |
end
|
309 |
|
|
|
310 |
30 |
bbeaver |
assign DEBUG_DQ_OE = DQ_E_oe_0 | DQ_E_oe_1 | DQ_E_oe_2 | DQ_E_oe_3
|
311 |
|
|
| DQ_O_oe_0 | DQ_O_oe_1 | DQ_O_oe_2 | DQ_O_oe_3;
|
312 |
|
|
assign DEBUG_DQS_OE = DQS_E_oe_0 | DQS_E_oe_1 | DQS_E_oe_2 | DQS_E_oe_3
|
313 |
|
|
| DQS_O_oe_0 | DQS_O_oe_1 | DQS_O_oe_2 | DQS_O_oe_3;
|
314 |
27 |
bbeaver |
|
315 |
|
|
// The top-level code here is responsible for delaying the data as needed
|
316 |
|
|
// to meet the LATENCY requirement.
|
317 |
|
|
|
318 |
|
|
// LATENCY,
|
319 |
|
|
//parameter LATENCY = 2.0; // might be 2.0, 2.5, 3.0, 3.5, 4.0
|
320 |
|
|
|
321 |
26 |
bbeaver |
ddr_2_dram_single_bank
|
322 |
|
|
# ( FREQUENCY,
|
323 |
29 |
bbeaver |
LATENCY,
|
324 |
26 |
bbeaver |
NUM_ADDR_BITS,
|
325 |
|
|
NUM_COL_BITS,
|
326 |
|
|
NUM_DATA_BITS,
|
327 |
32 |
bbeaver |
NUM_WORDS_IN_TEST_MEMORY,
|
328 |
|
|
1 // enable_timing_checks
|
329 |
26 |
bbeaver |
) ddr_2_dram_single_bank_0 (
|
330 |
|
|
.DQ (DQ[NUM_DATA_BITS - 1 : 0]),
|
331 |
|
|
.DQS (DQS),
|
332 |
27 |
bbeaver |
.DQ_E_out (DQ_E_out_0[NUM_DATA_BITS - 1 : 0]),
|
333 |
|
|
.DQ_O_out (DQ_O_out_0[NUM_DATA_BITS - 1 : 0]),
|
334 |
30 |
bbeaver |
.DQ_E_oe (DQ_E_oe_0),
|
335 |
|
|
.DQ_O_oe (DQ_O_oe_0),
|
336 |
|
|
.DQS_E_out (DQS_E_out_0),
|
337 |
|
|
.DQS_O_out (DQS_O_out_0),
|
338 |
|
|
.DQS_E_oe (DQS_E_oe_0),
|
339 |
|
|
.DQS_O_oe (DQS_O_oe_0),
|
340 |
27 |
bbeaver |
.Timing_Error (Timing_Error_0),
|
341 |
26 |
bbeaver |
.DM (DM),
|
342 |
|
|
.A (A[12:0]),
|
343 |
|
|
.BA (BA[1:0]),
|
344 |
|
|
.RAS_L (RAS_L),
|
345 |
|
|
.CAS_L (CAS_L),
|
346 |
|
|
.WE_L (WE_L),
|
347 |
|
|
.CS_L (CS_L),
|
348 |
|
|
.CKE (CKE),
|
349 |
|
|
.CLK_P (CLK_P),
|
350 |
|
|
.CLK_N (CLK_N),
|
351 |
|
|
.bank_num (2'b00)
|
352 |
|
|
);
|
353 |
|
|
|
354 |
|
|
ddr_2_dram_single_bank
|
355 |
|
|
# ( FREQUENCY,
|
356 |
29 |
bbeaver |
LATENCY,
|
357 |
26 |
bbeaver |
NUM_ADDR_BITS,
|
358 |
|
|
NUM_COL_BITS,
|
359 |
|
|
NUM_DATA_BITS,
|
360 |
32 |
bbeaver |
NUM_WORDS_IN_TEST_MEMORY,
|
361 |
|
|
|
362 |
26 |
bbeaver |
) ddr_2_dram_single_bank_1 (
|
363 |
|
|
.DQ (DQ[NUM_DATA_BITS - 1 : 0]),
|
364 |
|
|
.DQS (DQS),
|
365 |
27 |
bbeaver |
.DQ_E_out (DQ_E_out_1[NUM_DATA_BITS - 1 : 0]),
|
366 |
|
|
.DQ_O_out (DQ_O_out_1[NUM_DATA_BITS - 1 : 0]),
|
367 |
30 |
bbeaver |
.DQ_E_oe (DQ_E_oe_1),
|
368 |
|
|
.DQ_O_oe (DQ_O_oe_1),
|
369 |
|
|
.DQS_E_out (DQS_E_out_1),
|
370 |
|
|
.DQS_O_out (DQS_O_out_1),
|
371 |
|
|
.DQS_E_oe (DQS_E_oe_1),
|
372 |
|
|
.DQS_O_oe (DQS_O_oe_1),
|
373 |
27 |
bbeaver |
.Timing_Error (Timing_Error_1),
|
374 |
26 |
bbeaver |
.DM (DM),
|
375 |
|
|
.A (A[12:0]),
|
376 |
|
|
.BA (BA[1:0]),
|
377 |
|
|
.RAS_L (RAS_L),
|
378 |
|
|
.CAS_L (CAS_L),
|
379 |
|
|
.WE_L (WE_L),
|
380 |
|
|
.CS_L (CS_L),
|
381 |
|
|
.CKE (CKE),
|
382 |
|
|
.CLK_P (CLK_P),
|
383 |
|
|
.CLK_N (CLK_N),
|
384 |
|
|
.bank_num (2'b01)
|
385 |
|
|
);
|
386 |
|
|
|
387 |
|
|
ddr_2_dram_single_bank
|
388 |
|
|
# ( FREQUENCY,
|
389 |
29 |
bbeaver |
LATENCY,
|
390 |
26 |
bbeaver |
NUM_ADDR_BITS,
|
391 |
|
|
NUM_COL_BITS,
|
392 |
|
|
NUM_DATA_BITS,
|
393 |
32 |
bbeaver |
NUM_WORDS_IN_TEST_MEMORY,
|
394 |
|
|
|
395 |
26 |
bbeaver |
) ddr_2_dram_single_bank_2 (
|
396 |
|
|
.DQ (DQ[NUM_DATA_BITS - 1 : 0]),
|
397 |
|
|
.DQS (DQS),
|
398 |
27 |
bbeaver |
.DQ_E_out (DQ_E_out_2[NUM_DATA_BITS - 1 : 0]),
|
399 |
|
|
.DQ_O_out (DQ_O_out_2[NUM_DATA_BITS - 1 : 0]),
|
400 |
30 |
bbeaver |
.DQ_E_oe (DQ_E_oe_2),
|
401 |
|
|
.DQ_O_oe (DQ_O_oe_2),
|
402 |
|
|
.DQS_E_out (DQS_E_out_2),
|
403 |
|
|
.DQS_O_out (DQS_O_out_2),
|
404 |
|
|
.DQS_E_oe (DQS_E_oe_2),
|
405 |
|
|
.DQS_O_oe (DQS_O_oe_2),
|
406 |
27 |
bbeaver |
.Timing_Error (Timing_Error_2),
|
407 |
26 |
bbeaver |
.DM (DM),
|
408 |
|
|
.A (A[12:0]),
|
409 |
|
|
.BA (BA[1:0]),
|
410 |
|
|
.RAS_L (RAS_L),
|
411 |
|
|
.CAS_L (CAS_L),
|
412 |
|
|
.WE_L (WE_L),
|
413 |
|
|
.CS_L (CS_L),
|
414 |
|
|
.CKE (CKE),
|
415 |
|
|
.CLK_P (CLK_P),
|
416 |
|
|
.CLK_N (CLK_N),
|
417 |
|
|
.bank_num (2'b10)
|
418 |
|
|
);
|
419 |
|
|
|
420 |
|
|
ddr_2_dram_single_bank
|
421 |
|
|
# ( FREQUENCY,
|
422 |
29 |
bbeaver |
LATENCY,
|
423 |
26 |
bbeaver |
NUM_ADDR_BITS,
|
424 |
|
|
NUM_COL_BITS,
|
425 |
|
|
NUM_DATA_BITS,
|
426 |
32 |
bbeaver |
NUM_WORDS_IN_TEST_MEMORY,
|
427 |
|
|
|
428 |
26 |
bbeaver |
) ddr_2_dram_single_bank_3 (
|
429 |
|
|
.DQ (DQ[NUM_DATA_BITS - 1 : 0]),
|
430 |
|
|
.DQS (DQS),
|
431 |
27 |
bbeaver |
.DQ_E_out (DQ_E_out_3[NUM_DATA_BITS - 1 : 0]),
|
432 |
|
|
.DQ_O_out (DQ_O_out_3[NUM_DATA_BITS - 1 : 0]),
|
433 |
30 |
bbeaver |
.DQ_E_oe (DQ_E_oe_3),
|
434 |
|
|
.DQ_O_oe (DQ_O_oe_3),
|
435 |
|
|
.DQS_E_out (DQS_E_out_3),
|
436 |
|
|
.DQS_O_out (DQS_O_out_3),
|
437 |
|
|
.DQS_E_oe (DQS_E_oe_3),
|
438 |
|
|
.DQS_O_oe (DQS_O_oe_3),
|
439 |
27 |
bbeaver |
.Timing_Error (Timing_Error_3),
|
440 |
26 |
bbeaver |
.DM (DM),
|
441 |
|
|
.A (A[12:0]),
|
442 |
|
|
.BA (BA[1:0]),
|
443 |
|
|
.RAS_L (RAS_L),
|
444 |
|
|
.CAS_L (CAS_L),
|
445 |
|
|
.WE_L (WE_L),
|
446 |
|
|
.CS_L (CS_L),
|
447 |
|
|
.CKE (CKE),
|
448 |
|
|
.CLK_P (CLK_P),
|
449 |
|
|
.CLK_N (CLK_N),
|
450 |
|
|
.bank_num (2'b11)
|
451 |
|
|
);
|
452 |
|
|
|
453 |
|
|
endmodule
|
454 |
|
|
|
455 |
|
|
module ddr_2_dram_single_bank (
|
456 |
|
|
DQ, DQS,
|
457 |
30 |
bbeaver |
DQ_E_out, DQ_O_out, DQ_E_oe, DQ_O_oe,
|
458 |
|
|
DQS_E_out, DQS_O_out, DQS_E_oe, DQS_O_oe,
|
459 |
27 |
bbeaver |
Timing_Error,
|
460 |
26 |
bbeaver |
DM,
|
461 |
|
|
A, BA,
|
462 |
|
|
RAS_L,
|
463 |
|
|
CAS_L,
|
464 |
|
|
WE_L,
|
465 |
|
|
CS_L,
|
466 |
|
|
CKE,
|
467 |
|
|
CLK_P, CLK_N,
|
468 |
|
|
bank_num
|
469 |
|
|
);
|
470 |
|
|
|
471 |
|
|
// Constant Parameters
|
472 |
|
|
parameter FREQUENCY = 133.0; // might be 100, 125, 166, any other frequency
|
473 |
29 |
bbeaver |
parameter LATENCY = 2.0; // might be 2.0, 2.5, 3.0, 3.5, 4.0, 4.5
|
474 |
26 |
bbeaver |
parameter NUM_ADDR_BITS = 13;
|
475 |
32 |
bbeaver |
parameter NUM_COL_BITS = 12;
|
476 |
26 |
bbeaver |
parameter NUM_DATA_BITS = 4;
|
477 |
|
|
parameter NUM_WORDS_IN_TEST_MEMORY = 32;
|
478 |
32 |
bbeaver |
parameter ENABLE_TIMING_CHECKS = 1;
|
479 |
26 |
bbeaver |
|
480 |
|
|
input [NUM_DATA_BITS - 1 : 0] DQ;
|
481 |
|
|
input DQS;
|
482 |
27 |
bbeaver |
output [NUM_DATA_BITS - 1 : 0] DQ_E_out;
|
483 |
|
|
output [NUM_DATA_BITS - 1 : 0] DQ_O_out;
|
484 |
30 |
bbeaver |
output DQ_E_oe, DQ_O_oe;
|
485 |
|
|
output DQS_E_out, DQS_O_out, DQS_E_oe, DQS_O_oe;
|
486 |
27 |
bbeaver |
output Timing_Error;
|
487 |
26 |
bbeaver |
input DM;
|
488 |
|
|
input [NUM_ADDR_BITS - 1 : 0] A;
|
489 |
|
|
input [1 : 0] BA;
|
490 |
|
|
input RAS_L;
|
491 |
|
|
input CAS_L;
|
492 |
|
|
input WE_L;
|
493 |
|
|
input CS_L;
|
494 |
|
|
input CKE;
|
495 |
|
|
input CLK_P, CLK_N;
|
496 |
|
|
input [1:0] bank_num;
|
497 |
|
|
|
498 |
31 |
bbeaver |
// DDR DRAMs always capture their command on the RISING EDGE of CLK_P;
|
499 |
|
|
// This fake DDR DRAM understands: Idle, Activate, Read, Write, Automatic Refresh
|
500 |
|
|
// This fake DDR DRAM assumes that all Reads and Writes do automatic precharge.
|
501 |
|
|
// This fake DDR DRAM understands writes to the control register
|
502 |
|
|
// This fake DDR DRAM always does 4-word bursts. The first word of data
|
503 |
|
|
// is always the legal one. The next 3 are that first word inverted.
|
504 |
|
|
// DDR DRAMs always capture their data on BOTH EDGES of DQS
|
505 |
|
|
// DDR DRAMs always output enable the DQS wire to 1'h0 1 clock before
|
506 |
|
|
// they start sending data
|
507 |
|
|
// DDR DRAMs will be allowed to have a latency of 2, 2.5, 3, 3.5, 4, 4.5
|
508 |
|
|
// from the read command.
|
509 |
|
|
|
510 |
|
|
// DDR DRAM commands are made by using the following sighals:
|
511 |
|
|
// {CKE, CS_L, RAS_L, CAS_L, WS_L}
|
512 |
|
|
// 0 X X X X power-down
|
513 |
|
|
// 1 1 X X X NOOP
|
514 |
|
|
// 1 0 1 1 1 NOOP
|
515 |
|
|
// 1 0 0 1 1 ACTIVATE
|
516 |
|
|
// 1 0 1 0 1 READ (A10)
|
517 |
|
|
// 1 0 1 0 0 WRITE (A10)
|
518 |
|
|
// 1 0 0 1 0 PRECHARGE (A10)
|
519 |
|
|
// 1 0 0 0 1 AUTO REFRESH
|
520 |
|
|
// 1 0 0 0 0 LOAD MODE REGISTER
|
521 |
|
|
// 1 0 1 1 0 not used?
|
522 |
|
|
|
523 |
|
|
parameter NOOP = 5'h17;
|
524 |
|
|
parameter LOAD_MODE = 5'h10;
|
525 |
|
|
parameter ACTIVATE_BANK = 5'h13;
|
526 |
|
|
parameter READ_BANK = 5'h15;
|
527 |
|
|
parameter WRITE_BANK = 5'h14;
|
528 |
|
|
parameter PRECHARGE_BANK = 5'h12;
|
529 |
|
|
parameter REFRESH_BANK = 5'h11;
|
530 |
|
|
|
531 |
|
|
wire [4:0] control_wires = {CKE, CS_L, RAS_L, CAS_L, WE_L};
|
532 |
|
|
|
533 |
30 |
bbeaver |
// This simple-minded DRAM assumes that all transactions are valid.
|
534 |
31 |
bbeaver |
// Therefore, it always captures RAS and CAS address information, even
|
535 |
30 |
bbeaver |
// if there is an obvious protocol violation.
|
536 |
|
|
|
537 |
|
|
reg [NUM_ADDR_BITS - 1 : 0] Captured_RAS_Address;
|
538 |
|
|
reg [1:0] Captured_RAS_Bank_Selects;
|
539 |
|
|
|
540 |
|
|
reg [NUM_ADDR_BITS - 1 : 0] Captured_CAS_Address;
|
541 |
|
|
reg [1:0] Captured_CAS_Bank_Selects;
|
542 |
|
|
|
543 |
31 |
bbeaver |
reg RAS_Address_Valid;
|
544 |
32 |
bbeaver |
reg Full_Address_Valid;
|
545 |
31 |
bbeaver |
reg DRAM_Read_Requested;
|
546 |
30 |
bbeaver |
|
547 |
32 |
bbeaver |
// synopsys translate_off
|
548 |
31 |
bbeaver |
initial
|
549 |
32 |
bbeaver |
begin // only for debug
|
550 |
31 |
bbeaver |
RAS_Address_Valid <= 1'b0;
|
551 |
32 |
bbeaver |
Full_Address_Valid <= 1'b0;
|
552 |
31 |
bbeaver |
end
|
553 |
32 |
bbeaver |
// synopsys translate_on
|
554 |
31 |
bbeaver |
|
555 |
|
|
// Capture RAS and CAS address information
|
556 |
|
|
always @(posedge CLK_P)
|
557 |
|
|
begin
|
558 |
|
|
if ((control_wires[4:0] == ACTIVATE_BANK) & (BA[1:0] == bank_num[1:0]))
|
559 |
|
|
begin
|
560 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0] <= A[NUM_ADDR_BITS - 1 : 0];
|
561 |
|
|
Captured_RAS_Bank_Selects[1:0] <= BA[1 : 0];
|
562 |
|
|
RAS_Address_Valid <= 1'b1;
|
563 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0] <=
|
564 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0];
|
565 |
|
|
Captured_CAS_Bank_Selects[1:0] <= Captured_CAS_Bank_Selects[1:0];
|
566 |
|
|
DRAM_Read_Requested <= 1'b0;
|
567 |
32 |
bbeaver |
Full_Address_Valid <= 1'b0;
|
568 |
31 |
bbeaver |
end
|
569 |
|
|
else if ((control_wires[4:0] == READ_BANK) & (BA[1:0] == bank_num[1:0]))
|
570 |
|
|
begin
|
571 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0] <=
|
572 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0];
|
573 |
|
|
Captured_RAS_Bank_Selects[1:0] <= Captured_RAS_Bank_Selects[1:0];
|
574 |
|
|
if (A[10] == 1'b1) // automatic precharge
|
575 |
|
|
RAS_Address_Valid <= 1'b0;
|
576 |
|
|
else
|
577 |
|
|
RAS_Address_Valid <= 1'b1;
|
578 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0] <= A[NUM_ADDR_BITS - 1 : 0];
|
579 |
|
|
Captured_CAS_Bank_Selects[1:0] <= BA[1 : 0];
|
580 |
|
|
DRAM_Read_Requested <= 1'b1;
|
581 |
32 |
bbeaver |
Full_Address_Valid <= 1'b1;
|
582 |
31 |
bbeaver |
if (RAS_Address_Valid == 1'b0)
|
583 |
|
|
begin
|
584 |
|
|
$display ("*** %m DRAM accessed for Read without first doing an Activate %t", $time);
|
585 |
|
|
end
|
586 |
|
|
end
|
587 |
|
|
else if ((control_wires[4:0] == WRITE_BANK) & (BA[1:0] == bank_num[1:0]))
|
588 |
|
|
begin
|
589 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0] <=
|
590 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0];
|
591 |
|
|
Captured_RAS_Bank_Selects[1:0] <= Captured_RAS_Bank_Selects[1:0];
|
592 |
|
|
if (A[10] == 1'b1) // automatic precharge
|
593 |
|
|
RAS_Address_Valid <= 1'b0;
|
594 |
|
|
else
|
595 |
|
|
RAS_Address_Valid <= 1'b1;
|
596 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0] <= A[NUM_ADDR_BITS - 1 : 0];
|
597 |
|
|
Captured_CAS_Bank_Selects[1:0] <= BA[1 : 0];
|
598 |
|
|
DRAM_Read_Requested <= 1'b0;
|
599 |
32 |
bbeaver |
Full_Address_Valid <= 1'b1;
|
600 |
31 |
bbeaver |
if (RAS_Address_Valid == 1'b0)
|
601 |
|
|
begin
|
602 |
|
|
$display ("*** %m DRAM accessed for Write without first doing an Activate %t", $time);
|
603 |
|
|
end
|
604 |
|
|
end
|
605 |
|
|
else if ( (control_wires[4:0] == PRECHARGE_BANK)
|
606 |
|
|
& ((BA[1:0] == bank_num[1:0]) | (A[10] == 1'b1)))
|
607 |
|
|
begin
|
608 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0] <=
|
609 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0];
|
610 |
|
|
Captured_RAS_Bank_Selects[1:0] <= Captured_RAS_Bank_Selects[1:0];
|
611 |
|
|
RAS_Address_Valid <= 1'b0;
|
612 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0] <=
|
613 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0];
|
614 |
|
|
Captured_CAS_Bank_Selects[1:0] <= Captured_CAS_Bank_Selects[1:0];
|
615 |
|
|
DRAM_Read_Requested <= 1'b0;
|
616 |
32 |
bbeaver |
Full_Address_Valid <= 1'b0;
|
617 |
31 |
bbeaver |
end
|
618 |
|
|
else // NOOP, Load Mode Register, Refresh, Unallocated
|
619 |
|
|
begin
|
620 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0] <=
|
621 |
|
|
Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0];
|
622 |
|
|
Captured_RAS_Bank_Selects[1:0] <= Captured_RAS_Bank_Selects[1:0];
|
623 |
|
|
RAS_Address_Valid <= RAS_Address_Valid;
|
624 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0] <=
|
625 |
|
|
Captured_CAS_Address[NUM_ADDR_BITS - 1 : 0];
|
626 |
|
|
Captured_CAS_Bank_Selects[1:0] <= Captured_CAS_Bank_Selects[1:0];
|
627 |
|
|
DRAM_Read_Requested <= 1'b0;
|
628 |
32 |
bbeaver |
Full_Address_Valid <= 1'b0;
|
629 |
31 |
bbeaver |
end
|
630 |
|
|
end
|
631 |
|
|
|
632 |
30 |
bbeaver |
// This debugging DRAM requires that entire 4-word bursts be done.
|
633 |
|
|
// At present, this design does not implement DM masking.
|
634 |
|
|
// This debugging DRAM captures data using the DQS signals. It
|
635 |
|
|
// immediately moves the data into the CLK_P positive edge clock domain.
|
636 |
|
|
|
637 |
|
|
reg [NUM_DATA_BITS - 1 : 0] DQS_Captured_Write_Data_Even;
|
638 |
|
|
reg [NUM_DATA_BITS - 1 : 0] DQS_Captured_Write_Data_Odd;
|
639 |
|
|
reg DQS_Captured_Write_DM_Even, DQS_Captured_Write_DM_Odd;
|
640 |
|
|
reg [NUM_DATA_BITS - 1 : 0] Delay_Write_Data_Even;
|
641 |
|
|
reg [NUM_DATA_BITS - 1 : 0] Sync_Write_Data_Even;
|
642 |
|
|
reg [NUM_DATA_BITS - 1 : 0] Sync_Write_Data_Odd;
|
643 |
|
|
reg Delay_Write_DM_Even, Sync_Write_DM_Even, Sync_Write_DM_Odd;
|
644 |
|
|
|
645 |
|
|
// Capture data on rising edge of DQS
|
646 |
|
|
always @(posedge DQS)
|
647 |
|
|
begin
|
648 |
|
|
DQS_Captured_Write_Data_Even[NUM_DATA_BITS - 1 : 0] <= DQ[NUM_DATA_BITS - 1 : 0];
|
649 |
|
|
DQS_Captured_Write_DM_Even <= DM;
|
650 |
|
|
end
|
651 |
|
|
|
652 |
|
|
// Delay data captured on rising edge so that it can be captured the NEXT rising edge
|
653 |
|
|
always @(negedge CLK_P)
|
654 |
|
|
begin
|
655 |
|
|
Delay_Write_Data_Even[NUM_DATA_BITS - 1 : 0] <=
|
656 |
|
|
DQS_Captured_Write_Data_Even[NUM_DATA_BITS - 1 : 0];
|
657 |
|
|
Delay_Write_DM_Even <= DQS_Captured_Write_DM_Even;
|
658 |
|
|
end
|
659 |
|
|
|
660 |
32 |
bbeaver |
// Capture data on falling edge of DQS
|
661 |
|
|
always @(negedge DQS)
|
662 |
|
|
begin
|
663 |
|
|
DQS_Captured_Write_Data_Odd[NUM_DATA_BITS - 1 : 0] <= DQ[NUM_DATA_BITS - 1 : 0];
|
664 |
|
|
DQS_Captured_Write_DM_Odd <= DM;
|
665 |
|
|
end
|
666 |
|
|
|
667 |
30 |
bbeaver |
// Capture a data item pair into the positive edge clock domain.
|
668 |
|
|
always @(posedge CLK_P)
|
669 |
|
|
begin
|
670 |
|
|
Sync_Write_Data_Even[NUM_DATA_BITS - 1 : 0] <=
|
671 |
|
|
Delay_Write_Data_Even[NUM_DATA_BITS - 1 : 0];
|
672 |
|
|
Sync_Write_Data_Odd[NUM_DATA_BITS - 1 : 0] <=
|
673 |
31 |
bbeaver |
DQS_Captured_Write_Data_Odd[NUM_DATA_BITS - 1 : 0];
|
674 |
30 |
bbeaver |
Sync_Write_DM_Even <= Delay_Write_DM_Even;
|
675 |
|
|
Sync_Write_DM_Odd <= DQS_Captured_Write_DM_Odd;
|
676 |
|
|
end
|
677 |
|
|
|
678 |
32 |
bbeaver |
// For Writes, the CAS Address comes in at time T0.
|
679 |
31 |
bbeaver |
// Data is available on the external DQ wires at time T1 and T2;
|
680 |
|
|
// Data is available as Sync_Write_Data at times T2 and T3
|
681 |
|
|
// The SRAM can be written as soon as the last data is available,
|
682 |
|
|
// which seems to be at T4.
|
683 |
|
|
//
|
684 |
|
|
// For Reads, the Address comes in at time T0.
|
685 |
|
|
// The DQS signal needs to start being driven to 1'b0 at T1
|
686 |
|
|
// The DQ signals need to start being driven with valid data at T2
|
687 |
|
|
// Both DQS and DQ need to be valid until the beginning of T4
|
688 |
|
|
//
|
689 |
|
|
// At first glance, it would seem that the Read Data needs to be
|
690 |
|
|
// grabbed out of the DRAM before, or at the same time, as the
|
691 |
|
|
// data is written into the DRAM.
|
692 |
|
|
// Fortunately, the parameter TWTR says that there must be 1 extra
|
693 |
|
|
// clock between a Write and a Read to serve as a Write Recovery
|
694 |
|
|
// time. Write data is available out of the internal Sync DRAM
|
695 |
|
|
// storage element in plenty of time to get to the bus.
|
696 |
|
|
|
697 |
32 |
bbeaver |
reg [NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0] DRAM_Address_T1;
|
698 |
|
|
reg [NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0] DRAM_Address_T2;
|
699 |
|
|
reg [NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0] DRAM_Address_T3;
|
700 |
|
|
reg [1:0] BANK_Address_T1, BANK_Address_T2, BANK_Address_T3;
|
701 |
|
|
reg DRAM_Read_T1, DRAM_Read_T2, DRAM_Read_T3;
|
702 |
|
|
reg DRAM_Full_Addr_Valid_T1, DRAM_Full_Addr_Valid_T2, DRAM_Full_Addr_Valid_T3;
|
703 |
|
|
reg [NUM_DATA_BITS - 1 : 0] Delayed_Sync_Write_Data_Even_T3;
|
704 |
|
|
reg [NUM_DATA_BITS - 1 : 0] Delayed_Sync_Write_Data_Odd_T3;
|
705 |
31 |
bbeaver |
|
706 |
|
|
// Pipeline delay the Read and Write address so that it stays available
|
707 |
|
|
// all the way up to the time the data is available and the whole
|
708 |
|
|
// lot of it is written to storage.
|
709 |
|
|
|
710 |
32 |
bbeaver |
always @(posedge CLK_P)
|
711 |
|
|
begin
|
712 |
|
|
DRAM_Address_T1[NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0] <=
|
713 |
|
|
{Captured_RAS_Address[NUM_ADDR_BITS - 1 : 0],
|
714 |
|
|
Captured_CAS_Address[NUM_COL_BITS - 1 : 11], // skip address bit 10
|
715 |
|
|
Captured_CAS_Address[9 : 0]};
|
716 |
|
|
DRAM_Address_T2[NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0] <=
|
717 |
|
|
DRAM_Address_T1[NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0];
|
718 |
|
|
DRAM_Address_T3[NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0] <=
|
719 |
|
|
DRAM_Address_T2[NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0];
|
720 |
|
|
BANK_Address_T1[1:0] <= Captured_CAS_Bank_Selects[1:0];
|
721 |
|
|
BANK_Address_T2[1:0] <= BANK_Address_T1[1:0];
|
722 |
|
|
BANK_Address_T3[1:0] <= BANK_Address_T2[1:0];
|
723 |
|
|
DRAM_Read_T1 <= DRAM_Read_Requested;
|
724 |
|
|
DRAM_Read_T2 <= DRAM_Read_T1;
|
725 |
|
|
DRAM_Read_T3 <= DRAM_Read_T2;
|
726 |
|
|
DRAM_Full_Addr_Valid_T1 <= Full_Address_Valid;
|
727 |
|
|
DRAM_Full_Addr_Valid_T2 <= DRAM_Full_Addr_Valid_T1;
|
728 |
|
|
DRAM_Full_Addr_Valid_T3 <= DRAM_Full_Addr_Valid_T2;
|
729 |
|
|
Delayed_Sync_Write_Data_Even_T3[NUM_DATA_BITS - 1 : 0] <=
|
730 |
|
|
Sync_Write_Data_Even[NUM_DATA_BITS - 1 : 0];
|
731 |
|
|
Delayed_Sync_Write_Data_Odd_T3[NUM_DATA_BITS - 1 : 0] <=
|
732 |
|
|
Sync_Write_Data_Odd[NUM_DATA_BITS - 1 : 0];
|
733 |
|
|
end
|
734 |
31 |
bbeaver |
|
735 |
32 |
bbeaver |
|
736 |
|
|
assign DQ_E_oe = 1'b0;
|
737 |
|
|
assign DQ_O_oe = 1'b0;
|
738 |
|
|
assign DQS_E_oe = 1'b0;
|
739 |
|
|
assign DQS_O_oe = 1'b0;
|
740 |
|
|
|
741 |
30 |
bbeaver |
// Storage
|
742 |
|
|
|
743 |
32 |
bbeaver |
wire [(4 * NUM_DATA_BITS) - 1 : 0] write_data =
|
744 |
|
|
{Sync_Write_Data_Odd[NUM_DATA_BITS - 1 : 0],
|
745 |
|
|
Sync_Write_Data_Even[NUM_DATA_BITS - 1 : 0],
|
746 |
|
|
Delayed_Sync_Write_Data_Odd_T3[NUM_DATA_BITS - 1 : 0],
|
747 |
|
|
Delayed_Sync_Write_Data_Even_T3[NUM_DATA_BITS - 1 : 0]};
|
748 |
|
|
wire [(4 * NUM_DATA_BITS) - 1 : 0] read_data;
|
749 |
|
|
|
750 |
30 |
bbeaver |
sram_for_debugging_sync
|
751 |
31 |
bbeaver |
# ( NUM_ADDR_BITS + NUM_COL_BITS,
|
752 |
|
|
4 * NUM_DATA_BITS // NUM_DATA_BITS
|
753 |
30 |
bbeaver |
) storage (
|
754 |
32 |
bbeaver |
.data_out (read_data[(4 * NUM_DATA_BITS) - 1 : 0]),
|
755 |
|
|
.data_in (write_data[(4 * NUM_DATA_BITS) - 1 : 0]),
|
756 |
|
|
.address (DRAM_Address_T3[NUM_ADDR_BITS + NUM_COL_BITS - 1 : 0]),
|
757 |
|
|
.read_enable (DRAM_Full_Addr_Valid_T3 & DRAM_Read_T3),
|
758 |
|
|
.write_enable (DRAM_Full_Addr_Valid_T3 & ~DRAM_Read_T3),
|
759 |
30 |
bbeaver |
.clk (CLK_P)
|
760 |
|
|
);
|
761 |
|
|
|
762 |
26 |
bbeaver |
// These are the important DDR DRAM timing specs in nanoseconds:
|
763 |
27 |
bbeaver |
parameter LOAD_MODE_REGISTER_PERIOD_TMRD = 15.0; // stay idle after load mode
|
764 |
28 |
bbeaver |
parameter ACT_A_TO_ACT_B_TRRD = 15.0; // Activate-to-activate minimum time
|
765 |
|
|
parameter ACT_TO_READ_OR_WRITE_TRCD = 20.0;
|
766 |
|
|
parameter ACT_TO_PRECHARGE_TRAS = 40.0;
|
767 |
|
|
parameter ACT_TO_REFRESH_TRC = 65.0;
|
768 |
|
|
parameter ACT_A_TO_ACT_A_TRC = 65.0; // needed if failover
|
769 |
27 |
bbeaver |
parameter WRITE_RECOVERY_TO_PRECHARGE_TWR = 15.0;
|
770 |
|
|
parameter PRECHARGE_PERIOD_TRP = 20.0;
|
771 |
|
|
parameter REFRESH_PERIOD_TRFC = 75.0;
|
772 |
25 |
bbeaver |
|
773 |
27 |
bbeaver |
parameter CLOCK_PERIOD = (1.0 / FREQUENCY);
|
774 |
|
|
|
775 |
26 |
bbeaver |
// These timing requirements become CYCLE requirements, depending on the
|
776 |
|
|
// operating frequency. Note that 133.333 MHz = 7.5 nSec;
|
777 |
27 |
bbeaver |
// These calculations assume that 133 MHz is the fastest this circuit will run.
|
778 |
|
|
// These are calculated by doing (N * 1/period) for N big enough to result in > 85 MHz.
|
779 |
|
|
// Each 1/period gives a frequency to test for, and each N gives the cycle count.
|
780 |
|
|
// Example: 20 nSec gives N * 50 MHz. So for N == 2, that gives 100 MHz > 85 MHz.
|
781 |
|
|
// If FREQUENCY > 100 MHz, use N = 2, else use N = 1;
|
782 |
|
|
// The cycle count is the number of cycles to HOLD OFF doing the next command.
|
783 |
|
|
// p.s. Note I don't know how to take the integer part of something in verilog!
|
784 |
26 |
bbeaver |
|
785 |
29 |
bbeaver |
parameter LOAD_MODE_REGISTER_CYCLES = (FREQUENCY > 133.334) ? 3 : 2;
|
786 |
|
|
parameter ACT_A_TO_ACT_B_CYCLES = (FREQUENCY > 133.334) ? 3 : 2;
|
787 |
|
|
parameter ACT_TO_READ_OR_WRITE_CYCLES = (FREQUENCY > 100.000) ? 3 : 2;
|
788 |
|
|
parameter ACT_TO_PRECHARGE_CYCLES = (FREQUENCY > 125.000) ? 6
|
789 |
|
|
: ((FREQUENCY > 100.000) ? 5 : 4);
|
790 |
|
|
// parameter ACK_TO_REFRESH_CYCLES = (FREQUENCY > 123.075) ? 9
|
791 |
|
|
// : ((FREQUENCY > 107.690) ? 8
|
792 |
|
|
// : ((FREQUENCY > 92.300) ? 7 : 6));
|
793 |
|
|
parameter ACT_A_TO_ACT_A_CYCLES = (FREQUENCY > 123.075) ? 9
|
794 |
|
|
: ((FREQUENCY > 107.690) ? 8
|
795 |
|
|
: ((FREQUENCY > 92.300) ? 7 : 6));
|
796 |
|
|
parameter READ_TO_WRITE_CYCLES = (LATENCY > 4.0) ? 5
|
797 |
|
|
: ((LATENCY > 3.0) ? 4
|
798 |
|
|
: ((LATENCY > 2.0) ? 3 : 2));
|
799 |
|
|
parameter WRITE_TO_READ_CYCLES = 2;
|
800 |
|
|
parameter WRITE_RECOVERY_TO_PRECHARGE_CYCLES = (FREQUENCY > 133.334) ? 3 : 2;
|
801 |
|
|
parameter PRECHARGE_CYCLES = (FREQUENCY > 100.000) ? 3 : 2;
|
802 |
|
|
parameter REFRESH_CYCLES = (FREQUENCY > 133.334) ? 11
|
803 |
|
|
: ((FREQUENCY > 120.000) ? 10
|
804 |
|
|
: ((FREQUENCY > 106.667) ? 9
|
805 |
|
|
: ((FREQUENCY > 93.330) ? 8 : 7)));
|
806 |
27 |
bbeaver |
|
807 |
26 |
bbeaver |
// The DDR-II DRAM has 4 banks. Each bank can operate independently, with
|
808 |
|
|
// only a few exceptions.
|
809 |
|
|
//
|
810 |
|
|
// Each bank needs counters to
|
811 |
|
|
// 1) prevent refresh too soon after activate
|
812 |
|
|
// 2) prevent activate to same bank too soon after activate
|
813 |
|
|
// 3) prevent activate to alternate bank too soon after activate
|
814 |
|
|
// 4) prevent (or notice) precharge too soon after activate
|
815 |
|
|
// 5) count out autorefresh delay
|
816 |
|
|
|
817 |
29 |
bbeaver |
reg [3:0] load_mode_delay_counter;
|
818 |
28 |
bbeaver |
reg [3:0] act_a_to_act_b_counter;
|
819 |
|
|
reg [3:0] act_to_read_or_write_counter;
|
820 |
|
|
reg [3:0] act_to_precharge_counter;
|
821 |
|
|
reg [3:0] act_a_to_act_a_counter; // double use for act_to_refresh and act_a_to_act_a
|
822 |
27 |
bbeaver |
reg [3:0] burst_counter;
|
823 |
29 |
bbeaver |
reg [3:0] read_to_write_counter;
|
824 |
|
|
reg [3:0] write_to_read_counter;
|
825 |
27 |
bbeaver |
reg [3:0] write_recovery_counter;
|
826 |
|
|
reg [3:0] precharge_counter;
|
827 |
|
|
reg [3:0] refresh_counter;
|
828 |
26 |
bbeaver |
|
829 |
27 |
bbeaver |
parameter POWER_ON = 0;
|
830 |
|
|
parameter WRITING_REG = 1;
|
831 |
|
|
parameter BANK_IDLE = 2;
|
832 |
|
|
parameter ACTIVATING = 3;
|
833 |
|
|
parameter WRITING = 4;
|
834 |
|
|
parameter WRITING_PRECHARGE = 5;
|
835 |
|
|
parameter READING = 6;
|
836 |
|
|
parameter READING_PRECHARGE = 7;
|
837 |
|
|
parameter PRECHARGING = 8;
|
838 |
|
|
parameter REFRESHING = 9;
|
839 |
29 |
bbeaver |
parameter WAITING_FOR_AUTO_PRECHARGE = 10;
|
840 |
26 |
bbeaver |
|
841 |
27 |
bbeaver |
parameter BANK_STATE_WIDTH = 4;
|
842 |
26 |
bbeaver |
|
843 |
27 |
bbeaver |
reg [BANK_STATE_WIDTH - 1 : 0] bank_state;
|
844 |
|
|
reg Timing_Error;
|
845 |
26 |
bbeaver |
|
846 |
|
|
initial
|
847 |
|
|
begin // nail state to known at the start of simulation
|
848 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] = POWER_ON; // nail it to known at the start of simulation
|
849 |
26 |
bbeaver |
end
|
850 |
|
|
|
851 |
|
|
always @(posedge CLK_P)
|
852 |
|
|
begin
|
853 |
32 |
bbeaver |
if (ENABLE_TIMING_CHECKS != 0)
|
854 |
|
|
begin // if out the entire case statement!
|
855 |
27 |
bbeaver |
case (bank_state[BANK_STATE_WIDTH - 1 : 0])
|
856 |
26 |
bbeaver |
POWER_ON:
|
857 |
|
|
begin
|
858 |
|
|
if ( (control_wires[4] == 1'b0) // powered off
|
859 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
860 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
861 |
|
|
begin
|
862 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= POWER_ON;
|
863 |
|
|
Timing_Error <= 1'b0;
|
864 |
26 |
bbeaver |
end
|
865 |
|
|
else if (control_wires[4:0] == LOAD_MODE) // no bank involved
|
866 |
|
|
begin
|
867 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_REG;
|
868 |
|
|
Timing_Error <= 1'b0;
|
869 |
26 |
bbeaver |
end
|
870 |
|
|
else
|
871 |
|
|
begin
|
872 |
|
|
$display ("*** %m DDR DRAM needs to have a LOAD MODE REGISTER before any other command %t", $time);
|
873 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= POWER_ON;
|
874 |
|
|
Timing_Error <= 1'b1;
|
875 |
26 |
bbeaver |
end
|
876 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= LOAD_MODE_REGISTER_CYCLES;
|
877 |
28 |
bbeaver |
act_a_to_act_b_counter[3:0] <= 4'h0;
|
878 |
|
|
act_to_read_or_write_counter[3:0] <= 4'h0;
|
879 |
|
|
act_to_precharge_counter[3:0] <= 4'h0;
|
880 |
|
|
act_a_to_act_a_counter[3:0] <= 4'h0;
|
881 |
27 |
bbeaver |
burst_counter[3:0] <= 4'h0;
|
882 |
29 |
bbeaver |
read_to_write_counter [3:0] <= 4'h0;
|
883 |
|
|
write_to_read_counter [3:0] <= 4'h0;
|
884 |
27 |
bbeaver |
write_recovery_counter[3:0] <= 4'h0;
|
885 |
|
|
precharge_counter[3:0] <= 4'h0;
|
886 |
|
|
refresh_counter[3:0] <= 4'h0;
|
887 |
26 |
bbeaver |
end
|
888 |
28 |
bbeaver |
|
889 |
27 |
bbeaver |
WRITING_REG:
|
890 |
|
|
begin
|
891 |
29 |
bbeaver |
if ( (control_wires[4] == 1'b0) // powered off
|
892 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
893 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
894 |
27 |
bbeaver |
begin
|
895 |
29 |
bbeaver |
if (load_mode_delay_counter[3:0] > 4'h2) // looping
|
896 |
27 |
bbeaver |
begin
|
897 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_REG;
|
898 |
|
|
Timing_Error <= 1'b0;
|
899 |
|
|
end
|
900 |
|
|
else
|
901 |
|
|
begin
|
902 |
29 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
903 |
|
|
Timing_Error <= 1'b0;
|
904 |
|
|
end
|
905 |
|
|
end
|
906 |
|
|
else // nothing else legal until load mode finished
|
907 |
|
|
begin
|
908 |
|
|
if (load_mode_delay_counter[3:0] > 4'h2) // looping
|
909 |
|
|
begin
|
910 |
27 |
bbeaver |
$display ("*** %m DDR DRAM cannot accept any other command while doing a LOAD MODE REGISTER command %t", $time);
|
911 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_REG;
|
912 |
|
|
Timing_Error <= 1'b1;
|
913 |
|
|
end
|
914 |
29 |
bbeaver |
else
|
915 |
|
|
begin
|
916 |
|
|
$display ("*** %m DDR DRAM cannot accept any other command while doing a LOAD MODE REGISTER command %t", $time);
|
917 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
918 |
|
|
Timing_Error <= 1'b1;
|
919 |
|
|
end
|
920 |
27 |
bbeaver |
end
|
921 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= (load_mode_delay_counter[3:0] != 4'h0)
|
922 |
|
|
? (load_mode_delay_counter[3:0] - 4'h1) : 4'h0;
|
923 |
28 |
bbeaver |
act_a_to_act_b_counter[3:0] <= 4'h0;
|
924 |
|
|
act_to_read_or_write_counter[3:0] <= 4'h0;
|
925 |
|
|
act_to_precharge_counter[3:0] <= 4'h0;
|
926 |
|
|
act_a_to_act_a_counter[3:0] <= 4'h0;
|
927 |
27 |
bbeaver |
burst_counter[3:0] <= 4'h0;
|
928 |
29 |
bbeaver |
read_to_write_counter [3:0] <= 4'h0;
|
929 |
|
|
write_to_read_counter [3:0] <= 4'h0;
|
930 |
27 |
bbeaver |
write_recovery_counter[3:0] <= 4'h0;
|
931 |
|
|
precharge_counter[3:0] <= 4'h0;
|
932 |
|
|
refresh_counter[3:0] <= 4'h0;
|
933 |
|
|
end
|
934 |
26 |
bbeaver |
|
935 |
27 |
bbeaver |
// All interesting work starts here, except for read, write followed by read, write, precharge
|
936 |
|
|
BANK_IDLE:
|
937 |
26 |
bbeaver |
begin
|
938 |
|
|
if ( (control_wires[4] == 1'b0) // powered off
|
939 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
940 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
941 |
|
|
begin
|
942 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
943 |
|
|
Timing_Error <= 1'b0;
|
944 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
945 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
946 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
947 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
948 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
949 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
950 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
951 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
952 |
26 |
bbeaver |
end
|
953 |
27 |
bbeaver |
else if (control_wires[4:0] == LOAD_MODE) // no bank involved
|
954 |
|
|
begin
|
955 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_REG;
|
956 |
|
|
Timing_Error <= 1'b0;
|
957 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
958 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
959 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
960 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
961 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
962 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
963 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
964 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
965 |
27 |
bbeaver |
end
|
966 |
|
|
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
967 |
|
|
begin
|
968 |
|
|
if (BA[1:0] == bank_num[1:0])
|
969 |
|
|
begin
|
970 |
28 |
bbeaver |
if (act_a_to_act_a_counter[3:0] > 4'h1)
|
971 |
27 |
bbeaver |
begin
|
972 |
28 |
bbeaver |
$display ("*** %m DDR DRAM cannot do an ACT too soon after another ACT to the same bank %t", $time);
|
973 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
974 |
|
|
Timing_Error <= 1'b1;
|
975 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
976 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
977 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
978 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
979 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
980 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
981 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
982 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
983 |
27 |
bbeaver |
end
|
984 |
|
|
else
|
985 |
|
|
begin
|
986 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
987 |
|
|
Timing_Error <= 1'b0;
|
988 |
28 |
bbeaver |
act_a_to_act_b_counter[3:0] <= ACT_A_TO_ACT_B_CYCLES;
|
989 |
|
|
act_to_read_or_write_counter[3:0] <= ACT_TO_READ_OR_WRITE_CYCLES;
|
990 |
|
|
act_to_precharge_counter[3:0] <= ACT_TO_PRECHARGE_CYCLES;
|
991 |
|
|
act_a_to_act_a_counter[3:0] <= ACT_A_TO_ACT_A_CYCLES;
|
992 |
27 |
bbeaver |
end
|
993 |
|
|
end
|
994 |
28 |
bbeaver |
else // some other bank
|
995 |
29 |
bbeaver |
begin
|
996 |
|
|
if (act_a_to_act_b_counter[3:0] > 4'h1)
|
997 |
|
|
begin
|
998 |
|
|
$display ("*** %m DDR DRAM cannot do an ACT too soon after another ACT to the same bank %t", $time);
|
999 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1000 |
|
|
Timing_Error <= 1'b1;
|
1001 |
|
|
end
|
1002 |
|
|
else
|
1003 |
|
|
begin
|
1004 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1005 |
|
|
Timing_Error <= 1'b0;
|
1006 |
|
|
end
|
1007 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1008 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1009 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1010 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1011 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1012 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1013 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1014 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1015 |
27 |
bbeaver |
end
|
1016 |
|
|
end
|
1017 |
28 |
bbeaver |
else if ((control_wires[4:0] == READ_BANK) & (BA[1:0] != bank_num[1:0]))
|
1018 |
27 |
bbeaver |
begin
|
1019 |
28 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1020 |
|
|
Timing_Error <= 1'b0;
|
1021 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1022 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1023 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1024 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1025 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1026 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1027 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1028 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1029 |
|
|
end
|
1030 |
|
|
else if ((control_wires[4:0] == WRITE_BANK) & (BA[1:0] != bank_num[1:0]))
|
1031 |
|
|
begin
|
1032 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1033 |
|
|
Timing_Error <= 1'b0;
|
1034 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1035 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1036 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1037 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1038 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1039 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1040 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1041 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1042 |
|
|
end
|
1043 |
|
|
else if (control_wires[4:0] == PRECHARGE_BANK)
|
1044 |
|
|
begin
|
1045 |
|
|
if ((BA[1:0] == bank_num[1:0]) | (A[10] == 1'b1))
|
1046 |
27 |
bbeaver |
begin
|
1047 |
29 |
bbeaver |
if (act_to_precharge_counter[3:0] > 4'h1)
|
1048 |
28 |
bbeaver |
begin
|
1049 |
|
|
$display ("*** %m DDR DRAM cannot do an PRECHARGE too soon after ACTIVATE %t", $time);
|
1050 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1051 |
|
|
Timing_Error <= 1'b1;
|
1052 |
|
|
end
|
1053 |
|
|
else // ignore precharges when in idle state
|
1054 |
|
|
begin
|
1055 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1056 |
|
|
Timing_Error <= 1'b0;
|
1057 |
|
|
end
|
1058 |
27 |
bbeaver |
end
|
1059 |
|
|
else
|
1060 |
|
|
begin
|
1061 |
28 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1062 |
27 |
bbeaver |
Timing_Error <= 1'b0;
|
1063 |
|
|
end
|
1064 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1065 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1066 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1067 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1068 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1069 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1070 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1071 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1072 |
27 |
bbeaver |
end
|
1073 |
|
|
else if (control_wires[4:0] == REFRESH_BANK) // all already precharged
|
1074 |
|
|
begin
|
1075 |
28 |
bbeaver |
if (act_a_to_act_a_counter[3:0] > 4'h1)
|
1076 |
27 |
bbeaver |
begin
|
1077 |
28 |
bbeaver |
$display ("*** %m DDR DRAM cannot do an REFRESH too soon after ACTIVATE %t", $time);
|
1078 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1079 |
|
|
Timing_Error <= 1'b1;
|
1080 |
|
|
end
|
1081 |
|
|
else
|
1082 |
|
|
begin
|
1083 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= REFRESHING;
|
1084 |
|
|
Timing_Error <= 1'b0;
|
1085 |
|
|
end
|
1086 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1087 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1088 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1089 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1090 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1091 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1092 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1093 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1094 |
27 |
bbeaver |
end
|
1095 |
26 |
bbeaver |
else
|
1096 |
|
|
begin
|
1097 |
27 |
bbeaver |
$display ("*** %m DDR DRAM can only do Activate, Refresh, Precharge, or Load Mode Register from Idle %t", $time);
|
1098 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1099 |
|
|
Timing_Error <= 1'b1;
|
1100 |
29 |
bbeaver |
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1101 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1102 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1103 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1104 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1105 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1106 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1107 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1108 |
26 |
bbeaver |
end
|
1109 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= LOAD_MODE_REGISTER_CYCLES;
|
1110 |
27 |
bbeaver |
burst_counter[3:0] <= 4'h0;
|
1111 |
29 |
bbeaver |
read_to_write_counter [3:0] <= 4'h0;
|
1112 |
|
|
write_to_read_counter [3:0] <= 4'h0;
|
1113 |
|
|
write_recovery_counter[3:0] <= (write_recovery_counter[3:0] != 4'h0)
|
1114 |
|
|
? (write_recovery_counter[3:0] - 4'h1) : 4'h0;
|
1115 |
|
|
precharge_counter[3:0] <= (precharge_counter[3:0] != 4'h0)
|
1116 |
|
|
? (precharge_counter[3:0] - 4'h1) : 4'h0;
|
1117 |
27 |
bbeaver |
refresh_counter[3:0] <= REFRESH_CYCLES;
|
1118 |
26 |
bbeaver |
end
|
1119 |
|
|
|
1120 |
27 |
bbeaver |
ACTIVATING:
|
1121 |
26 |
bbeaver |
begin
|
1122 |
|
|
if ( (control_wires[4] == 1'b0) // powered off
|
1123 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
1124 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
1125 |
|
|
begin
|
1126 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1127 |
|
|
Timing_Error <= 1'b0;
|
1128 |
26 |
bbeaver |
end
|
1129 |
28 |
bbeaver |
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
1130 |
27 |
bbeaver |
begin
|
1131 |
28 |
bbeaver |
if (BA[1:0] == bank_num[1:0])
|
1132 |
27 |
bbeaver |
begin
|
1133 |
28 |
bbeaver |
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is already Activated %t", $time);
|
1134 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1135 |
|
|
Timing_Error <= 1'b1;
|
1136 |
|
|
end
|
1137 |
|
|
else
|
1138 |
|
|
begin
|
1139 |
28 |
bbeaver |
if (act_a_to_act_b_counter[3:0] > 4'h1)
|
1140 |
|
|
begin
|
1141 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a different bank too soon after this bank is Activated %t", $time);
|
1142 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1143 |
|
|
Timing_Error <= 1'b1;
|
1144 |
|
|
end
|
1145 |
27 |
bbeaver |
else
|
1146 |
28 |
bbeaver |
begin
|
1147 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1148 |
|
|
Timing_Error <= 1'b0;
|
1149 |
|
|
end
|
1150 |
|
|
end
|
1151 |
|
|
end
|
1152 |
|
|
else if (control_wires[4:0] == READ_BANK) // no bank involved
|
1153 |
|
|
begin
|
1154 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1155 |
|
|
begin
|
1156 |
|
|
if (act_to_read_or_write_counter[3:0] > 4'h1)
|
1157 |
|
|
begin
|
1158 |
|
|
$display ("*** %m DDR DRAM has to wait from Activate to Read %t", $time);
|
1159 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1160 |
|
|
Timing_Error <= 1'b1;
|
1161 |
|
|
end
|
1162 |
29 |
bbeaver |
else if (write_to_read_counter[3:0] > 4'h1)
|
1163 |
|
|
begin
|
1164 |
|
|
$display ("*** %m DDR DRAM has to wait from Write to Read %t", $time);
|
1165 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1166 |
|
|
Timing_Error <= 1'b1;
|
1167 |
|
|
end
|
1168 |
28 |
bbeaver |
else
|
1169 |
|
|
begin
|
1170 |
|
|
if (A[10] == 1'b1)
|
1171 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1172 |
|
|
else
|
1173 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1174 |
|
|
Timing_Error <= 1'b0;
|
1175 |
|
|
end
|
1176 |
|
|
end
|
1177 |
|
|
else
|
1178 |
|
|
begin
|
1179 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1180 |
27 |
bbeaver |
Timing_Error <= 1'b0;
|
1181 |
|
|
end
|
1182 |
|
|
end
|
1183 |
|
|
else if (control_wires[4:0] == WRITE_BANK) // no bank involved
|
1184 |
|
|
begin
|
1185 |
28 |
bbeaver |
if (BA[1:0] == bank_num[1:0])
|
1186 |
27 |
bbeaver |
begin
|
1187 |
28 |
bbeaver |
if (act_to_read_or_write_counter[3:0] > 4'h1)
|
1188 |
|
|
begin
|
1189 |
|
|
$display ("*** %m DDR DRAM has to wait from Activate to Write %t", $time);
|
1190 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1191 |
|
|
Timing_Error <= 1'b1;
|
1192 |
|
|
end
|
1193 |
29 |
bbeaver |
else if (read_to_write_counter[3:0] > 4'h1)
|
1194 |
|
|
begin
|
1195 |
|
|
$display ("*** %m DDR DRAM has to wait from Read to Write %t", $time);
|
1196 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1197 |
|
|
Timing_Error <= 1'b1;
|
1198 |
|
|
end
|
1199 |
28 |
bbeaver |
else
|
1200 |
|
|
begin
|
1201 |
|
|
if (A[10] == 1'b1)
|
1202 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1203 |
|
|
else
|
1204 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1205 |
|
|
Timing_Error <= 1'b0;
|
1206 |
|
|
end
|
1207 |
27 |
bbeaver |
end
|
1208 |
|
|
else
|
1209 |
|
|
begin
|
1210 |
28 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1211 |
27 |
bbeaver |
Timing_Error <= 1'b0;
|
1212 |
|
|
end
|
1213 |
|
|
end
|
1214 |
28 |
bbeaver |
else if (control_wires[4:0] == PRECHARGE_BANK) // only do precharge if this bank is addressed
|
1215 |
27 |
bbeaver |
begin
|
1216 |
28 |
bbeaver |
if ((BA[1:0] == bank_num[1:0]) | (A[10] == 1'b1))
|
1217 |
27 |
bbeaver |
begin
|
1218 |
28 |
bbeaver |
if (act_to_precharge_counter[3:0] > 4'h1)
|
1219 |
|
|
begin
|
1220 |
|
|
$display ("*** %m DDR DRAM has to wait from Activate to Precharge %t", $time);
|
1221 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1222 |
|
|
Timing_Error <= 1'b1;
|
1223 |
|
|
end
|
1224 |
29 |
bbeaver |
else if (write_recovery_counter[3:0] > 4'h1)
|
1225 |
|
|
begin
|
1226 |
|
|
$display ("*** %m DDR DRAM has to wait from end of Write to Precharge %t", $time);
|
1227 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1228 |
|
|
Timing_Error <= 1'b1;
|
1229 |
|
|
end
|
1230 |
28 |
bbeaver |
else
|
1231 |
|
|
begin
|
1232 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1233 |
|
|
Timing_Error <= 1'b0;
|
1234 |
|
|
end
|
1235 |
27 |
bbeaver |
end
|
1236 |
|
|
else
|
1237 |
|
|
begin
|
1238 |
28 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1239 |
27 |
bbeaver |
Timing_Error <= 1'b0;
|
1240 |
|
|
end
|
1241 |
|
|
end
|
1242 |
26 |
bbeaver |
else
|
1243 |
|
|
begin
|
1244 |
27 |
bbeaver |
$display ("*** %m DDR DRAM can only do Read, Write, or Precharge from Activated %t", $time);
|
1245 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1246 |
|
|
Timing_Error <= 1'b1;
|
1247 |
26 |
bbeaver |
end
|
1248 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= 4'h0;
|
1249 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1250 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1251 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1252 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1253 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1254 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1255 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1256 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1257 |
|
|
burst_counter[3:0] <= 4'h2;
|
1258 |
29 |
bbeaver |
read_to_write_counter [3:0] <= (read_to_write_counter[3:0] != 4'h0)
|
1259 |
|
|
? (read_to_write_counter[3:0] - 4'h1) : 4'h0;
|
1260 |
|
|
write_to_read_counter [3:0] <= (write_to_read_counter[3:0] != 4'h0)
|
1261 |
|
|
? (write_to_read_counter[3:0] - 4'h1) : 4'h0;
|
1262 |
|
|
write_recovery_counter[3:0] <= (write_recovery_counter[3:0] != 4'h0)
|
1263 |
|
|
? (write_recovery_counter[3:0] - 4'h1) : 4'h0;
|
1264 |
27 |
bbeaver |
precharge_counter[3:0] <= PRECHARGE_CYCLES;
|
1265 |
|
|
refresh_counter[3:0] <= 4'h0;
|
1266 |
26 |
bbeaver |
end
|
1267 |
|
|
|
1268 |
27 |
bbeaver |
WRITING:
|
1269 |
26 |
bbeaver |
begin
|
1270 |
|
|
if ( (control_wires[4] == 1'b0) // powered off
|
1271 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
1272 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
1273 |
|
|
begin
|
1274 |
28 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1275 |
|
|
begin
|
1276 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1277 |
|
|
Timing_Error <= 1'b0;
|
1278 |
|
|
end
|
1279 |
|
|
else
|
1280 |
|
|
begin
|
1281 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1282 |
|
|
Timing_Error <= 1'b0;
|
1283 |
|
|
end
|
1284 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1285 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1286 |
26 |
bbeaver |
end
|
1287 |
28 |
bbeaver |
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
1288 |
|
|
begin
|
1289 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1290 |
|
|
begin
|
1291 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is being Written %t", $time);
|
1292 |
|
|
Timing_Error <= 1'b1;
|
1293 |
|
|
end
|
1294 |
|
|
else
|
1295 |
|
|
begin
|
1296 |
|
|
if (act_a_to_act_b_counter[3:0] > 4'h1)
|
1297 |
|
|
begin
|
1298 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a different bank too soon after this bank is Activated %t", $time);
|
1299 |
|
|
Timing_Error <= 1'b1;
|
1300 |
|
|
end
|
1301 |
|
|
else
|
1302 |
|
|
begin
|
1303 |
|
|
Timing_Error <= 1'b0;
|
1304 |
|
|
end
|
1305 |
|
|
end
|
1306 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1307 |
|
|
begin
|
1308 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1309 |
|
|
end
|
1310 |
|
|
else
|
1311 |
|
|
begin
|
1312 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1313 |
|
|
end
|
1314 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1315 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1316 |
|
|
end
|
1317 |
|
|
else if (control_wires[4:0] == READ_BANK)
|
1318 |
|
|
begin
|
1319 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1320 |
|
|
begin
|
1321 |
29 |
bbeaver |
$display ("*** %m DDR DRAM cannot do a Read until Write completes plus recovery %t", $time);
|
1322 |
|
|
Timing_Error <= 1'b1;
|
1323 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1324 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1325 |
28 |
bbeaver |
end
|
1326 |
29 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1327 |
|
|
begin
|
1328 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1329 |
|
|
end
|
1330 |
28 |
bbeaver |
else
|
1331 |
|
|
begin
|
1332 |
29 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1333 |
28 |
bbeaver |
end
|
1334 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1335 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1336 |
28 |
bbeaver |
end
|
1337 |
|
|
else if (control_wires[4:0] == WRITE_BANK)
|
1338 |
|
|
begin
|
1339 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1340 |
|
|
begin
|
1341 |
29 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1342 |
|
|
begin
|
1343 |
|
|
$display ("*** %m DDR DRAM cannot do a Write to a bank until the previous Write completes %t", $time);
|
1344 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING; // might want to go to activate!
|
1345 |
|
|
Timing_Error <= 1'b1;
|
1346 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1347 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1348 |
|
|
end
|
1349 |
28 |
bbeaver |
else
|
1350 |
29 |
bbeaver |
begin
|
1351 |
|
|
if (A[10] == 1'b1)
|
1352 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1353 |
|
|
else
|
1354 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1355 |
|
|
Timing_Error <= 1'b0;
|
1356 |
|
|
burst_counter[3:0] <= 4'h2;
|
1357 |
|
|
end
|
1358 |
28 |
bbeaver |
end
|
1359 |
29 |
bbeaver |
else // was to a different bank. We are done
|
1360 |
28 |
bbeaver |
begin
|
1361 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1362 |
|
|
begin
|
1363 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1364 |
|
|
end
|
1365 |
|
|
else
|
1366 |
|
|
begin
|
1367 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1368 |
|
|
end
|
1369 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1370 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1371 |
|
|
end
|
1372 |
|
|
end
|
1373 |
|
|
else if (control_wires[4:0] == PRECHARGE_BANK) // do idles when it is safe to do so
|
1374 |
|
|
begin
|
1375 |
|
|
if ((BA[1:0] == bank_num[1:0]) | (A[10] == 1'b1))
|
1376 |
|
|
begin
|
1377 |
29 |
bbeaver |
$display ("*** %m DDR DRAM cannot do a Precharge until Write completes plus recovery %t", $time);
|
1378 |
|
|
Timing_Error <= 1'b1;
|
1379 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1380 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1381 |
|
|
end
|
1382 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1383 |
|
|
begin
|
1384 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1385 |
|
|
end
|
1386 |
|
|
else
|
1387 |
|
|
begin
|
1388 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1389 |
|
|
end
|
1390 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1391 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1392 |
|
|
end
|
1393 |
|
|
else
|
1394 |
|
|
begin
|
1395 |
|
|
$display ("*** %m DDR DRAM can only do Read, Write, or Precharge from Write %t", $time);
|
1396 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING;
|
1397 |
|
|
Timing_Error <= 1'b1;
|
1398 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1399 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1400 |
|
|
end
|
1401 |
|
|
load_mode_delay_counter[3:0] <= 4'h0;
|
1402 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1403 |
|
|
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1404 |
|
|
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1405 |
|
|
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1406 |
|
|
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1407 |
|
|
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1408 |
|
|
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1409 |
|
|
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1410 |
|
|
read_to_write_counter [3:0] <= (read_to_write_counter[3:0] != 4'h0)
|
1411 |
|
|
? (read_to_write_counter[3:0] - 4'h1) : 4'h0;
|
1412 |
|
|
write_to_read_counter [3:0] <= WRITE_TO_READ_CYCLES;
|
1413 |
|
|
write_recovery_counter[3:0] <= WRITE_RECOVERY_TO_PRECHARGE_CYCLES + 1; // to let write finish!
|
1414 |
|
|
precharge_counter[3:0] <= PRECHARGE_CYCLES;
|
1415 |
|
|
refresh_counter[3:0] <= 4'h0;
|
1416 |
|
|
end
|
1417 |
|
|
|
1418 |
|
|
WRITING_PRECHARGE:
|
1419 |
|
|
begin
|
1420 |
|
|
if ( (control_wires[4] == 1'b0) // powered off
|
1421 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
1422 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
1423 |
|
|
begin
|
1424 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1425 |
|
|
begin
|
1426 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1427 |
|
|
Timing_Error <= 1'b0;
|
1428 |
|
|
end
|
1429 |
|
|
else
|
1430 |
|
|
begin
|
1431 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1432 |
|
|
Timing_Error <= 1'b0;
|
1433 |
|
|
end
|
1434 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1435 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1436 |
|
|
end
|
1437 |
|
|
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
1438 |
|
|
begin
|
1439 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1440 |
|
|
begin
|
1441 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is being Written %t", $time);
|
1442 |
|
|
Timing_Error <= 1'b1;
|
1443 |
|
|
end
|
1444 |
|
|
else
|
1445 |
|
|
begin
|
1446 |
|
|
if (act_a_to_act_b_counter[3:0] > 4'h1)
|
1447 |
28 |
bbeaver |
begin
|
1448 |
29 |
bbeaver |
$display ("*** %m DDR DRAM cannot do an Activate to a different bank too soon after this bank is Activated %t", $time);
|
1449 |
28 |
bbeaver |
Timing_Error <= 1'b1;
|
1450 |
|
|
end
|
1451 |
|
|
else
|
1452 |
|
|
begin
|
1453 |
|
|
Timing_Error <= 1'b0;
|
1454 |
|
|
end
|
1455 |
|
|
end
|
1456 |
29 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1457 |
|
|
begin
|
1458 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1459 |
|
|
end
|
1460 |
28 |
bbeaver |
else
|
1461 |
|
|
begin
|
1462 |
29 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1463 |
|
|
end
|
1464 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1465 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1466 |
|
|
end
|
1467 |
|
|
else if (control_wires[4:0] == READ_BANK)
|
1468 |
|
|
begin
|
1469 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1470 |
|
|
begin
|
1471 |
|
|
$display ("*** %m DDR DRAM cannot do a Read until Write_precharge completes precharge %t", $time);
|
1472 |
|
|
Timing_Error <= 1'b1;
|
1473 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1474 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1475 |
|
|
end
|
1476 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1477 |
|
|
begin
|
1478 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1479 |
|
|
end
|
1480 |
|
|
else
|
1481 |
|
|
begin
|
1482 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1483 |
|
|
end
|
1484 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1485 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1486 |
|
|
end
|
1487 |
|
|
else if (control_wires[4:0] == WRITE_BANK)
|
1488 |
|
|
begin
|
1489 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1490 |
|
|
begin
|
1491 |
|
|
$display ("*** %m DDR DRAM cannot do a Write until Write_precharge completes precharge %t", $time);
|
1492 |
|
|
Timing_Error <= 1'b1;
|
1493 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1494 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1495 |
|
|
end
|
1496 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1497 |
|
|
begin
|
1498 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1499 |
|
|
end
|
1500 |
|
|
else
|
1501 |
|
|
begin
|
1502 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1503 |
|
|
end
|
1504 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1505 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1506 |
|
|
end
|
1507 |
|
|
else if (control_wires[4:0] == PRECHARGE_BANK) // do idles when it is safe to do so
|
1508 |
|
|
begin
|
1509 |
|
|
if ((BA[1:0] == bank_num[1:0]) | (A[10] == 1'b1))
|
1510 |
|
|
begin
|
1511 |
|
|
$display ("*** %m DDR DRAM cannot do a Precharge until Write_precharge completes plus recovery %t", $time);
|
1512 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1513 |
|
|
Timing_Error <= 1'b1;
|
1514 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1515 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1516 |
|
|
end
|
1517 |
|
|
else // was to a different bank. We are done
|
1518 |
|
|
begin
|
1519 |
28 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1520 |
|
|
begin
|
1521 |
29 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1522 |
28 |
bbeaver |
end
|
1523 |
|
|
else
|
1524 |
|
|
begin
|
1525 |
29 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1526 |
28 |
bbeaver |
end
|
1527 |
|
|
end
|
1528 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1529 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1530 |
|
|
end
|
1531 |
27 |
bbeaver |
else
|
1532 |
26 |
bbeaver |
begin
|
1533 |
29 |
bbeaver |
$display ("*** %m DDR DRAM can only wait from Write_precharge %t", $time);
|
1534 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WRITING_PRECHARGE;
|
1535 |
27 |
bbeaver |
Timing_Error <= 1'b1;
|
1536 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1537 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1538 |
26 |
bbeaver |
end
|
1539 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= 4'h0;
|
1540 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1541 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1542 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1543 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1544 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1545 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1546 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1547 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1548 |
29 |
bbeaver |
read_to_write_counter [3:0] <= (read_to_write_counter[3:0] != 4'h0)
|
1549 |
|
|
? (read_to_write_counter[3:0] - 4'h1) : 4'h0;
|
1550 |
|
|
write_to_read_counter [3:0] <= WRITE_TO_READ_CYCLES;
|
1551 |
|
|
write_recovery_counter[3:0] <= WRITE_RECOVERY_TO_PRECHARGE_CYCLES + 1; // to let write finish!
|
1552 |
28 |
bbeaver |
precharge_counter[3:0] <= PRECHARGE_CYCLES;
|
1553 |
29 |
bbeaver |
refresh_counter[3:0] <= 4'h0;
|
1554 |
27 |
bbeaver |
end
|
1555 |
28 |
bbeaver |
|
1556 |
|
|
READING:
|
1557 |
|
|
begin
|
1558 |
27 |
bbeaver |
if ( (control_wires[4] == 1'b0) // powered off
|
1559 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
1560 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
1561 |
26 |
bbeaver |
begin
|
1562 |
28 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1563 |
|
|
begin
|
1564 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1565 |
|
|
Timing_Error <= 1'b0;
|
1566 |
|
|
end
|
1567 |
26 |
bbeaver |
else
|
1568 |
28 |
bbeaver |
begin
|
1569 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1570 |
|
|
Timing_Error <= 1'b0;
|
1571 |
|
|
end
|
1572 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1573 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1574 |
26 |
bbeaver |
end
|
1575 |
28 |
bbeaver |
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
1576 |
26 |
bbeaver |
begin
|
1577 |
28 |
bbeaver |
if (BA[1:0] == bank_num[1:0])
|
1578 |
|
|
begin
|
1579 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is being Read %t", $time);
|
1580 |
|
|
Timing_Error <= 1'b1;
|
1581 |
|
|
end
|
1582 |
27 |
bbeaver |
else
|
1583 |
28 |
bbeaver |
begin
|
1584 |
|
|
if (act_a_to_act_b_counter[3:0] > 4'h1)
|
1585 |
|
|
begin
|
1586 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a different bank too soon after this bank is Activated %t", $time);
|
1587 |
|
|
Timing_Error <= 1'b1;
|
1588 |
|
|
end
|
1589 |
|
|
else
|
1590 |
|
|
begin
|
1591 |
|
|
Timing_Error <= 1'b0;
|
1592 |
|
|
end
|
1593 |
|
|
end
|
1594 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1595 |
|
|
begin
|
1596 |
27 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1597 |
28 |
bbeaver |
end
|
1598 |
|
|
else
|
1599 |
|
|
begin
|
1600 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1601 |
|
|
end
|
1602 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1603 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1604 |
26 |
bbeaver |
end
|
1605 |
28 |
bbeaver |
else if (control_wires[4:0] == READ_BANK)
|
1606 |
26 |
bbeaver |
begin
|
1607 |
28 |
bbeaver |
if (BA[1:0] == bank_num[1:0])
|
1608 |
27 |
bbeaver |
begin
|
1609 |
29 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1610 |
|
|
begin
|
1611 |
|
|
$display ("*** %m DDR DRAM cannot do a Read to a bank until the previous Read completes %t", $time);
|
1612 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1613 |
|
|
Timing_Error <= 1'b1;
|
1614 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1615 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1616 |
|
|
end
|
1617 |
28 |
bbeaver |
else
|
1618 |
29 |
bbeaver |
begin
|
1619 |
|
|
if (A[10] == 1'b1)
|
1620 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1621 |
|
|
else
|
1622 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1623 |
|
|
Timing_Error <= 1'b0;
|
1624 |
|
|
burst_counter[3:0] <= 4'h2;
|
1625 |
|
|
end
|
1626 |
27 |
bbeaver |
end
|
1627 |
29 |
bbeaver |
else // was to a different bank. We are done
|
1628 |
27 |
bbeaver |
begin
|
1629 |
28 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1630 |
|
|
begin
|
1631 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1632 |
|
|
end
|
1633 |
|
|
else
|
1634 |
|
|
begin
|
1635 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1636 |
|
|
end
|
1637 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1638 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1639 |
|
|
end
|
1640 |
|
|
end
|
1641 |
|
|
else if (control_wires[4:0] == WRITE_BANK)
|
1642 |
|
|
begin
|
1643 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1644 |
|
|
begin
|
1645 |
29 |
bbeaver |
$display ("*** %m DDR DRAM cannot do a Read until Write completes plus recovery %t", $time);
|
1646 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1647 |
|
|
Timing_Error <= 1'b1;
|
1648 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1649 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1650 |
27 |
bbeaver |
end
|
1651 |
29 |
bbeaver |
else // was to a different bank. We are done
|
1652 |
28 |
bbeaver |
begin
|
1653 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1654 |
|
|
begin
|
1655 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1656 |
|
|
end
|
1657 |
|
|
else
|
1658 |
|
|
begin
|
1659 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1660 |
|
|
end
|
1661 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1662 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1663 |
|
|
end
|
1664 |
26 |
bbeaver |
end
|
1665 |
28 |
bbeaver |
else if (control_wires[4:0] == PRECHARGE_BANK) // do idles when it is safe to do so
|
1666 |
|
|
begin
|
1667 |
|
|
if ((BA[1:0] == bank_num[1:0]) | (A[10] == 1'b1))
|
1668 |
|
|
begin
|
1669 |
29 |
bbeaver |
if (burst_counter[3:0] > 4'h1)
|
1670 |
28 |
bbeaver |
begin
|
1671 |
29 |
bbeaver |
$display ("*** %m DDR DRAM cannot do a Precharge to a bank until the previous Read completes %t", $time);
|
1672 |
28 |
bbeaver |
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1673 |
|
|
Timing_Error <= 1'b1;
|
1674 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1675 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1676 |
28 |
bbeaver |
end
|
1677 |
|
|
else
|
1678 |
|
|
begin
|
1679 |
29 |
bbeaver |
if (act_to_precharge_counter[3:0] > 4'h1)
|
1680 |
|
|
begin
|
1681 |
|
|
$display ("*** %m DDR DRAM has to wait during READ from Activate to Precharge %t", $time);
|
1682 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1683 |
|
|
Timing_Error <= 1'b1;
|
1684 |
|
|
end
|
1685 |
|
|
else
|
1686 |
|
|
begin
|
1687 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1688 |
|
|
Timing_Error <= 1'b0;
|
1689 |
|
|
end
|
1690 |
28 |
bbeaver |
end
|
1691 |
|
|
end
|
1692 |
29 |
bbeaver |
else // was to a different bank. We are done
|
1693 |
28 |
bbeaver |
begin
|
1694 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1695 |
|
|
begin
|
1696 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1697 |
|
|
end
|
1698 |
|
|
else
|
1699 |
|
|
begin
|
1700 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= ACTIVATING;
|
1701 |
|
|
end
|
1702 |
|
|
end
|
1703 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1704 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1705 |
|
|
end
|
1706 |
26 |
bbeaver |
else
|
1707 |
|
|
begin
|
1708 |
28 |
bbeaver |
$display ("*** %m DDR DRAM can only do Read, Write, or Precharge from Read %t", $time);
|
1709 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING;
|
1710 |
27 |
bbeaver |
Timing_Error <= 1'b1;
|
1711 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1712 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1713 |
26 |
bbeaver |
end
|
1714 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= (load_mode_delay_counter[3:0] != 4'h0)
|
1715 |
|
|
? (load_mode_delay_counter[3:0] - 4'h1) : 4'h0;
|
1716 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1717 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1718 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1719 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1720 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1721 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1722 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1723 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1724 |
29 |
bbeaver |
read_to_write_counter [3:0] <= READ_TO_WRITE_CYCLES;
|
1725 |
|
|
write_to_read_counter [3:0] <= (write_to_read_counter[3:0] != 4'h0)
|
1726 |
|
|
? (write_to_read_counter[3:0] - 4'h1) : 4'h0;
|
1727 |
|
|
write_recovery_counter[3:0] <= (write_recovery_counter[3:0] != 4'h0)
|
1728 |
27 |
bbeaver |
? (write_recovery_counter[3:0] - 4'h1) : 4'h0;
|
1729 |
|
|
precharge_counter[3:0] <= PRECHARGE_CYCLES;
|
1730 |
29 |
bbeaver |
refresh_counter[3:0] <= 4'h0;
|
1731 |
26 |
bbeaver |
end
|
1732 |
27 |
bbeaver |
|
1733 |
28 |
bbeaver |
READING_PRECHARGE:
|
1734 |
26 |
bbeaver |
begin
|
1735 |
29 |
bbeaver |
if ( (control_wires[4] == 1'b0) // powered off
|
1736 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
1737 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
1738 |
|
|
begin
|
1739 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1740 |
|
|
begin
|
1741 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1742 |
|
|
Timing_Error <= 1'b0;
|
1743 |
|
|
end
|
1744 |
|
|
else
|
1745 |
|
|
begin
|
1746 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1747 |
|
|
Timing_Error <= 1'b0;
|
1748 |
|
|
end
|
1749 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1750 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1751 |
|
|
end
|
1752 |
|
|
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
1753 |
|
|
begin
|
1754 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1755 |
|
|
begin
|
1756 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is being Read %t", $time);
|
1757 |
|
|
Timing_Error <= 1'b1;
|
1758 |
|
|
end
|
1759 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1760 |
|
|
begin
|
1761 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1762 |
|
|
end
|
1763 |
|
|
else
|
1764 |
|
|
begin
|
1765 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1766 |
|
|
end
|
1767 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1768 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1769 |
|
|
end
|
1770 |
|
|
else if (control_wires[4:0] == READ_BANK)
|
1771 |
|
|
begin
|
1772 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1773 |
|
|
begin
|
1774 |
|
|
$display ("*** %m DDR DRAM cannot do a Read until Read_precharge completes precharge %t", $time);
|
1775 |
|
|
Timing_Error <= 1'b1;
|
1776 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1777 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1778 |
|
|
end
|
1779 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1780 |
|
|
begin
|
1781 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1782 |
|
|
end
|
1783 |
|
|
else
|
1784 |
|
|
begin
|
1785 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1786 |
|
|
end
|
1787 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1788 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1789 |
|
|
end
|
1790 |
|
|
else if (control_wires[4:0] == WRITE_BANK)
|
1791 |
|
|
begin
|
1792 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1793 |
|
|
begin
|
1794 |
|
|
$display ("*** %m DDR DRAM cannot do a Write until Read_precharge completes precharge %t", $time);
|
1795 |
|
|
Timing_Error <= 1'b1;
|
1796 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1797 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1798 |
|
|
end
|
1799 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1800 |
|
|
begin
|
1801 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1802 |
|
|
end
|
1803 |
|
|
else
|
1804 |
|
|
begin
|
1805 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1806 |
|
|
end
|
1807 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1808 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1809 |
|
|
end
|
1810 |
|
|
else if (control_wires[4:0] == PRECHARGE_BANK) // do idles when it is safe to do so
|
1811 |
|
|
begin
|
1812 |
|
|
if ((BA[1:0] == bank_num[1:0]) | (A[10] == 1'b1))
|
1813 |
|
|
begin
|
1814 |
|
|
$display ("*** %m DDR DRAM cannot do a Precharge until Read_precharge completes plus recovery %t", $time);
|
1815 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1816 |
|
|
Timing_Error <= 1'b1;
|
1817 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1818 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1819 |
|
|
end
|
1820 |
|
|
else // was to a different bank. We are done
|
1821 |
|
|
begin
|
1822 |
|
|
if (burst_counter[3:0] > 4'h1)
|
1823 |
|
|
begin
|
1824 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1825 |
|
|
end
|
1826 |
|
|
else
|
1827 |
|
|
begin
|
1828 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1829 |
|
|
end
|
1830 |
|
|
end
|
1831 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1832 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1833 |
|
|
end
|
1834 |
|
|
else
|
1835 |
|
|
begin
|
1836 |
|
|
$display ("*** %m DDR DRAM can only do Read, Write, or Precharge from Read %t", $time);
|
1837 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= READING_PRECHARGE;
|
1838 |
|
|
Timing_Error <= 1'b1;
|
1839 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1840 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1841 |
|
|
end
|
1842 |
|
|
load_mode_delay_counter[3:0] <= (load_mode_delay_counter[3:0] != 4'h0)
|
1843 |
|
|
? (load_mode_delay_counter[3:0] - 4'h1) : 4'h0;
|
1844 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1845 |
|
|
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1846 |
|
|
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1847 |
|
|
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1848 |
|
|
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1849 |
|
|
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1850 |
|
|
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1851 |
|
|
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1852 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1853 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1854 |
|
|
read_to_write_counter [3:0] <= READ_TO_WRITE_CYCLES;
|
1855 |
|
|
write_to_read_counter [3:0] <= (write_to_read_counter[3:0] != 4'h0)
|
1856 |
|
|
? (write_to_read_counter[3:0] - 4'h1) : 4'h0;
|
1857 |
|
|
write_recovery_counter[3:0] <= (write_recovery_counter[3:0] != 4'h0)
|
1858 |
|
|
? (write_recovery_counter[3:0] - 4'h1) : 4'h0;
|
1859 |
|
|
precharge_counter[3:0] <= PRECHARGE_CYCLES;
|
1860 |
|
|
refresh_counter[3:0] <= 4'h0;
|
1861 |
26 |
bbeaver |
end
|
1862 |
27 |
bbeaver |
|
1863 |
29 |
bbeaver |
WAITING_FOR_AUTO_PRECHARGE:
|
1864 |
|
|
begin
|
1865 |
|
|
if ( (control_wires[4] == 1'b0) // powered off
|
1866 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
1867 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
1868 |
|
|
begin
|
1869 |
|
|
if ( (write_recovery_counter[3:0] > 4'h1)
|
1870 |
|
|
| (act_to_precharge_counter[3:0] > 4'h1) )
|
1871 |
|
|
begin
|
1872 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1873 |
|
|
Timing_Error <= 1'b0;
|
1874 |
|
|
end
|
1875 |
|
|
else
|
1876 |
|
|
begin
|
1877 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1878 |
|
|
Timing_Error <= 1'b0;
|
1879 |
|
|
end
|
1880 |
|
|
end
|
1881 |
|
|
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
1882 |
|
|
begin
|
1883 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1884 |
|
|
begin
|
1885 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is being auto_precharging %t", $time);
|
1886 |
|
|
Timing_Error <= 1'b1;
|
1887 |
|
|
end
|
1888 |
|
|
if ( (write_recovery_counter[3:0] > 4'h1)
|
1889 |
|
|
| (act_to_precharge_counter[3:0] > 4'h1) )
|
1890 |
|
|
begin
|
1891 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1892 |
|
|
Timing_Error <= 1'b0;
|
1893 |
|
|
end
|
1894 |
|
|
else
|
1895 |
|
|
begin
|
1896 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1897 |
|
|
Timing_Error <= 1'b0;
|
1898 |
|
|
end
|
1899 |
|
|
end
|
1900 |
|
|
else if (control_wires[4:0] == READ_BANK)
|
1901 |
|
|
begin
|
1902 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1903 |
|
|
begin
|
1904 |
|
|
$display ("*** %m DDR DRAM cannot do a Read until bank completes precharge %t", $time);
|
1905 |
|
|
Timing_Error <= 1'b1;
|
1906 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1907 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1908 |
|
|
end
|
1909 |
|
|
if ( (write_recovery_counter[3:0] > 4'h1)
|
1910 |
|
|
| (act_to_precharge_counter[3:0] > 4'h1) )
|
1911 |
|
|
begin
|
1912 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1913 |
|
|
Timing_Error <= 1'b0;
|
1914 |
|
|
end
|
1915 |
|
|
else
|
1916 |
|
|
begin
|
1917 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1918 |
|
|
Timing_Error <= 1'b0;
|
1919 |
|
|
end
|
1920 |
|
|
end
|
1921 |
|
|
else if (control_wires[4:0] == WRITE_BANK)
|
1922 |
|
|
begin
|
1923 |
|
|
if (BA[1:0] == bank_num[1:0])
|
1924 |
|
|
begin
|
1925 |
|
|
$display ("*** %m DDR DRAM cannot do a Write until bank completes precharge %t", $time);
|
1926 |
|
|
Timing_Error <= 1'b1;
|
1927 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1928 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1929 |
|
|
end
|
1930 |
|
|
if ( (write_recovery_counter[3:0] > 4'h1)
|
1931 |
|
|
| (act_to_precharge_counter[3:0] > 4'h1) )
|
1932 |
|
|
begin
|
1933 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1934 |
|
|
Timing_Error <= 1'b0;
|
1935 |
|
|
end
|
1936 |
|
|
else
|
1937 |
|
|
begin
|
1938 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1939 |
|
|
Timing_Error <= 1'b0;
|
1940 |
|
|
end
|
1941 |
|
|
end
|
1942 |
|
|
else if (control_wires[4:0] == PRECHARGE_BANK) // do idles when it is safe to do so
|
1943 |
|
|
begin
|
1944 |
|
|
if ( (write_recovery_counter[3:0] > 4'h1)
|
1945 |
|
|
| (act_to_precharge_counter[3:0] > 4'h1) )
|
1946 |
|
|
begin
|
1947 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1948 |
|
|
Timing_Error <= 1'b0;
|
1949 |
|
|
end
|
1950 |
|
|
else
|
1951 |
|
|
begin
|
1952 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1953 |
|
|
Timing_Error <= 1'b0;
|
1954 |
|
|
end
|
1955 |
|
|
end
|
1956 |
|
|
else
|
1957 |
|
|
begin
|
1958 |
|
|
$display ("*** %m DDR DRAM can only wait from Write_precharge %t", $time);
|
1959 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= WAITING_FOR_AUTO_PRECHARGE;
|
1960 |
|
|
Timing_Error <= 1'b1;
|
1961 |
|
|
end
|
1962 |
|
|
load_mode_delay_counter[3:0] <= 4'h0;
|
1963 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
1964 |
|
|
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
1965 |
|
|
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
1966 |
|
|
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
1967 |
|
|
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
1968 |
|
|
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
1969 |
|
|
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
1970 |
|
|
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
1971 |
|
|
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
1972 |
|
|
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
1973 |
|
|
read_to_write_counter [3:0] <= (read_to_write_counter[3:0] != 4'h0)
|
1974 |
|
|
? (read_to_write_counter[3:0] - 4'h1) : 4'h0;
|
1975 |
|
|
write_to_read_counter [3:0] <= (write_to_read_counter[3:0] != 4'h0)
|
1976 |
|
|
? (write_to_read_counter[3:0] - 4'h1) : 4'h0;
|
1977 |
|
|
write_recovery_counter[3:0] <= (write_recovery_counter[3:0] != 4'h0)
|
1978 |
|
|
? (write_recovery_counter[3:0] - 4'h1) : 4'h0;
|
1979 |
|
|
precharge_counter[3:0] <= PRECHARGE_CYCLES;
|
1980 |
|
|
refresh_counter[3:0] <= 4'h0;
|
1981 |
|
|
end
|
1982 |
|
|
|
1983 |
28 |
bbeaver |
PRECHARGING:
|
1984 |
26 |
bbeaver |
begin
|
1985 |
28 |
bbeaver |
if ( (control_wires[4] == 1'b0) // powered off
|
1986 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
1987 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
1988 |
|
|
begin
|
1989 |
29 |
bbeaver |
if (precharge_counter[3:0] > 4'h2) // looping
|
1990 |
28 |
bbeaver |
begin
|
1991 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
1992 |
|
|
Timing_Error <= 1'b0;
|
1993 |
|
|
end
|
1994 |
|
|
else
|
1995 |
|
|
begin
|
1996 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
1997 |
|
|
Timing_Error <= 1'b0;
|
1998 |
|
|
end
|
1999 |
|
|
end
|
2000 |
|
|
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
2001 |
|
|
begin
|
2002 |
|
|
if (BA[1:0] == bank_num[1:0])
|
2003 |
|
|
begin
|
2004 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is being Precharged %t", $time);
|
2005 |
|
|
Timing_Error <= 1'b1;
|
2006 |
|
|
end
|
2007 |
|
|
else
|
2008 |
|
|
begin
|
2009 |
|
|
Timing_Error <= 1'b0;
|
2010 |
|
|
end
|
2011 |
29 |
bbeaver |
if (precharge_counter[3:0] > 4'h2) // looping
|
2012 |
28 |
bbeaver |
begin
|
2013 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
2014 |
|
|
end
|
2015 |
|
|
else
|
2016 |
|
|
begin
|
2017 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2018 |
|
|
end
|
2019 |
|
|
end
|
2020 |
|
|
else if (control_wires[4:0] == READ_BANK) // no bank involved
|
2021 |
|
|
begin
|
2022 |
|
|
if (BA[1:0] == bank_num[1:0])
|
2023 |
|
|
begin
|
2024 |
|
|
$display ("*** %m DDR DRAM cannot do an Read to a bank which is being Precharged %t", $time);
|
2025 |
|
|
Timing_Error <= 1'b1;
|
2026 |
|
|
end
|
2027 |
|
|
else
|
2028 |
|
|
begin
|
2029 |
|
|
Timing_Error <= 1'b0;
|
2030 |
|
|
end
|
2031 |
29 |
bbeaver |
if (precharge_counter[3:0] > 4'h2) // looping
|
2032 |
28 |
bbeaver |
begin
|
2033 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
2034 |
|
|
end
|
2035 |
|
|
else
|
2036 |
|
|
begin
|
2037 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2038 |
|
|
end
|
2039 |
|
|
end
|
2040 |
|
|
else if (control_wires[4:0] == WRITE_BANK) // no bank involved
|
2041 |
|
|
begin
|
2042 |
|
|
if (BA[1:0] == bank_num[1:0])
|
2043 |
|
|
begin
|
2044 |
|
|
$display ("*** %m DDR DRAM cannot do an Write to a bank which is being Precharged %t", $time);
|
2045 |
|
|
Timing_Error <= 1'b1;
|
2046 |
|
|
end
|
2047 |
|
|
else
|
2048 |
|
|
begin
|
2049 |
|
|
Timing_Error <= 1'b0;
|
2050 |
|
|
end
|
2051 |
29 |
bbeaver |
if (precharge_counter[3:0] > 4'h2) // looping
|
2052 |
28 |
bbeaver |
begin
|
2053 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
2054 |
|
|
end
|
2055 |
|
|
else
|
2056 |
|
|
begin
|
2057 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2058 |
|
|
end
|
2059 |
|
|
end
|
2060 |
|
|
else if (control_wires[4:0] == PRECHARGE_BANK) // ignore extra precharges
|
2061 |
|
|
begin
|
2062 |
|
|
Timing_Error <= 1'b0;
|
2063 |
29 |
bbeaver |
if (precharge_counter[3:0] > 4'h2) // looping
|
2064 |
28 |
bbeaver |
begin
|
2065 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
2066 |
|
|
end
|
2067 |
|
|
else
|
2068 |
|
|
begin
|
2069 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2070 |
|
|
end
|
2071 |
|
|
end
|
2072 |
|
|
else
|
2073 |
|
|
begin
|
2074 |
|
|
$display ("*** %m DDR DRAM can't do anything from Precharge %t", $time);
|
2075 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= PRECHARGING;
|
2076 |
|
|
Timing_Error <= 1'b1;
|
2077 |
|
|
end
|
2078 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= (load_mode_delay_counter[3:0] != 4'h0)
|
2079 |
|
|
? (load_mode_delay_counter[3:0] - 4'h1) : 4'h0;
|
2080 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
2081 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
2082 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
2083 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
2084 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
2085 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
2086 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
2087 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
2088 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
2089 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
2090 |
29 |
bbeaver |
read_to_write_counter [3:0] <= (read_to_write_counter[3:0] != 4'h0)
|
2091 |
|
|
? (read_to_write_counter[3:0] - 4'h1) : 4'h0;
|
2092 |
|
|
write_to_read_counter [3:0] <= (write_to_read_counter[3:0] != 4'h0)
|
2093 |
|
|
? (write_to_read_counter[3:0] - 4'h1) : 4'h0;
|
2094 |
|
|
write_recovery_counter[3:0] <= (write_recovery_counter[3:0] != 4'h0)
|
2095 |
28 |
bbeaver |
? (write_recovery_counter[3:0] - 4'h1) : 4'h0;
|
2096 |
29 |
bbeaver |
precharge_counter[3:0] <= (precharge_counter[3:0] != 4'h0)
|
2097 |
28 |
bbeaver |
? (precharge_counter[3:0] - 4'h1) : 4'h0;
|
2098 |
29 |
bbeaver |
refresh_counter[3:0] <= (refresh_counter[3:0] != 4'h0)
|
2099 |
28 |
bbeaver |
? (refresh_counter[3:0] - 4'h1) : 4'h0;
|
2100 |
26 |
bbeaver |
end
|
2101 |
27 |
bbeaver |
|
2102 |
|
|
REFRESHING:
|
2103 |
28 |
bbeaver |
begin
|
2104 |
|
|
if ( (control_wires[4] == 1'b0) // powered off
|
2105 |
|
|
| (control_wires[3] == 1'b1) // not selected
|
2106 |
|
|
| (control_wires[4:0] == NOOP) ) // noop
|
2107 |
|
|
begin
|
2108 |
29 |
bbeaver |
if (refresh_counter[3:0] > 4'h2) // looping
|
2109 |
28 |
bbeaver |
begin
|
2110 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= REFRESHING;
|
2111 |
|
|
Timing_Error <= 1'b0;
|
2112 |
|
|
end
|
2113 |
|
|
else
|
2114 |
|
|
begin
|
2115 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2116 |
|
|
Timing_Error <= 1'b0;
|
2117 |
|
|
end
|
2118 |
|
|
end
|
2119 |
|
|
else if (control_wires[4:0] == ACTIVATE_BANK) // activate only if this bank is addressed
|
2120 |
|
|
begin
|
2121 |
|
|
if (BA[1:0] == bank_num[1:0])
|
2122 |
|
|
begin
|
2123 |
|
|
$display ("*** %m DDR DRAM cannot do an Activate to a bank which is being Refreshed %t", $time);
|
2124 |
|
|
Timing_Error <= 1'b1;
|
2125 |
|
|
end
|
2126 |
|
|
else
|
2127 |
|
|
begin
|
2128 |
|
|
Timing_Error <= 1'b0;
|
2129 |
|
|
end
|
2130 |
29 |
bbeaver |
if (refresh_counter[3:0] > 4'h2) // looping
|
2131 |
28 |
bbeaver |
begin
|
2132 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= REFRESHING;
|
2133 |
|
|
end
|
2134 |
|
|
else
|
2135 |
|
|
begin
|
2136 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2137 |
|
|
end
|
2138 |
|
|
end
|
2139 |
|
|
else if (control_wires[4:0] == READ_BANK) // no bank involved
|
2140 |
|
|
begin
|
2141 |
|
|
if (BA[1:0] == bank_num[1:0])
|
2142 |
|
|
begin
|
2143 |
|
|
$display ("*** %m DDR DRAM cannot do an Read to a bank which is being Refreshed %t", $time);
|
2144 |
|
|
Timing_Error <= 1'b1;
|
2145 |
|
|
end
|
2146 |
|
|
else
|
2147 |
|
|
begin
|
2148 |
|
|
Timing_Error <= 1'b0;
|
2149 |
|
|
end
|
2150 |
29 |
bbeaver |
if (refresh_counter[3:0] > 4'h2) // looping
|
2151 |
28 |
bbeaver |
begin
|
2152 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= REFRESHING;
|
2153 |
|
|
end
|
2154 |
|
|
else
|
2155 |
|
|
begin
|
2156 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2157 |
|
|
end
|
2158 |
|
|
end
|
2159 |
|
|
else if (control_wires[4:0] == WRITE_BANK) // no bank involved
|
2160 |
|
|
begin
|
2161 |
|
|
if (BA[1:0] == bank_num[1:0])
|
2162 |
|
|
begin
|
2163 |
|
|
$display ("*** %m DDR DRAM cannot do an Write to a bank which is being Refreshed %t", $time);
|
2164 |
|
|
Timing_Error <= 1'b1;
|
2165 |
|
|
end
|
2166 |
|
|
else
|
2167 |
|
|
begin
|
2168 |
|
|
Timing_Error <= 1'b0;
|
2169 |
|
|
end
|
2170 |
29 |
bbeaver |
if (refresh_counter[3:0] > 4'h2) // looping
|
2171 |
28 |
bbeaver |
begin
|
2172 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= REFRESHING;
|
2173 |
|
|
end
|
2174 |
|
|
else
|
2175 |
|
|
begin
|
2176 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2177 |
|
|
end
|
2178 |
|
|
end
|
2179 |
|
|
else if (control_wires[4:0] == PRECHARGE_BANK) // ignore extra precharges
|
2180 |
|
|
begin
|
2181 |
|
|
Timing_Error <= 1'b0;
|
2182 |
29 |
bbeaver |
if (refresh_counter[3:0] > 4'h2) // looping
|
2183 |
28 |
bbeaver |
begin
|
2184 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= REFRESHING;
|
2185 |
|
|
end
|
2186 |
|
|
else
|
2187 |
|
|
begin
|
2188 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2189 |
|
|
end
|
2190 |
|
|
end
|
2191 |
|
|
else
|
2192 |
|
|
begin
|
2193 |
|
|
$display ("*** %m DDR DRAM can't do anything from Refresh %t", $time);
|
2194 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= REFRESHING;
|
2195 |
|
|
Timing_Error <= 1'b1;
|
2196 |
|
|
end
|
2197 |
29 |
bbeaver |
load_mode_delay_counter[3:0] <= (load_mode_delay_counter[3:0] != 4'h0)
|
2198 |
|
|
? (load_mode_delay_counter[3:0] - 4'h1) : 4'h0;
|
2199 |
|
|
act_a_to_act_b_counter[3:0] <= (act_a_to_act_b_counter[3:0] != 4'h0)
|
2200 |
28 |
bbeaver |
? (act_a_to_act_b_counter[3:0] - 4'h1) : 4'h0;
|
2201 |
29 |
bbeaver |
act_to_read_or_write_counter[3:0] <= (act_to_read_or_write_counter[3:0] != 4'h0)
|
2202 |
28 |
bbeaver |
? (act_to_read_or_write_counter[3:0] - 4'h1) : 4'h0;
|
2203 |
29 |
bbeaver |
act_to_precharge_counter[3:0] <= (act_to_precharge_counter[3:0] != 4'h0)
|
2204 |
28 |
bbeaver |
? (act_to_precharge_counter[3:0] - 4'h1) : 4'h0;
|
2205 |
29 |
bbeaver |
act_a_to_act_a_counter[3:0] <= (act_a_to_act_a_counter[3:0] != 4'h0)
|
2206 |
28 |
bbeaver |
? (act_a_to_act_a_counter[3:0] - 4'h1) : 4'h0;
|
2207 |
29 |
bbeaver |
burst_counter[3:0] <= (burst_counter[3:0] != 4'h0)
|
2208 |
28 |
bbeaver |
? (burst_counter[3:0] - 4'h1) : 4'h0;
|
2209 |
29 |
bbeaver |
write_recovery_counter[3:0] <= (write_recovery_counter[3:0] != 4'h0)
|
2210 |
28 |
bbeaver |
? (write_recovery_counter[3:0] - 4'h1) : 4'h0;
|
2211 |
29 |
bbeaver |
precharge_counter[3:0] <= (precharge_counter[3:0] != 4'h0)
|
2212 |
|
|
? (precharge_counter[3:0] - 4'h1) : 4'h0;
|
2213 |
|
|
refresh_counter[3:0] <= (refresh_counter[3:0] != 4'h0)
|
2214 |
28 |
bbeaver |
? (refresh_counter[3:0] - 4'h1) : 4'h0;
|
2215 |
29 |
bbeaver |
end
|
2216 |
|
|
|
2217 |
26 |
bbeaver |
default:
|
2218 |
|
|
begin
|
2219 |
27 |
bbeaver |
$display ("*** %m DDR DRAM default jump should be impossible %t", $time);
|
2220 |
|
|
bank_state[BANK_STATE_WIDTH - 1 : 0] <= BANK_IDLE;
|
2221 |
|
|
Timing_Error <= 1'b1;
|
2222 |
26 |
bbeaver |
end
|
2223 |
|
|
endcase
|
2224 |
32 |
bbeaver |
end // if out the entire case statement!
|
2225 |
26 |
bbeaver |
end
|
2226 |
25 |
bbeaver |
endmodule
|
2227 |
|
|
|
2228 |
|
|
`define TEST_DDR_2_DRAM
|
2229 |
|
|
`ifdef TEST_DDR_2_DRAM
|
2230 |
|
|
module test_ddr_2_dram;
|
2231 |
|
|
reg CLK_P, CLK_N;
|
2232 |
|
|
|
2233 |
|
|
initial
|
2234 |
|
|
begin
|
2235 |
|
|
CLK_P <= 1'b0;
|
2236 |
|
|
CLK_N <= 1'b1;
|
2237 |
26 |
bbeaver |
# 10_000 ; // make times be even
|
2238 |
25 |
bbeaver |
while (1'b1)
|
2239 |
|
|
begin
|
2240 |
26 |
bbeaver |
#10_000 ; // 10 nSec
|
2241 |
25 |
bbeaver |
CLK_P <= ~CLK_P;
|
2242 |
|
|
CLK_N <= ~CLK_N;
|
2243 |
|
|
end
|
2244 |
|
|
end
|
2245 |
|
|
|
2246 |
|
|
initial
|
2247 |
|
|
begin
|
2248 |
29 |
bbeaver |
#2000_000 $finish;
|
2249 |
25 |
bbeaver |
end
|
2250 |
|
|
|
2251 |
26 |
bbeaver |
// hook up sequential test bench to instantiation of DDR DRAM for test
|
2252 |
|
|
parameter DATA_BUS_WIDTH = 4;
|
2253 |
|
|
|
2254 |
|
|
wire [DATA_BUS_WIDTH - 1 : 0] DQ;
|
2255 |
25 |
bbeaver |
wire DQS;
|
2256 |
32 |
bbeaver |
|
2257 |
25 |
bbeaver |
reg DM;
|
2258 |
|
|
reg [12:0] A;
|
2259 |
|
|
reg [1:0] BA;
|
2260 |
|
|
reg RAS_L, CAS_L, WE_L, CS_L, CKE;
|
2261 |
26 |
bbeaver |
reg [DATA_BUS_WIDTH - 1 : 0] DQ_out_0;
|
2262 |
|
|
reg [DATA_BUS_WIDTH - 1 : 0] DQ_out_1;
|
2263 |
32 |
bbeaver |
reg DQ_oe_0, DQ_oe_1;
|
2264 |
26 |
bbeaver |
reg DQS_out;
|
2265 |
|
|
reg DQS_oe;
|
2266 |
25 |
bbeaver |
|
2267 |
26 |
bbeaver |
// MUX the two data items together based on clock phase
|
2268 |
|
|
wire [DATA_BUS_WIDTH - 1 : 0] DQ_out = CLK_P
|
2269 |
|
|
? DQ_out_1[DATA_BUS_WIDTH - 1 : 0]
|
2270 |
|
|
: DQ_out_0[DATA_BUS_WIDTH - 1 : 0];
|
2271 |
|
|
|
2272 |
|
|
// Either send data or tristate the bus
|
2273 |
|
|
assign DQ[DATA_BUS_WIDTH - 1 : 0] = DQ_oe
|
2274 |
|
|
? DQ_out[DATA_BUS_WIDTH - 1 : 0]
|
2275 |
|
|
: {DATA_BUS_WIDTH{1'bZ}};
|
2276 |
|
|
|
2277 |
|
|
// The DQS signal is OE'd BEFORE the Data. Called the preamble.
|
2278 |
|
|
assign DQS = DQS_oe ? DQS_out : 1'bZ;
|
2279 |
|
|
|
2280 |
|
|
// {CKE, CS_L, RAS_L, CAS_L, WE_L}
|
2281 |
|
|
parameter NOOP = 5'h17;
|
2282 |
|
|
parameter ACTIVATE = 5'h13;
|
2283 |
|
|
parameter READ = 5'h15;
|
2284 |
|
|
parameter WRITE = 5'h14;
|
2285 |
|
|
parameter PRECHARGE = 5'h12;
|
2286 |
|
|
parameter REFRESH = 5'h11;
|
2287 |
|
|
parameter LOAD_MODE = 5'h10;
|
2288 |
|
|
|
2289 |
|
|
initial
|
2290 |
|
|
begin
|
2291 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'hZ;
|
2292 |
|
|
DQ_oe_0 <= 1'b0;
|
2293 |
|
|
DQ_out_1[DATA_BUS_WIDTH - 1 : 0] <= 4'hZ;
|
2294 |
|
|
DQ_oe_1 <= 1'b0;
|
2295 |
|
|
|
2296 |
26 |
bbeaver |
CKE <= 1'b1;
|
2297 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2298 |
|
|
DQ_oe <= 1'b0; DQS_oe <= 1'b0;
|
2299 |
|
|
@ (posedge CLK_P) ; // noop
|
2300 |
|
|
|
2301 |
29 |
bbeaver |
A[12:0] <= 13'h1555; BA[1:0] <= 2'h0;
|
2302 |
26 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= LOAD_MODE;
|
2303 |
|
|
@ (posedge CLK_P) ; // write reg
|
2304 |
|
|
|
2305 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2306 |
|
|
@ (posedge CLK_P) ; // noop
|
2307 |
|
|
|
2308 |
29 |
bbeaver |
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2309 |
26 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= ACTIVATE;
|
2310 |
|
|
@ (posedge CLK_P) ; // activate
|
2311 |
|
|
|
2312 |
29 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2313 |
|
|
@ (posedge CLK_P) ; // noop
|
2314 |
26 |
bbeaver |
|
2315 |
29 |
bbeaver |
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2316 |
26 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= WRITE;
|
2317 |
29 |
bbeaver |
@ (posedge CLK_P) ; // write DRAM
|
2318 |
26 |
bbeaver |
|
2319 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'h1;
|
2320 |
|
|
DQ_out_1[DATA_BUS_WIDTH - 1 : 0] <= 4'hZ;
|
2321 |
|
|
|
2322 |
26 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2323 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2324 |
|
|
|
2325 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'h2;
|
2326 |
|
|
DQ_out_1[DATA_BUS_WIDTH - 1 : 0] <= 4'hE;
|
2327 |
|
|
|
2328 |
29 |
bbeaver |
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2329 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= WRITE;
|
2330 |
|
|
@ (posedge CLK_P) ; // write DRAM
|
2331 |
|
|
|
2332 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'h3;
|
2333 |
|
|
DQ_out_1[DATA_BUS_WIDTH - 1 : 0] <= 4'hD;
|
2334 |
|
|
|
2335 |
26 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2336 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2337 |
|
|
|
2338 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'h4;
|
2339 |
|
|
DQ_out_1[DATA_BUS_WIDTH - 1 : 0] <= 4'hC;
|
2340 |
|
|
|
2341 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2342 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2343 |
|
|
|
2344 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'hZ;
|
2345 |
|
|
DQ_out_1[DATA_BUS_WIDTH - 1 : 0] <= 4'hB;
|
2346 |
|
|
|
2347 |
29 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2348 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2349 |
|
|
|
2350 |
32 |
bbeaver |
DQ_out_1[DATA_BUS_WIDTH - 1 : 0] <= 4'hZ;
|
2351 |
|
|
|
2352 |
29 |
bbeaver |
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2353 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= READ;
|
2354 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2355 |
|
|
|
2356 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2357 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2358 |
|
|
|
2359 |
|
|
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2360 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= READ;
|
2361 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2362 |
|
|
|
2363 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2364 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2365 |
|
|
|
2366 |
|
|
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2367 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= PRECHARGE;
|
2368 |
29 |
bbeaver |
@ (posedge CLK_P) ; // noop
|
2369 |
|
|
|
2370 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2371 |
28 |
bbeaver |
@ (posedge CLK_P) ; // noop + data
|
2372 |
|
|
|
2373 |
29 |
bbeaver |
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2374 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= ACTIVATE;
|
2375 |
|
|
@ (posedge CLK_P) ; // activate
|
2376 |
|
|
|
2377 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2378 |
29 |
bbeaver |
@ (posedge CLK_P) ; // noop
|
2379 |
|
|
|
2380 |
|
|
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2381 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= READ;
|
2382 |
|
|
@ (posedge CLK_P) ; // read
|
2383 |
|
|
|
2384 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2385 |
28 |
bbeaver |
@ (posedge CLK_P) ; // noop + data
|
2386 |
|
|
|
2387 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2388 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2389 |
|
|
|
2390 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2391 |
29 |
bbeaver |
@ (posedge CLK_P) ; // noop + data //
|
2392 |
|
|
|
2393 |
|
|
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2394 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= WRITE;
|
2395 |
|
|
@ (posedge CLK_P) ; // write
|
2396 |
|
|
|
2397 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'hE;
|
2398 |
29 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2399 |
28 |
bbeaver |
@ (posedge CLK_P) ; // noop + data
|
2400 |
|
|
|
2401 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'hD;
|
2402 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2403 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2404 |
|
|
|
2405 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'hZ;
|
2406 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2407 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2408 |
|
|
|
2409 |
29 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2410 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2411 |
|
|
|
2412 |
|
|
|
2413 |
|
|
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2414 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= PRECHARGE;
|
2415 |
|
|
@ (posedge CLK_P) ; // noop
|
2416 |
|
|
|
2417 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2418 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2419 |
|
|
|
2420 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= REFRESH;
|
2421 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2422 |
|
|
|
2423 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2424 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2425 |
|
|
|
2426 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2427 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2428 |
|
|
|
2429 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2430 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2431 |
|
|
|
2432 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2433 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2434 |
|
|
|
2435 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2436 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2437 |
|
|
|
2438 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2439 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2440 |
|
|
|
2441 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2442 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2443 |
|
|
|
2444 |
29 |
bbeaver |
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2445 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= ACTIVATE;
|
2446 |
|
|
@ (posedge CLK_P) ; // activate
|
2447 |
|
|
|
2448 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2449 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2450 |
|
|
|
2451 |
29 |
bbeaver |
A[12:0] <= 13'h400; BA[1:0] <= 2'h0;
|
2452 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= WRITE;
|
2453 |
|
|
@ (posedge CLK_P) ; // write
|
2454 |
|
|
|
2455 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'hB;
|
2456 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2457 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2458 |
|
|
|
2459 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'h7;
|
2460 |
29 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2461 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2462 |
|
|
|
2463 |
32 |
bbeaver |
DQ_out_0[DATA_BUS_WIDTH - 1 : 0] <= 4'hZ;
|
2464 |
29 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2465 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2466 |
|
|
|
2467 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2468 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2469 |
|
|
|
2470 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2471 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2472 |
|
|
|
2473 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2474 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2475 |
|
|
|
2476 |
|
|
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2477 |
28 |
bbeaver |
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= ACTIVATE;
|
2478 |
|
|
@ (posedge CLK_P) ; // activate
|
2479 |
|
|
|
2480 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2481 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2482 |
|
|
|
2483 |
29 |
bbeaver |
A[12:0] <= 13'h400; BA[1:0] <= 2'h0;
|
2484 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= READ;
|
2485 |
|
|
@ (posedge CLK_P) ; // write
|
2486 |
|
|
|
2487 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2488 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2489 |
|
|
|
2490 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2491 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2492 |
|
|
|
2493 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2494 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2495 |
|
|
|
2496 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2497 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2498 |
|
|
|
2499 |
|
|
A[12:0] <= 13'h0; BA[1:0] <= 2'h0;
|
2500 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= ACTIVATE;
|
2501 |
|
|
@ (posedge CLK_P) ; // activate
|
2502 |
|
|
|
2503 |
|
|
{CKE, CS_L, RAS_L, CAS_L, WE_L} <= NOOP;
|
2504 |
|
|
@ (posedge CLK_P) ; // noop + data
|
2505 |
|
|
|
2506 |
26 |
bbeaver |
end
|
2507 |
|
|
|
2508 |
32 |
bbeaver |
|
2509 |
|
|
|
2510 |
|
|
|
2511 |
|
|
assign DQ[DATA_BUS_WIDTH - 1 : 0] =
|
2512 |
|
|
( (DQ_out_0[DATA_BUS_WIDTH - 1 : 0] !== {DATA_BUS_WIDTH{1'bZ}})
|
2513 |
|
|
& (CLK_N == 1'b1) )
|
2514 |
|
|
? DQ_out_0[DATA_BUS_WIDTH - 1 : 0]
|
2515 |
|
|
: ( ( (DQ_out_1[DATA_BUS_WIDTH - 1 : 0] !== {DATA_BUS_WIDTH{1'bZ}})
|
2516 |
|
|
& (CLK_P == 1'b1) )
|
2517 |
|
|
? DQ_out_1[DATA_BUS_WIDTH - 1 : 0]
|
2518 |
|
|
: {DATA_BUS_WIDTH{1'bZ}});
|
2519 |
|
|
|
2520 |
25 |
bbeaver |
ddr_2_dram
|
2521 |
28 |
bbeaver |
# ( 100.0, // frequency
|
2522 |
26 |
bbeaver |
2.0, // latency
|
2523 |
|
|
13, // num_addr_bits
|
2524 |
32 |
bbeaver |
12, // num_col_bits
|
2525 |
|
|
4 * DATA_BUS_WIDTH, // num_data_bits
|
2526 |
|
|
32, // num_words_in_test_memory
|
2527 |
|
|
1
|
2528 |
25 |
bbeaver |
) ddr_2_dram (
|
2529 |
32 |
bbeaver |
.DQ ({DQ[DATA_BUS_WIDTH - 1 : 0], DQ[DATA_BUS_WIDTH - 1 : 0],
|
2530 |
|
|
DQ[DATA_BUS_WIDTH - 1 : 0], DQ[DATA_BUS_WIDTH - 1 : 0]}),
|
2531 |
25 |
bbeaver |
.DQS (DQS),
|
2532 |
|
|
.DM (DM),
|
2533 |
|
|
.A (A[12:0]),
|
2534 |
|
|
.BA (BA[1:0]),
|
2535 |
|
|
.RAS_L (RAS_L),
|
2536 |
|
|
.CAS_L (CAS_L),
|
2537 |
|
|
.WE_L (WE_L),
|
2538 |
|
|
.CS_L (CS_L),
|
2539 |
|
|
.CKE (CKE),
|
2540 |
|
|
.CLK_P (CLK_P),
|
2541 |
|
|
.CLK_N (CLK_N)
|
2542 |
|
|
);
|
2543 |
|
|
|
2544 |
27 |
bbeaver |
wire [3:0] BANK_STATE_0 = ddr_2_dram.ddr_2_dram_single_bank_0.bank_state[3:0];
|
2545 |
|
|
wire [3:0] BANK_STATE_1 = ddr_2_dram.ddr_2_dram_single_bank_1.bank_state[3:0];
|
2546 |
|
|
wire [3:0] BANK_STATE_2 = ddr_2_dram.ddr_2_dram_single_bank_2.bank_state[3:0];
|
2547 |
|
|
wire [3:0] BANK_STATE_3 = ddr_2_dram.ddr_2_dram_single_bank_3.bank_state[3:0];
|
2548 |
26 |
bbeaver |
|
2549 |
25 |
bbeaver |
endmodule
|
2550 |
|
|
`endif // TEST_DDR_2_DRAM
|