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//////////////////////////////////////////////////////////////////////
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//// ////
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//// plesiochronous_fifo #(N, N, N, N, N) ////
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//// ////
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//// This file is part of the general opencores effort. ////
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//// <http://www.opencores.org/cores/misc/> ////
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//// ////
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//// Module Description: ////
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//// An example of a plesiochronous FIFO between 2 clock domains ////
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//// ////
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//// To Do: ////
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//// nothing pending ////
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//// ////
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//// Author(s): ////
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//// - Anonymous ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Anonymous and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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bbeaver |
// $Id: plesiochronous_fifo.v,v 1.3 2001-09-03 13:26:38 bbeaver Exp $
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bbeaver |
//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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bbeaver |
// Revision 1.2 2001/09/03 13:31:00 Blue Beaver
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// no message
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//
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bbeaver |
// Revision 1.1 2001/09/03 12:51:43 Blue Beaver
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// no message
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//
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// Revision 1.5 2001/09/03 12:50:38 Blue Beaver
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// no message
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//
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//
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//////////////////////////////////////////////////////////////////////
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//
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// Web definition of Plesiochronous:
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// "Signals which are arbitrarily close in frequency to some defined precision.
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// They are not sourced from the same clock and so, over the long term, will
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// be skewed from each other. Their relative closeness of frequency allows a
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// switch to cross connect, switch, or in some way process them. That same
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// inaccuracy of timing will force a switch, over time, to repeat or delete
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// frames (called frame slips) in order to handle buffer underflow or overflow."
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//
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// Summary: Make a FIFO which is used to cross between 2 Pleasiochronous
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// clock domains.
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// This code assumes that latency does not matter.
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// This code assumes that the FIFO is being used for packet IO.
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// This code REQUIRES that the reader of the FIFO reads an entire
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// packet in back-to-back clocks, with no dead cycles.
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// This code REQUIRES that the writer of the FIFO leaves dead cycles
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bbeaver |
// between packets when writing the FIFO, so that it does not overflow.
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//
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// NOTE: This FIFO REQUIRES that the Sender ALWAYS sends a full packet into
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// the FIFO on adjacent Sender-side clocks. NO WAIT STATES except at
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// packet boundries. The Sender promises this to the Receiver.
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//
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// NOTE: This FIFO REQUIRES that the Receiver ALWAYS receives a full packet
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// out of the FIFO as soon as it gets an indication that the FIFO
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// is half full. NO WAIT STATES. The Receiver promises this to
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// the Sender.
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//
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// NOTE: The Read side has to capture the Read Data IMMEDIATELY. It must
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// wrap read_fifo_half_full back directly to read_consume, and must
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// capture and use the data it captures the first clock read_consume
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// is asserted. read_consume means data valid to the receiver logic.
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//
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// NOTE: A plesiochronous system is one in which the different clock domains
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// are running at different frequencies, but the designer knows how
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// far apart the system frequencies are worst case. The designer
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// can use this knowledge to make the system seem fully synchronous.
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//
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// NOTE: The system does NOT need to have the same frequencies for both the
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// reader and the writer, if the widths of the interfaces are different.
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// For instance, assume that the sender runs at N MHz with an M bit
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// interface. The receiver might run at N/2 MHz with a 2*M bit
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// interface.
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// As long as there are bounds on the variations of the sender's N MHz
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// clock and the receiver's N/2 MHz clock, the system can be
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// considered to be plesiochronous.
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//
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// NOTE: The idea: The Sender writes data into the FIFO. Every so often,
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// BUT ONLY AT A PACKET BOUNDRY, the sender intentionally does not
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// write to the FIFO for 1 clock.
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// The Receiver watches the FIFO. The receiver does not START reading
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// from the FIFO until the FIFO becomes half full. Once it starts
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// reading, it removes an entire packet from the FIFO all at once.
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// The Sender can be sure that it will not overrun the FIFO, because
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// it knows that the Receiver is emptying it. Even if the Sender is
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// filling faster than the Receiver is emptying, the bounded
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// difference in frequencies lets the Sender know that it cannot
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// fill up the FIFO before it skips a write.
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// The skipped write cycle keeps the Sender from over-filling the
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// FIFO in the long run.
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// The Receiver knows that it can receive an entire packet from the
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// FIFO without emptying it. Even if the Receiver is emptying the
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// FIFO faster than the Sender is filling it, the bounded
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// difference in frequencies lets the Receiver know that it cannot
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// empty the FIFO before it finishes reading a full packet.
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// As soon as the Receiver finishes reading a packet, it waits until
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// the FIFO gets at least half full again. The wait may be for
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// more than 1 clock. The waits until the FIFO is half full keeps
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// the Receiver from emptying the FIFO inthe ling run.
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//
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// NOTE: You have to tell the FIFO the paramaters of the clocks and packets
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// you are designing for. This lets the FIFO calculate whether it
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// can safely meet the design goals.
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//
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// NOTE: In this case, the FIFO is ALWAYS 6 elements deep. There are 6 entries
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// instead of 4 to handle cases I can't imagine involving clock jitter.
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//
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// NOTE: This module instantiates synchronizer_flop.v, available at
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// www.opencores.com/
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//
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// This code was developed using VeriLogger Pro, by Synapticad.
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// Their support is greatly appreciated.
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//
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//===========================================================================
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`timescale 1ns/1ps
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module plesiochronous_fifo (
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reset_flags_async,
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write_clk,
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write_submit,
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write_data,
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read_clk, read_sync_clk,
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read_fifo_half_full,
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read_consume,
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read_data
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);
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// These parameters MUST be set where the module is instantiated.
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parameter TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION = 0; // typically 100
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parameter RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION = 0; // typically 100
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parameter NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET = 0; // might be 256, for instance
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parameter TRANSMIT_FIFO_WIDTH = 0; // MUST be the same as RECEIVE_FIFO_WIDTH now
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parameter RECEIVE_FIFO_WIDTH = 0;
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input reset_flags_async;
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input write_clk;
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input write_submit;
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input [TRANSMIT_FIFO_WIDTH - 1 : 0] write_data;
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input read_clk, read_sync_clk; // The read_sync_clock is the SAME as the read_clk
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output read_fifo_half_full;
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input read_consume;
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output [RECEIVE_FIFO_WIDTH - 1 : 0] read_data;
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// Calculate paramaters based on the main parameters set by the user.
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parameter WORSE_CASE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION =
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RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION
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+ TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION;
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parameter TRANSMIT_CLOCK_DIVIDED_BY_RECEIVE_CLOCK_RATIO =
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TRANSMIT_FIFO_WIDTH/RECEIVE_FIFO_WIDTH; // must be 1 now
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parameter TRANSMIT_FIFO_CLOCK_SLIP_DEPTH =
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1000000/WORSE_CASE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION;
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function [2:0] grey_code_counter_inc;
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input [2:0] grey_code_counter_in;
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begin
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case (grey_code_counter_in[2:0])
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3'b000: grey_code_counter_inc[2:0] = 3'b001;
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3'b001: grey_code_counter_inc[2:0] = 3'b011;
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3'b011: grey_code_counter_inc[2:0] = 3'b010;
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3'b010: grey_code_counter_inc[2:0] = 3'b110;
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3'b110: grey_code_counter_inc[2:0] = 3'b111;
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3'b111: grey_code_counter_inc[2:0] = 3'b101;
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3'b101: grey_code_counter_inc[2:0] = 3'b100;
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3'b100: grey_code_counter_inc[2:0] = 3'b000;
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default:
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begin
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grey_code_counter_inc[2:0] = 3'b000;
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// synopsys translate_off
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if ($time > 0)
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begin
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$display ("*** %m grey code in to inc has invalid value %h, at %t",
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grey_code_counter_in[2:0], $time);
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end
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else ; // be quiet linterizer
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// synopsys translate_off
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end
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endcase
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end
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endfunction
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function [2:0] grey_to_binary_3;
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input [2:0] grey_code_counter_in;
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begin
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case (grey_code_counter_in[2:0])
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3'b000: grey_to_binary_3[2:0] = 3'b000;
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3'b001: grey_to_binary_3[2:0] = 3'b001;
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3'b011: grey_to_binary_3[2:0] = 3'b010;
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3'b010: grey_to_binary_3[2:0] = 3'b011;
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3'b110: grey_to_binary_3[2:0] = 3'b100;
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3'b111: grey_to_binary_3[2:0] = 3'b101;
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3'b101: grey_to_binary_3[2:0] = 3'b110;
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3'b100: grey_to_binary_3[2:0] = 3'b111;
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default:
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begin
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grey_to_binary_3[2:0] = 3'b000;
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// synopsys translate_off
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if ($time > 0)
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begin
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$display ("*** %m grey code in to binary has invalid value %h, at %t",
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grey_to_binary_3[2:0], $time);
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end
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else ; // be quiet linterizer
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// synopsys translate_off
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end
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endcase
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end
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endfunction
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// Write-side FIFO counters
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reg [2:0] write_pointer_grey_W; // counts 0, 1, 3, 2, 6, 7, 5, 4, 0, 1, ...
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reg [2:0] write_pointer_physical; // counts 0, 1, 2, 3, 4, 0, 1, ...
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always @(posedge write_clk or posedge reset_flags_async)
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begin
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if (reset_flags_async == 1'b1)
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begin
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write_pointer_grey_W[2:0] <= 3'h0;
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write_pointer_physical[2:0] <= 3'h0;
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end
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else
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begin
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if (write_submit == 1'b1)
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begin
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write_pointer_grey_W[2:0] <= grey_code_counter_inc (write_pointer_grey_W[2:0]);
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write_pointer_physical[2:0] <= (write_pointer_physical[2:0] >= 3'h5)
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? 3'h0
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: write_pointer_physical[2:0] + 3'h1;
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end
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else
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begin
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write_pointer_grey_W[2:0] <= write_pointer_grey_W[2:0];
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write_pointer_physical[2:0] <= write_pointer_physical[2:0];
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end
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end
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end
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// Read-side FIFO counters
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reg [2:0] read_pointer_grey; // counts 0, 1, 3, 2, 6, 7, 5, 4, 0, 1, ...
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reg [2:0] read_pointer_physical; // counts 0, 1, 2, 3, 4, 0, 1, ...
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always @(posedge read_clk or posedge reset_flags_async)
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begin
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if (reset_flags_async == 1'b1)
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begin
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read_pointer_grey[2:0] <= 3'h0;
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read_pointer_physical[2:0] <= 3'h0;
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end
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else
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begin
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if (read_consume == 1'b1)
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begin
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read_pointer_grey[2:0] <= grey_code_counter_inc (read_pointer_grey[2:0]);
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read_pointer_physical[2:0] <= (read_pointer_physical[2:0] >= 3'h5)
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? 3'h0
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: read_pointer_physical[2:0] + 3'h1;
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end
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else
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begin
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read_pointer_grey[2:0] <= read_pointer_grey[2:0];
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read_pointer_physical[2:0] <= read_pointer_physical[2:0];
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end
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end
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end
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// NOTE: Very unusual FIFO. It needs to synchronize the Write Pointer into
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298 |
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// the Read clock domain, but does NOT need to synchronize the Read
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299 |
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// Pointer into the Write clock domain. The Writer KNOWS that it
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// can always safely write. This is guaranteed by the Read side
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301 |
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// behavior. That Read side is GUARANTEED to always be reading.
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wire [2:0] write_pointer_grey_sync_R;
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synchronizer_flop sync_write_grey_0 (
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.data_in (write_pointer_grey_W[0]),
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.clk_out (read_sync_clk),
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.sync_data_out (write_pointer_grey_sync_R[0]),
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.async_reset (reset_flags_async)
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);
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synchronizer_flop sync_write_grey_1 (
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.data_in (write_pointer_grey_W[1]),
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.clk_out (read_sync_clk),
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.sync_data_out (write_pointer_grey_sync_R[1]),
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.async_reset (reset_flags_async)
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);
|
318 |
|
|
|
319 |
|
|
synchronizer_flop sync_write_grey_2 (
|
320 |
|
|
.data_in (write_pointer_grey_W[2]),
|
321 |
|
|
.clk_out (read_sync_clk),
|
322 |
|
|
.sync_data_out (write_pointer_grey_sync_R[2]),
|
323 |
|
|
.async_reset (reset_flags_async)
|
324 |
|
|
);
|
325 |
|
|
|
326 |
|
|
// Calculate how much stuff is stored in the FIFO. This can be
|
327 |
|
|
// done by comparing the Read and Write Grey Code Counters.
|
328 |
|
|
// They start out the same. The Write side gets ahead of
|
329 |
|
|
// the read side, until the read side starts unloading.
|
330 |
|
|
// If the write side stops writing, they can get to be the
|
331 |
|
|
// same again.
|
332 |
|
|
// These counters wrap. In the case that the Write Counter is
|
333 |
|
|
// greater than than the Read Counter, the amount of stuff
|
334 |
|
|
// in the FIFO is write pointer - read pointer;
|
335 |
|
|
// In the case that the Write Counter is less than the Read
|
336 |
|
|
// Counter, the amount of stuff in the FIFO is 8 + difference.
|
337 |
|
|
// BUT only the bottom 3 bits matter! That seems to mean
|
338 |
|
|
// that you can simply subtract and look at the bottom 3 bits.
|
339 |
|
|
|
340 |
|
|
wire [2:0] write_pointer_binary_R =
|
341 |
|
|
grey_to_binary_3 (write_pointer_grey_sync_R[2:0]);
|
342 |
|
|
|
343 |
|
|
wire [2:0] read_pointer_binary =
|
344 |
|
|
grey_to_binary_3 (read_pointer_grey[2:0]);
|
345 |
|
|
|
346 |
|
|
wire [2:0] number_of_elements_in_fifo =
|
347 |
|
|
write_pointer_binary_R[2:0] - read_pointer_binary[2:0];
|
348 |
|
|
|
349 |
|
|
// Tell the Receiver to go when there are 2 or more elements in this 5 element FIFO.
|
350 |
|
|
assign read_fifo_half_full = number_of_elements_in_fifo[2:0] >= 3'h3;
|
351 |
|
|
|
352 |
|
|
// FIFO storage
|
353 |
|
|
reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_0;
|
354 |
|
|
reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_1;
|
355 |
|
|
reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_2;
|
356 |
|
|
reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_3;
|
357 |
|
|
reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_4;
|
358 |
|
|
reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_5;
|
359 |
|
|
|
360 |
|
|
always @(posedge write_clk)
|
361 |
|
|
begin
|
362 |
|
|
fifo_0[TRANSMIT_FIFO_WIDTH - 1 : 0] =
|
363 |
|
|
(write_submit & (write_pointer_physical[2:0] == 3'h0))
|
364 |
|
|
? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0]
|
365 |
|
|
: fifo_0[TRANSMIT_FIFO_WIDTH - 1 : 0];
|
366 |
|
|
fifo_1[TRANSMIT_FIFO_WIDTH - 1 : 0] =
|
367 |
|
|
(write_submit & (write_pointer_physical[2:0] == 3'h1))
|
368 |
|
|
? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0]
|
369 |
|
|
: fifo_1[TRANSMIT_FIFO_WIDTH - 1 : 0];
|
370 |
|
|
fifo_2[TRANSMIT_FIFO_WIDTH - 1 : 0] =
|
371 |
|
|
(write_submit & (write_pointer_physical[2:0] == 3'h2))
|
372 |
|
|
? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0]
|
373 |
|
|
: fifo_2[TRANSMIT_FIFO_WIDTH - 1 : 0];
|
374 |
|
|
fifo_3[TRANSMIT_FIFO_WIDTH - 1 : 0] =
|
375 |
|
|
(write_submit & (write_pointer_physical[2:0] == 3'h3))
|
376 |
|
|
? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0]
|
377 |
|
|
: fifo_3[TRANSMIT_FIFO_WIDTH - 1 : 0];
|
378 |
|
|
fifo_4[TRANSMIT_FIFO_WIDTH - 1 : 0] =
|
379 |
|
|
(write_submit & (write_pointer_physical[2:0] == 3'h4))
|
380 |
|
|
? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0]
|
381 |
|
|
: fifo_4[TRANSMIT_FIFO_WIDTH - 1 : 0];
|
382 |
|
|
fifo_5[TRANSMIT_FIFO_WIDTH - 1 : 0] =
|
383 |
|
|
(write_submit & (write_pointer_physical[2:0] == 3'h5))
|
384 |
|
|
? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0]
|
385 |
|
|
: fifo_5[TRANSMIT_FIFO_WIDTH - 1 : 0];
|
386 |
|
|
end
|
387 |
|
|
|
388 |
|
|
// Read port to FIFO
|
389 |
|
|
assign read_data = ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h0}}
|
390 |
|
|
& fifo_0[TRANSMIT_FIFO_WIDTH - 1 : 0])
|
391 |
|
|
| ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h1}}
|
392 |
|
|
& fifo_1[TRANSMIT_FIFO_WIDTH - 1 : 0])
|
393 |
|
|
| ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h2}}
|
394 |
|
|
& fifo_2[TRANSMIT_FIFO_WIDTH - 1 : 0])
|
395 |
|
|
| ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h3}}
|
396 |
|
|
& fifo_3[TRANSMIT_FIFO_WIDTH - 1 : 0])
|
397 |
|
|
| ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h4}}
|
398 |
|
|
& fifo_4[TRANSMIT_FIFO_WIDTH - 1 : 0])
|
399 |
|
|
| ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h5}}
|
400 |
|
|
& fifo_5[TRANSMIT_FIFO_WIDTH - 1 : 0]);
|
401 |
|
|
|
402 |
|
|
// synopsys translate_off
|
403 |
|
|
// ASSUMING that the clock period is 10 nSec, look to make sure data is valid long
|
404 |
|
|
// enough to get through the read MUX. At least 1 write clock period!
|
405 |
|
|
reg written_0, written_1, written_2, written_3, written_4, written_5;
|
406 |
|
|
reg valid_0, valid_1, valid_2, valid_3, valid_4, valid_5;
|
407 |
|
|
initial
|
408 |
|
|
begin
|
409 |
|
|
written_0 = 1'b0;
|
410 |
|
|
written_1 = 1'b0;
|
411 |
|
|
written_2 = 1'b0;
|
412 |
|
|
written_3 = 1'b0;
|
413 |
|
|
written_4 = 1'b0;
|
414 |
|
|
written_5 = 1'b0;
|
415 |
|
|
end
|
416 |
|
|
always @(posedge write_clk)
|
417 |
|
|
begin
|
418 |
|
|
written_0 <= (write_submit & (write_pointer_physical[2:0] == 3'h0)) ^ written_0; // only change when written
|
419 |
|
|
valid_0 <= written_0;
|
420 |
|
|
written_1 <= (write_submit & (write_pointer_physical[2:0] == 3'h1)) ^ written_1;
|
421 |
|
|
valid_1 <= written_1;
|
422 |
|
|
written_2 <= (write_submit & (write_pointer_physical[2:0] == 3'h2)) ^ written_2;
|
423 |
|
|
valid_2 <= written_2;
|
424 |
|
|
written_3 <= (write_submit & (write_pointer_physical[2:0] == 3'h3)) ^ written_3;
|
425 |
|
|
valid_3 <= written_3;
|
426 |
|
|
written_4 <= (write_submit & (write_pointer_physical[2:0] == 3'h4)) ^ written_4;
|
427 |
|
|
valid_4 <= written_4;
|
428 |
|
|
written_5 <= (write_submit & (write_pointer_physical[2:0] == 3'h5)) ^ written_5;
|
429 |
|
|
valid_5 <= written_5;
|
430 |
|
|
end
|
431 |
|
|
always @(posedge read_clk)
|
432 |
|
|
begin
|
433 |
|
|
if (read_consume & (read_pointer_physical[2:0] == 3'h0) & (written_0 ^ valid_0))
|
434 |
|
|
$display ("*** read data 0 not valid for full read clock at %t", $time);
|
435 |
|
|
if (read_consume & (read_pointer_physical[2:0] == 3'h1) & (written_1 ^ valid_1))
|
436 |
|
|
$display ("*** read data 1 not valid for full read clock at %t", $time);
|
437 |
|
|
if (read_consume & (read_pointer_physical[2:0] == 3'h2) & (written_2 ^ valid_2))
|
438 |
|
|
$display ("*** read data 2 not valid for full read clock at %t", $time);
|
439 |
|
|
if (read_consume & (read_pointer_physical[2:0] == 3'h3) & (written_3 ^ valid_3))
|
440 |
|
|
$display ("*** read data 3 not valid for full read clock at %t", $time);
|
441 |
|
|
if (read_consume & (read_pointer_physical[2:0] == 3'h4) & (written_4 ^ valid_4))
|
442 |
|
|
$display ("*** read data 4 not valid for full read clock at %t", $time);
|
443 |
|
|
if (read_consume & (read_pointer_physical[2:0] == 3'h5) & (written_5 ^ valid_5))
|
444 |
|
|
$display ("*** read data 5 not valid for full read clock at %t", $time);
|
445 |
|
|
end
|
446 |
|
|
|
447 |
|
|
// Check that there is never more than 5 words in this FIFO. I know, that
|
448 |
|
|
// means there only needs to be 5 sets of flops!
|
449 |
|
|
// Remember that there MIGHT be more data in the FIFO than the receive side
|
450 |
|
|
// thinks, because the Write Pointer might not have been incremented. Also,
|
451 |
|
|
// due to jitter, the Write side might get 2 writes (!) in between any 2
|
452 |
|
|
// adjacent Read side clocks. This MIGHT mean that the data can go from
|
453 |
|
|
// having 3 entry in it to having 5 entries. Then, as the write clock
|
454 |
|
|
// contiues to run fast, the FIFO might work up to having 6 full entries.
|
455 |
|
|
// The other excuse I can have to having the extra set of flops is that it
|
456 |
|
|
// makes it clear that hold times are met, even when a write happens at
|
457 |
|
|
// the exact same time as the read which frees up the 5th entry.
|
458 |
|
|
// I feel much more confident with a 6th available entry.
|
459 |
|
|
|
460 |
|
|
always @(posedge read_clk)
|
461 |
|
|
begin
|
462 |
|
|
if (number_of_elements_in_fifo[2:0] >= 3'h6)
|
463 |
|
|
$display ("*** %m fatal plesiochronous FIFO got too much data in it at %t", $time);
|
464 |
|
|
end
|
465 |
|
|
// synopsys translate_on
|
466 |
|
|
|
467 |
|
|
// synopsys translate_off
|
468 |
|
|
initial
|
469 |
|
|
begin
|
470 |
|
|
if (TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION <= 0)
|
471 |
|
|
begin
|
472 |
|
|
$display ("*** Exiting because %m TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION %d <= 0",
|
473 |
|
|
TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION);
|
474 |
|
|
$finish;
|
475 |
|
|
end
|
476 |
|
|
if (RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION <= 0)
|
477 |
|
|
begin
|
478 |
|
|
$display ("*** Exiting because %m RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION %d <= 0",
|
479 |
|
|
RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION);
|
480 |
|
|
$finish;
|
481 |
|
|
end
|
482 |
|
|
if (NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET <= 0)
|
483 |
|
|
begin
|
484 |
|
|
$display ("*** Exiting because %m NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET %d <= 0",
|
485 |
|
|
NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET);
|
486 |
|
|
$finish;
|
487 |
|
|
end
|
488 |
|
|
if (TRANSMIT_FIFO_WIDTH <= 0)
|
489 |
|
|
begin
|
490 |
|
|
$display ("*** Exiting because %m TRANSMIT_FIFO_WIDTH %d <= 0",
|
491 |
|
|
TRANSMIT_FIFO_WIDTH);
|
492 |
|
|
$finish;
|
493 |
|
|
end
|
494 |
|
|
if (RECEIVE_FIFO_WIDTH <= 0)
|
495 |
|
|
begin
|
496 |
|
|
$display ("*** Exiting because %m RECEIVE_FIFO_WIDTH %d <= 0",
|
497 |
|
|
RECEIVE_FIFO_WIDTH);
|
498 |
|
|
$finish;
|
499 |
|
|
end
|
500 |
|
|
// NOTE: WORKING: Remove this restriction when this becomes able to write
|
501 |
|
|
// data with a different width than the read data port is.
|
502 |
|
|
// This will require the clocks to run at the ratio set by
|
503 |
|
|
// the rations of the FIFO port widths!
|
504 |
|
|
if (TRANSMIT_FIFO_WIDTH != RECEIVE_FIFO_WIDTH)
|
505 |
|
|
begin
|
506 |
|
|
$display ("*** Exiting because %m TRANSMIT_FIFO_WIDTH != RECEIVE_FIFO_WIDTH %d <= 0",
|
507 |
|
|
TRANSMIT_FIFO_WIDTH, RECEIVE_FIFO_WIDTH);
|
508 |
|
|
$finish;
|
509 |
|
|
end
|
510 |
|
|
|
511 |
|
|
// The Sender needs to know that it will not overrun the FIFO even if it is running
|
512 |
|
|
// faster than the Receiver. It needs to make careful calculations to make sure
|
513 |
|
|
// this is true.
|
514 |
|
|
// It knows that the Receiver won't start unloading until it thinks the FIFO is
|
515 |
|
|
// at least 1/2 full. But when is the latest this can happen?
|
516 |
|
|
// The latest is when the Sender writes word 0, then word 1, BUT the indication
|
517 |
|
|
// that word 1 is available does not get latched by the receiver until the
|
518 |
|
|
// NEXT clock. At that time, the Sender writes entry 2.
|
519 |
|
|
// The Receiver unloads data from word 0 at the same time the sender writes word 3.
|
520 |
|
|
// So the FIFO has valid data in locations 1, 2, and 3.
|
521 |
|
|
// The FIFO has 3 valid words in it at the start.
|
522 |
|
|
// If the Sender writes faster than the Receiver reads, the FIFO can work up to
|
523 |
|
|
// having 4 words of valid data in it.
|
524 |
|
|
//
|
525 |
|
|
// The Receiver needs to know that it will not run out of data if it unloads
|
526 |
|
|
// faster than the Sender sends. How can it check this?
|
527 |
|
|
// The earliest the Receiver can know that data is available is if the Sender
|
528 |
|
|
// writes word 0, the word 1, and the Receiver hears about the data available
|
529 |
|
|
// instantly. Then, the Sender writes word 2 while the receiver unloads word 0.
|
530 |
|
|
// So the FIFO has valid data in locations 1 and 2.
|
531 |
|
|
// The FIFO has 2 words of data in it at the start.
|
532 |
|
|
// If the Receiver reads faster than the Sender writes, the FIFO can work down to
|
533 |
|
|
// having 1 word of valid data in it.
|
534 |
|
|
//
|
535 |
|
|
// Having 4 words max and 1 word min are fine constraints on the FIFO's behavior.
|
536 |
|
|
// To meet the constraints, the Sender and Receiver clocks must not vary too far
|
537 |
|
|
// from one-another. If they got too far apart, too much data would be either
|
538 |
|
|
// read or written throught the FIFO.
|
539 |
|
|
|
540 |
|
|
// Calculate the maximum clock difference possible.
|
541 |
|
|
// NOTE: This calculation will have to take into account different port widths
|
542 |
|
|
// with corresponding different port clocks, if and when this is improved to
|
543 |
|
|
// allow port size changes across the FIFO.
|
544 |
|
|
|
545 |
|
|
if (TRANSMIT_FIFO_CLOCK_SLIP_DEPTH < NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET)
|
546 |
|
|
begin
|
547 |
|
|
$display ("*** Exiting because %m TRANSMIT_FIFO_CLOCK_SLIP_DEPTH %d < NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET %d",
|
548 |
|
|
TRANSMIT_FIFO_CLOCK_SLIP_DEPTH, NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET);
|
549 |
|
|
$finish;
|
550 |
|
|
end
|
551 |
|
|
end
|
552 |
|
|
// synopsys translate_on
|
553 |
|
|
endmodule
|
554 |
|
|
|
555 |
|
|
// `define TEST_PLESIOCHRONOUS_FIFO
|
556 |
|
|
`ifdef TEST_PLESIOCHRONOUS_FIFO
|
557 |
|
|
module test_plesiochronous_fifo;
|
558 |
|
|
// Plan: do a bunch of packets when the Write Clock is faster than the Read Clock
|
559 |
|
|
// Then do a bunch of packets when the Read Clock is faster than the Write Clock
|
560 |
|
|
//
|
561 |
|
|
// Experiment with small clock deltas to change event ordering.
|
562 |
|
|
// Print out at run time when the receiver is slipping clocks
|
563 |
|
|
// Check that data is strictly incrementing; no drops or repeats
|
564 |
|
|
real transmit_clock_period, receive_clock_period;
|
565 |
|
|
real transmit_clock_delta, receive_clock_delta;
|
566 |
|
|
integer packet_length;
|
567 |
|
|
integer packets_to_send;
|
568 |
|
|
integer i, j, k, l;
|
569 |
|
|
|
570 |
|
|
reg reset_flags_async;
|
571 |
|
|
reg write_clk;
|
572 |
|
|
reg write_submit;
|
573 |
|
|
reg [31:0] write_data;
|
574 |
|
|
reg read_clk;
|
575 |
|
|
wire read_fifo_half_full;
|
576 |
|
|
reg read_consume;
|
577 |
|
|
reg [31:0] expected_read_data;
|
578 |
|
|
wire [31:0] read_data;
|
579 |
|
|
|
580 |
|
|
task read_one_item;
|
581 |
|
|
begin
|
582 |
|
|
#0;
|
583 |
|
|
read_clk = 1'b1;
|
584 |
|
|
#receive_clock_period;
|
585 |
|
|
read_clk = 1'b0;
|
586 |
|
|
#receive_clock_period;
|
587 |
|
|
end
|
588 |
|
|
endtask
|
589 |
|
|
|
590 |
|
|
task write_one_item;
|
591 |
|
|
begin
|
592 |
|
|
#0;
|
593 |
|
|
write_clk = 1'b1;
|
594 |
|
|
#transmit_clock_period;
|
595 |
|
|
write_clk = 1'b0;
|
596 |
|
|
#transmit_clock_period;
|
597 |
|
|
end
|
598 |
|
|
endtask
|
599 |
|
|
|
600 |
|
|
task send_and_check;
|
601 |
|
|
begin
|
602 |
|
|
fork // Write Clock faster than Read Clock
|
603 |
|
|
begin // transmit activity
|
604 |
|
|
write_clk = 1'b0;
|
605 |
|
|
reset_flags_async = 1'b1;
|
606 |
|
|
# 10;
|
607 |
|
|
reset_flags_async = 1'b0;
|
608 |
|
|
# 10;
|
609 |
|
|
# transmit_clock_delta;
|
610 |
|
|
write_data[31:0] = 32'h00000000;
|
611 |
|
|
for (i = 0; i < packets_to_send; i = i + 1)
|
612 |
|
|
begin
|
613 |
|
|
write_submit = 1'b1;
|
614 |
|
|
for (j = 0; j < packet_length; j = j + 1)
|
615 |
|
|
begin
|
616 |
|
|
write_data[31:0] = write_data[31:0] + 32'h00000001;
|
617 |
|
|
write_one_item; // send 1 data item;
|
618 |
|
|
end
|
619 |
|
|
write_submit = 1'b0;
|
620 |
|
|
write_one_item; // skip a write;
|
621 |
|
|
end
|
622 |
|
|
end
|
623 |
|
|
|
624 |
|
|
begin // receive activity
|
625 |
|
|
read_clk = 1'b0;
|
626 |
|
|
# 10;
|
627 |
|
|
# 10;
|
628 |
|
|
# receive_clock_delta;
|
629 |
|
|
expected_read_data[31:0] = 32'h00000001;
|
630 |
|
|
for (k = 0; k < packets_to_send; k = k + 1)
|
631 |
|
|
begin
|
632 |
|
|
read_consume = 1'b0;
|
633 |
|
|
if (k == 0) // wait for the first one
|
634 |
|
|
begin
|
635 |
|
|
while (read_fifo_half_full == 1'b0)
|
636 |
|
|
begin
|
637 |
|
|
read_one_item; // snooze
|
638 |
|
|
end
|
639 |
|
|
end
|
640 |
|
|
else // all subsequent ones should be back-to-back.
|
641 |
|
|
begin
|
642 |
|
|
if (read_fifo_half_full == 1'b1)
|
643 |
|
|
begin
|
644 |
|
|
$display ("Reading with 0 delay");
|
645 |
|
|
end
|
646 |
|
|
else
|
647 |
|
|
begin
|
648 |
|
|
read_one_item; // snooze
|
649 |
|
|
if (read_fifo_half_full == 1'b1)
|
650 |
|
|
begin
|
651 |
|
|
$display ("Reading with 1 delay");
|
652 |
|
|
end
|
653 |
|
|
else
|
654 |
|
|
begin
|
655 |
|
|
read_one_item; // snooze
|
656 |
|
|
if (read_fifo_half_full == 1'b1)
|
657 |
|
|
begin
|
658 |
|
|
$display ("Reading with 2 delay");
|
659 |
|
|
end
|
660 |
|
|
else
|
661 |
|
|
begin
|
662 |
|
|
read_one_item; // snooze
|
663 |
|
|
if (read_fifo_half_full == 1'b1)
|
664 |
|
|
begin
|
665 |
|
|
$display ("Reading with 3 delay");
|
666 |
|
|
end
|
667 |
|
|
else
|
668 |
|
|
begin
|
669 |
|
|
$display ("*** Data didn't become available!");
|
670 |
|
|
end
|
671 |
|
|
end
|
672 |
|
|
end
|
673 |
|
|
end
|
674 |
|
|
end
|
675 |
|
|
read_consume = 1'b1; // this is a combinational copy of read_fifo_half_full!
|
676 |
|
|
for (l = 0; l < packet_length; l = l + 1)
|
677 |
|
|
begin
|
678 |
|
|
if (expected_read_data[31:0] !== read_data[31:0])
|
679 |
|
|
begin
|
680 |
|
|
$display ("*** Data wasn't as expected! %h %h",
|
681 |
|
|
read_data[31:0], expected_read_data[31:0]);
|
682 |
|
|
end
|
683 |
|
|
read_one_item;
|
684 |
|
|
expected_read_data[31:0] = expected_read_data[31:0] + 32'h0000001;
|
685 |
|
|
end
|
686 |
|
|
end
|
687 |
|
|
end
|
688 |
|
|
join
|
689 |
|
|
end
|
690 |
|
|
endtask
|
691 |
|
|
|
692 |
|
|
real normal_clk, fast_clk, slow_clk;
|
693 |
|
|
|
694 |
|
|
initial
|
695 |
|
|
begin
|
696 |
|
|
packet_length = 20; // needed if each clock varies <= 25000 parts per million
|
697 |
|
|
packets_to_send = 200;
|
698 |
|
|
normal_clk = 5.0;
|
699 |
|
|
fast_clk = normal_clk * 0.976; // FAILS if 9.75, 1.025 !?!
|
700 |
|
|
slow_clk = normal_clk * 1.024;
|
701 |
|
|
|
702 |
|
|
$display ("Same Frequency, no offset");
|
703 |
|
|
transmit_clock_period = normal_clk;
|
704 |
|
|
receive_clock_period = normal_clk;
|
705 |
|
|
transmit_clock_delta = 0.000;
|
706 |
|
|
receive_clock_delta = 0.000;
|
707 |
|
|
|
708 |
|
|
send_and_check;
|
709 |
|
|
|
710 |
|
|
$display ("Same Frequency, Transmit late");
|
711 |
|
|
transmit_clock_period = normal_clk;
|
712 |
|
|
receive_clock_period = normal_clk;
|
713 |
|
|
transmit_clock_delta = 0.001;
|
714 |
|
|
receive_clock_delta = 0.000;
|
715 |
|
|
|
716 |
|
|
send_and_check;
|
717 |
|
|
|
718 |
|
|
$display ("Same Frequency, Receive late");
|
719 |
|
|
transmit_clock_period = normal_clk;
|
720 |
|
|
receive_clock_period = normal_clk;
|
721 |
|
|
transmit_clock_delta = 0.000;
|
722 |
|
|
receive_clock_delta = 0.001;
|
723 |
|
|
|
724 |
|
|
send_and_check;
|
725 |
|
|
|
726 |
|
|
|
727 |
|
|
$display ("Transmit Fast, no offset");
|
728 |
|
|
transmit_clock_period = fast_clk;
|
729 |
|
|
receive_clock_period = slow_clk;
|
730 |
|
|
transmit_clock_delta = 0.000;
|
731 |
|
|
receive_clock_delta = 0.000;
|
732 |
|
|
|
733 |
|
|
send_and_check;
|
734 |
|
|
|
735 |
|
|
$display ("Transmit Fast, Transmit late");
|
736 |
|
|
transmit_clock_period = fast_clk;
|
737 |
|
|
receive_clock_period = slow_clk;
|
738 |
|
|
transmit_clock_delta = 0.001;
|
739 |
|
|
receive_clock_delta = 0.000;
|
740 |
|
|
|
741 |
|
|
send_and_check;
|
742 |
|
|
|
743 |
|
|
$display ("Transmit Fast, Receive late");
|
744 |
|
|
transmit_clock_period = fast_clk;
|
745 |
|
|
receive_clock_period = slow_clk;
|
746 |
|
|
transmit_clock_delta = 0.000;
|
747 |
|
|
receive_clock_delta = 0.001;
|
748 |
|
|
|
749 |
|
|
send_and_check;
|
750 |
|
|
|
751 |
|
|
|
752 |
|
|
$display ("Receive Fast, no offset");
|
753 |
|
|
transmit_clock_period = slow_clk;
|
754 |
|
|
receive_clock_period = fast_clk;
|
755 |
|
|
transmit_clock_delta = 0.000;
|
756 |
|
|
receive_clock_delta = 0.000;
|
757 |
|
|
|
758 |
|
|
send_and_check;
|
759 |
|
|
|
760 |
|
|
$display ("Receive Fast, Transmit late");
|
761 |
|
|
transmit_clock_period = slow_clk;
|
762 |
|
|
receive_clock_period = fast_clk;
|
763 |
|
|
transmit_clock_delta = 0.001;
|
764 |
|
|
receive_clock_delta = 0.000;
|
765 |
|
|
|
766 |
|
|
send_and_check;
|
767 |
|
|
|
768 |
|
|
$display ("Receive Fast, Receive late");
|
769 |
|
|
transmit_clock_period = slow_clk;
|
770 |
|
|
receive_clock_period = fast_clk;
|
771 |
|
|
transmit_clock_delta = 0.000;
|
772 |
|
|
receive_clock_delta = 0.001;
|
773 |
|
|
|
774 |
|
|
send_and_check;
|
775 |
|
|
|
776 |
|
|
end
|
777 |
|
|
|
778 |
|
|
|
779 |
|
|
// Instantiation parameters are in order:
|
780 |
|
|
// TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION
|
781 |
|
|
// RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION
|
782 |
|
|
// NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET
|
783 |
|
|
// TRANSMIT_FIFO_WIDTH
|
784 |
|
|
// RECEIVE_FIFO_WIDTH
|
785 |
|
|
|
786 |
|
|
plesiochronous_fifo #(25000, 25000, 20, 32, 32) test_fifo (
|
787 |
|
|
.reset_flags_async (reset_flags_async),
|
788 |
|
|
.write_clk (write_clk),
|
789 |
|
|
.write_submit (write_submit),
|
790 |
|
|
.write_data (write_data[31:0]),
|
791 |
|
|
.read_clk (read_clk),
|
792 |
|
|
.read_sync_clk (read_clk),
|
793 |
|
|
.read_fifo_half_full (read_fifo_half_full),
|
794 |
|
|
.read_consume (read_consume),
|
795 |
|
|
.read_data (read_data[31:0])
|
796 |
|
|
);
|
797 |
|
|
`endif // TEST_PLESIOCHRONOUS_FIFO
|
798 |
|
|
endmodule
|
799 |
|
|
|
800 |
|
|
|