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Sample IP CoreSpecification
Author: Lior Shtram
lior.shtram@flextronicssemi.com
Rev. 0.8
TIME \@ "MMMM d, yyyy" October 22, 2001
This page has been intentionally left blank.
Revision History
Rev.DateAuthorDescription0.130/1/01Lior ShtramFirst Draft0.22/201Rudolf UsselmannRemoved Header and Footer on Title Page.
Changed Page numbering to start after Title Page.
Changed Document Title Font to Times.0.306/02/01Richard HerveilleChanged OpenCores.com to OpenCores.org.
Changed tables so WISHBONE signals fit into cells, centered width column.
Changed page-numbering, start counting from Introduction page using Arabic numbers. Use Roman numbers for other pages.
Changed date on title page to autoupdate.
Added Contents page, used crosslinks for automatic header and page number generation.0.413/3/01Yair AmitayAdded Clocks section.0.53/5/01Jeanne WiegelmannCapitalized and modified headings.
Added shadings to tables.
Saved template as dot.0.613/5/01Jeanne WiegelmannModified document styles.
Created new Table of Contents.0.615/5/01Jeanne WiegelmannAdded Appendix and Index.0.729/5/01Damjan LampretChanged chapter order. Added OC logo.0.822/10/01Damjan LampretChanged all port names as per new coding guidelines convention.
Contents
TOC \t "Heading 3,2,Index,1,Appendix A,1,Heading 2 name,1,Appendix B,1" Introduction PAGEREF _Toc518887500 \h 3
Architecture PAGEREF _Toc518887501 \h 3
Operation PAGEREF _Toc518887502 \h 3
Registers PAGEREF _Toc518887503 \h 3
List of Registers PAGEREF _Toc518887504 \h 3
Register 1 Description PAGEREF _Toc518887505 \h 3
Clocks PAGEREF _Toc518887506 \h 3
IO Ports PAGEREF _Toc518887507 \h 3
Appendix A PAGEREF _Toc518887508 \h 3
Appendix B PAGEREF _Toc518887509 \h 3
Index PAGEREF _Toc518887510 \h 3
Introduction
This section contains the introduction to the core, describing its use and features.
Architecture
This section describes the architecture of the block. A block diagram should be included describing the top level of the design.
Operation
This section describes the operation of the core. Specific sequences, such as startup sequences, as well as the modes and states of the block should be described.
Registers
This section specifies all internal registers. It should completely cover the interface between the core and the host as seen from the software view.
List of Registers
NameAddressWidthAccessDescriptionTable SEQ Table \* ARABIC 1: List of registers
Register 1 Description
(You shall choose the style of register you prefer. Do not use both options in one and the same document.)
Bit #AccessDescriptionReset Value:
Reg_Name: 0000h
31302928...876543210Table SEQ Table \* ARABIC 2: Description of registers
Reset Value:
Reg_Name: 0000h
Clocks
This section specifies all the clocks. All clocks, clock domain passes and the clock relations should be described.
NameSourceRates (MHz)RemarksDescriptionMaxMinResolutionclk_pad_iInput Pad1040.1Duty cycle 70/30.For external interface.wb_clk_IPLL200--Must be synchronized to sm_clk_iSystem clock.sm_clk_iInput port55401There are multi-clocks paths.Clock 55MHz for State machine.Table SEQ Table \* ARABIC 3: List of clocks
IO Ports
This section specifies the core IO ports.
PortWidthDirectionDescriptionwb_clk_i1InputBlocks WISHBONE Clock Inputwb_rst_i1InputBlocks WISHBONE Reset Inputwb_sel_i4InputBlocks WISHBONE Select Inputsfoo_pad_o1OutputBlocks foo output to output padTable SEQ Table \* ARABIC 4: List of IO ports
Name
This section may be added to outline different specifications.
Name
This section may be added to outline different specifications.
This section contains an alphabetical list of helpful document entries with their corresponding page numbers.
OpenCores TITLE \* MERGEFORMAT Specifications Template DATE \* MERGEFORMAT 10/22/01
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.8 Preliminary PAGE ii
OpenCores TITLE \* MERGEFORMAT Specifications Template DATE \* MERGEFORMAT 10/22/01
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.8 Preliminary PAGE iv
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.8 Preliminary PAGE 9 of SECTIONPAGES9
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