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[/] [common/] [trunk/] [synchronizer_flop.v] - Blame information for rev 48

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//===========================================================================
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// $Id: synchronizer_flop.v,v 1.4 2001-09-03 13:18:30 bbeaver Exp $
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//
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// synchronizer_flop                                            ////
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////                                                              ////
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//// This file is part of the general opencores effort.           ////
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//// <http://www.opencores.org/cores/misc/>                       ////
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////                                                              ////
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//// Module Description:                                          ////
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////                                                              ////
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//// Make a rising-edge triggered flop with async reset with a    ////
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////   distinguished name so that it can be replaced with a flop  ////
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////   which does not make X's during simulation.                 ////
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////                                                              ////
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//// This flop should be used instead of a regular flop for ALL   ////
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////   cross-clock-domain flops.  Manually instantiating this     ////
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////   flop for all signals which must NEVER go to 1'bX during    ////
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////   simulation will make it possible for the user to           ////
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////   substitute a simulation model which does NOT have setup    ////
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////   and hold checks.                                           ////
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////                                                              ////
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//// If a target device library has a component which is          ////
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////   especially well suited to perform this function, it should ////
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////   be instantiated by name in this file.  Otherwise, the      ////
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////   behaviorial version of this module will be used.           ////
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////                                                              ////
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//// To Do:                                                       ////
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//// Nothing                                                      ////
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////                                                              ////
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//// Author(s):                                                   ////
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//// - anynomous                                                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2001/09/03 11:16:00  Blue Beaver
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// no message
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//
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// Revision 1.1.1.1  2001/09/03 10:24:58  bbeaver
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// no message
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//
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// Revision 1.1  2001/09/02 11:32:03  Blue Beaver
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// no message
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//
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//
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`timescale 1ns/1ps
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// If the vendor has a flop which is particularly good at settling out of
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//   metastability, it should be used here.
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module synchronizer_flop (
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  data_in, clk_out, sync_data_out, async_reset
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);
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  input   data_in;
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  input   clk_out;
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  output  sync_data_out;
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  input   async_reset;
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  reg     sync_data_out;
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  always @(posedge clk_out or posedge async_reset)
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  begin
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    if (async_reset == 1'b1)
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    begin
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      sync_data_out <= 1'b0;
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    end
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    else
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    begin
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// In gate-level simulation, must only go to 1'bX if the input is 1'bX or 1'bZ.
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// This should NEVER go to 1'bX due to setup or hold violations.
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      sync_data_out <= data_in;
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    end
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  end
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endmodule
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