1 |
3 |
danv |
--------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
4 |
danv |
-- Copyright 2020
|
4 |
|
|
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
|
5 |
|
|
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
|
6 |
|
|
--
|
7 |
|
|
-- Licensed under the Apache License, Version 2.0 (the "License");
|
8 |
|
|
-- you may not use this file except in compliance with the License.
|
9 |
|
|
-- You may obtain a copy of the License at
|
10 |
|
|
--
|
11 |
|
|
-- http://www.apache.org/licenses/LICENSE-2.0
|
12 |
|
|
--
|
13 |
|
|
-- Unless required by applicable law or agreed to in writing, software
|
14 |
|
|
-- distributed under the License is distributed on an "AS IS" BASIS,
|
15 |
|
|
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
16 |
|
|
-- See the License for the specific language governing permissions and
|
17 |
|
|
-- limitations under the License.
|
18 |
3 |
danv |
--
|
19 |
|
|
--------------------------------------------------------------------------------
|
20 |
|
|
|
21 |
|
|
-- Purpose: Shift register for control data bit
|
22 |
|
|
-- Description:
|
23 |
|
|
-- Delays input data by g_depth. The delay line shifts when in_val is
|
24 |
|
|
-- indicates an active clock cycle.
|
25 |
|
|
-- Remark:
|
26 |
|
|
-- . This common_bit_delay can not use common_delay.vhd because it needs a reset.
|
27 |
|
|
-- . Typically rst may be left not connected, because the internal power up
|
28 |
|
|
-- state of the shift_reg is 0.
|
29 |
|
|
-- . If dynamic restart control is needed then use in_clr for that. Otherwise
|
30 |
|
|
-- leave in_clr also not connected.
|
31 |
|
|
-- . For large g_depth Quartus infers a RAM block for this bitDelay even if
|
32 |
|
|
-- the same signal is applied to both in_bit and in_val. It does not help
|
33 |
|
|
-- to remove in_clr or to not use shift_reg(0) combinatorially.
|
34 |
|
|
|
35 |
|
|
library IEEE;
|
36 |
|
|
use IEEE.std_logic_1164.all;
|
37 |
|
|
|
38 |
|
|
entity common_bit_delay is
|
39 |
|
|
generic (
|
40 |
|
|
g_depth : NATURAL := 16 --Quartus infers fifo for 4 to 4096 g_depth, 8 Bits.
|
41 |
|
|
);
|
42 |
|
|
port (
|
43 |
|
|
clk : in std_logic;
|
44 |
|
|
rst : in std_logic := '0'; -- asynchronous reset for initial start
|
45 |
|
|
in_clr : in std_logic := '0'; -- synchronous reset for control of dynamic restart(s)
|
46 |
|
|
in_bit : in std_logic;
|
47 |
|
|
in_val : in std_logic := '1';
|
48 |
|
|
out_bit : out std_logic
|
49 |
|
|
);
|
50 |
|
|
end entity common_bit_delay;
|
51 |
|
|
|
52 |
|
|
architecture rtl of common_bit_delay is
|
53 |
|
|
|
54 |
|
|
-- Use index (0) as combinatorial input and index(1:g_depth) for the shift
|
55 |
|
|
-- delay, in this way the shift_reg type can support all g_depth >= 0
|
56 |
|
|
signal shift_reg : std_logic_vector(0 to g_depth) := (others=>'0');
|
57 |
|
|
|
58 |
|
|
begin
|
59 |
|
|
|
60 |
|
|
shift_reg(0) <= in_bit;
|
61 |
|
|
|
62 |
|
|
out_bit <= shift_reg(g_depth);
|
63 |
|
|
|
64 |
|
|
gen_reg : if g_depth>0 generate
|
65 |
|
|
p_clk : process(clk, rst)
|
66 |
|
|
begin
|
67 |
|
|
if rst='1' then
|
68 |
|
|
shift_reg(1 to g_depth) <= (others=>'0');
|
69 |
|
|
elsif rising_edge(clk) then
|
70 |
|
|
if in_clr='1' then
|
71 |
|
|
shift_reg(1 to g_depth) <= (others=>'0');
|
72 |
|
|
elsif in_val='1' then
|
73 |
|
|
shift_reg(1 to g_depth) <= shift_reg(0 to g_depth-1);
|
74 |
|
|
end if;
|
75 |
|
|
end if;
|
76 |
|
|
end process;
|
77 |
|
|
end generate;
|
78 |
|
|
|
79 |
|
|
end rtl;
|