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[/] [common_components/] [trunk/] [common_pipeline.vhd] - Blame information for rev 4

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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- 
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- 
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--     http://www.apache.org/licenses/LICENSE-2.0
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-- 
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY common_pipeline IS
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  GENERIC (
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    g_representation : STRING  := "SIGNED";   -- or "UNSIGNED"
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    g_pipeline       : NATURAL := 1;  -- 0 for wires, > 0 for registers, 
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    g_reset_value    : INTEGER := 0;
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    g_in_dat_w       : NATURAL := 8;
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    g_out_dat_w      : NATURAL := 9
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  );
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  PORT (
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    rst     : IN  STD_LOGIC := '0';
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    clk     : IN  STD_LOGIC;
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    clken   : IN  STD_LOGIC := '1';
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    in_clr  : IN  STD_LOGIC := '0';
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    in_en   : IN  STD_LOGIC := '1';
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    in_dat  : IN  STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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    out_dat : OUT STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0)
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  );
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END common_pipeline;
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ARCHITECTURE rtl OF common_pipeline IS
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  CONSTANT c_reset_value : STD_LOGIC_VECTOR(out_dat'RANGE) := TO_SVEC(g_reset_value, out_dat'LENGTH);
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  TYPE t_out_dat IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(out_dat'RANGE);
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  SIGNAL out_dat_p  : t_out_dat(0 TO g_pipeline) := (OTHERS=>c_reset_value);
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BEGIN
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  gen_pipe_n : IF g_pipeline>0 GENERATE
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    p_clk : PROCESS(clk, rst)
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    BEGIN
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      IF rst='1' THEN
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        out_dat_p(1 TO g_pipeline) <= (OTHERS=>c_reset_value);
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      ELSIF rising_edge(clk) THEN
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        IF clken='1' THEN
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          IF in_clr = '1' THEN
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            out_dat_p(1 TO g_pipeline) <= (OTHERS=>c_reset_value);
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          ELSIF in_en = '1' THEN
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            out_dat_p(1 TO g_pipeline) <= out_dat_p(0 TO g_pipeline-1);
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          END IF;
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        END IF;
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      END IF;
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    END PROCESS;
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  END GENERATE;
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  out_dat_p(0) <= RESIZE_SVEC(in_dat, out_dat'LENGTH) WHEN g_representation=  "SIGNED" ELSE
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                  RESIZE_UVEC(in_dat, out_dat'LENGTH) WHEN g_representation="UNSIGNED";
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  out_dat <= out_dat_p(g_pipeline);
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END rtl;

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