OpenCores
URL https://opencores.org/ocsvn/complexise/complexise/trunk

Subversion Repositories complexise

[/] [complexise/] [trunk/] [CI_ALTFP_MULT.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 iloveliora 
-- megafunction wizard: %ALTFP_MULT%
2 
-- GENERATION: STANDARD
3 
-- VERSION: WM1.0
4 
-- MODULE: altfp_mult
5 
 
6 
-- ============================================================
7 
-- File Name: CI_ALTFP_MULT.vhd
8 
-- Megafunction Name(s):
9 
--                      altfp_mult
10 
--
11 
-- Simulation Library Files(s):
12 
--                      lpm
13 
-- ============================================================
14 
-- ************************************************************
15 
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 
--
17 
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
18 
-- ************************************************************
19 
 
20 
 
21 
--Copyright (C) 1991-2009 Altera Corporation
22 
--Your use of Altera Corporation's design tools, logic functions
23 
--and other software and tools, and its AMPP partner logic
24 
--functions, and any output files from any of the foregoing
25 
--(including device programming or simulation files), and any
26 
--associated documentation or information are expressly subject
27 
--to the terms and conditions of the Altera Program License
28 
--Subscription Agreement, Altera MegaCore Function License
29 
--Agreement, or other applicable license agreement, including,
30 
--without limitation, that your use is for the sole purpose of
31 
--programming logic devices manufactured by Altera and sold by
32 
--Altera or its authorized distributors.  Please refer to the
33 
--applicable agreement for further details.
34 
 
35 
 
36 
--altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix" PIPELINE=6 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab nan overflow result underflow zero
37 
--VERSION_BEGIN 9.0SP2 cbx_alt_ded_mult_y 2008:05:19:10:01:35:SJ cbx_altbarrel_shift 2008:08:28:01:40:10:SJ cbx_altfp_mult 2008:05:19:10:46:44:SJ cbx_altmult_add 2009:04:07:18:02:29:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_mult 2008:09:30:18:36:56:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_padd 2008:09:04:11:11:31:SJ cbx_parallel_add 2008:05:19:10:26:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ  VERSION_END
38 
 
39 
 LIBRARY lpm;
40 
 USE lpm.all;
41 
 
42 
--synthesis_resources = lpm_add_sub 4 lpm_mult 1 lut 154
43 
 LIBRARY ieee;
44 
 USE ieee.std_logic_1164.all;
45 
 
46 
 ENTITY  CI_ALTFP_MULT_altfp_mult_50n IS
47 
         PORT
48 
         (
49 
                 aclr   :       IN  STD_LOGIC := '0';
50 
                 clk_en :       IN  STD_LOGIC := '1';
51 
                 clock  :       IN  STD_LOGIC;
52 
                 dataa  :       IN  STD_LOGIC_VECTOR (31 DOWNTO 0);
53 
                 datab  :       IN  STD_LOGIC_VECTOR (31 DOWNTO 0);
54 
                 nan    :       OUT  STD_LOGIC;
55 
                 overflow       :       OUT  STD_LOGIC;
56 
                 result :       OUT  STD_LOGIC_VECTOR (31 DOWNTO 0);
57 
                 underflow      :       OUT  STD_LOGIC;
58 
                 zero   :       OUT  STD_LOGIC
59 
         );
60 
 END CI_ALTFP_MULT_altfp_mult_50n;
61 
 
62 
 ARCHITECTURE RTL OF CI_ALTFP_MULT_altfp_mult_50n IS
63 
 
64 
         SIGNAL  dataa_exp_all_one_ff_p1        :       STD_LOGIC
65 
         -- synopsys translate_off
66 
          := '0'
67 
         -- synopsys translate_on
68 
         ;
69 
         SIGNAL  wire_dataa_exp_all_one_ff_p1_w_lg_q296w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
70 
         SIGNAL  wire_dataa_exp_all_one_ff_p1_w_lg_q291w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
71 
         SIGNAL  dataa_exp_not_zero_ff_p1       :       STD_LOGIC
72 
         -- synopsys translate_off
73 
          := '0'
74 
         -- synopsys translate_on
75 
         ;
76 
         SIGNAL  dataa_man_not_zero_ff_p1       :       STD_LOGIC
77 
         -- synopsys translate_off
78 
          := '0'
79 
         -- synopsys translate_on
80 
         ;
81 
         SIGNAL  wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
82 
         SIGNAL  wire_dataa_man_not_zero_ff_p1_w_lg_q290w       :       STD_LOGIC_VECTOR (0 DOWNTO 0);
83 
         SIGNAL  dataa_man_not_zero_ff_p2       :       STD_LOGIC
84 
         -- synopsys translate_off
85 
          := '0'
86 
         -- synopsys translate_on
87 
         ;
88 
         SIGNAL  datab_exp_all_one_ff_p1        :       STD_LOGIC
89 
         -- synopsys translate_off
90 
          := '0'
91 
         -- synopsys translate_on
92 
         ;
93 
         SIGNAL  wire_datab_exp_all_one_ff_p1_w_lg_q294w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
94 
         SIGNAL  wire_datab_exp_all_one_ff_p1_w_lg_q289w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
95 
         SIGNAL  datab_exp_not_zero_ff_p1       :       STD_LOGIC
96 
         -- synopsys translate_off
97 
          := '0'
98 
         -- synopsys translate_on
99 
         ;
100 
         SIGNAL  datab_man_not_zero_ff_p1       :       STD_LOGIC
101 
         -- synopsys translate_off
102 
          := '0'
103 
         -- synopsys translate_on
104 
         ;
105 
         SIGNAL  wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
106 
         SIGNAL  wire_datab_man_not_zero_ff_p1_w_lg_q288w       :       STD_LOGIC_VECTOR (0 DOWNTO 0);
107 
         SIGNAL  datab_man_not_zero_ff_p2       :       STD_LOGIC
108 
         -- synopsys translate_off
109 
          := '0'
110 
         -- synopsys translate_on
111 
         ;
112 
         SIGNAL  delay_exp2_bias        :       STD_LOGIC_VECTOR(9 DOWNTO 0)
113 
         -- synopsys translate_off
114 
          := (OTHERS => '0')
115 
         -- synopsys translate_on
116 
         ;
117 
         SIGNAL  delay_exp3_bias        :       STD_LOGIC_VECTOR(9 DOWNTO 0)
118 
         -- synopsys translate_off
119 
          := (OTHERS => '0')
120 
         -- synopsys translate_on
121 
         ;
122 
         SIGNAL  delay_exp_bias :       STD_LOGIC_VECTOR(9 DOWNTO 0)
123 
         -- synopsys translate_off
124 
          := (OTHERS => '0')
125 
         -- synopsys translate_on
126 
         ;
127 
         SIGNAL  delay_man_product_msb  :       STD_LOGIC
128 
         -- synopsys translate_off
129 
          := '0'
130 
         -- synopsys translate_on
131 
         ;
132 
         SIGNAL  wire_delay_man_product_msb_w_lg_q393w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
133 
         SIGNAL  wire_delay_man_product_msb_w_lg_q395w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
134 
         SIGNAL  delay_man_product_msb_p0       :       STD_LOGIC
135 
         -- synopsys translate_off
136 
          := '0'
137 
         -- synopsys translate_on
138 
         ;
139 
         SIGNAL  exp_add_p1     :       STD_LOGIC_VECTOR(8 DOWNTO 0)
140 
         -- synopsys translate_off
141 
          := (OTHERS => '0')
142 
         -- synopsys translate_on
143 
         ;
144 
         SIGNAL  exp_result_ff  :       STD_LOGIC_VECTOR(7 DOWNTO 0)
145 
         -- synopsys translate_off
146 
          := (OTHERS => '0')
147 
         -- synopsys translate_on
148 
         ;
149 
         SIGNAL  input_is_infinity_dffe_0       :       STD_LOGIC
150 
         -- synopsys translate_off
151 
          := '0'
152 
         -- synopsys translate_on
153 
         ;
154 
         SIGNAL  input_is_infinity_dffe_1       :       STD_LOGIC
155 
         -- synopsys translate_off
156 
          := '0'
157 
         -- synopsys translate_on
158 
         ;
159 
         SIGNAL  input_is_infinity_ff1  :       STD_LOGIC
160 
         -- synopsys translate_off
161 
          := '0'
162 
         -- synopsys translate_on
163 
         ;
164 
         SIGNAL  input_is_infinity_ff2  :       STD_LOGIC
165 
         -- synopsys translate_off
166 
          := '0'
167 
         -- synopsys translate_on
168 
         ;
169 
         SIGNAL  wire_input_is_infinity_ff2_w_lg_q464w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
170 
         SIGNAL  wire_input_is_infinity_ff2_w_lg_q466w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
171 
         SIGNAL  input_is_nan_dffe_0    :       STD_LOGIC
172 
         -- synopsys translate_off
173 
          := '0'
174 
         -- synopsys translate_on
175 
         ;
176 
         SIGNAL  input_is_nan_dffe_1    :       STD_LOGIC
177 
         -- synopsys translate_off
178 
          := '0'
179 
         -- synopsys translate_on
180 
         ;
181 
         SIGNAL  input_is_nan_ff1       :       STD_LOGIC
182 
         -- synopsys translate_off
183 
          := '0'
184 
         -- synopsys translate_on
185 
         ;
186 
         SIGNAL  input_is_nan_ff2       :       STD_LOGIC
187 
         -- synopsys translate_off
188 
          := '0'
189 
         -- synopsys translate_on
190 
         ;
191 
         SIGNAL  wire_input_is_nan_ff2_w_lg_q474w       :       STD_LOGIC_VECTOR (0 DOWNTO 0);
192 
         SIGNAL  input_not_zero_dffe_0  :       STD_LOGIC
193 
         -- synopsys translate_off
194 
          := '0'
195 
         -- synopsys translate_on
196 
         ;
197 
         SIGNAL  input_not_zero_dffe_1  :       STD_LOGIC
198 
         -- synopsys translate_off
199 
          := '0'
200 
         -- synopsys translate_on
201 
         ;
202 
         SIGNAL  input_not_zero_ff1     :       STD_LOGIC
203 
         -- synopsys translate_off
204 
          := '0'
205 
         -- synopsys translate_on
206 
         ;
207 
         SIGNAL  input_not_zero_ff2     :       STD_LOGIC
208 
         -- synopsys translate_off
209 
          := '0'
210 
         -- synopsys translate_on
211 
         ;
212 
         SIGNAL  wire_input_not_zero_ff2_w_lg_q463w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
213 
         SIGNAL  lsb_dffe       :       STD_LOGIC
214 
         -- synopsys translate_off
215 
          := '0'
216 
         -- synopsys translate_on
217 
         ;
218 
         SIGNAL  man_result_ff  :       STD_LOGIC_VECTOR(22 DOWNTO 0)
219 
         -- synopsys translate_off
220 
          := (OTHERS => '0')
221 
         -- synopsys translate_on
222 
         ;
223 
         SIGNAL  man_round_p    :       STD_LOGIC_VECTOR(23 DOWNTO 0)
224 
         -- synopsys translate_off
225 
          := (OTHERS => '0')
226 
         -- synopsys translate_on
227 
         ;
228 
         SIGNAL  man_round_p2   :       STD_LOGIC_VECTOR(24 DOWNTO 0)
229 
         -- synopsys translate_off
230 
          := (OTHERS => '0')
231 
         -- synopsys translate_on
232 
         ;
233 
         SIGNAL  wire_man_round_p2_w_lg_w_q_range399w400w       :       STD_LOGIC_VECTOR (23 DOWNTO 0);
234 
         SIGNAL  wire_man_round_p2_w_lg_w_q_range396w397w       :       STD_LOGIC_VECTOR (23 DOWNTO 0);
235 
         SIGNAL  wire_man_round_p2_w_lg_w_q_range391w398w       :       STD_LOGIC_VECTOR (0 DOWNTO 0);
236 
         SIGNAL  wire_man_round_p2_w_q_range399w        :       STD_LOGIC_VECTOR (23 DOWNTO 0);
237 
         SIGNAL  wire_man_round_p2_w_q_range396w        :       STD_LOGIC_VECTOR (23 DOWNTO 0);
238 
         SIGNAL  wire_man_round_p2_w_q_range391w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
239 
         SIGNAL  nan_ff :       STD_LOGIC
240 
         -- synopsys translate_off
241 
          := '0'
242 
         -- synopsys translate_on
243 
         ;
244 
         SIGNAL  overflow_ff    :       STD_LOGIC
245 
         -- synopsys translate_off
246 
          := '0'
247 
         -- synopsys translate_on
248 
         ;
249 
         SIGNAL  round_dffe     :       STD_LOGIC
250 
         -- synopsys translate_off
251 
          := '0'
252 
         -- synopsys translate_on
253 
         ;
254 
         SIGNAL  sign_node_ff0  :       STD_LOGIC
255 
         -- synopsys translate_off
256 
          := '0'
257 
         -- synopsys translate_on
258 
         ;
259 
         SIGNAL  sign_node_ff1  :       STD_LOGIC
260 
         -- synopsys translate_off
261 
          := '0'
262 
         -- synopsys translate_on
263 
         ;
264 
         SIGNAL  sign_node_ff2  :       STD_LOGIC
265 
         -- synopsys translate_off
266 
          := '0'
267 
         -- synopsys translate_on
268 
         ;
269 
         SIGNAL  sign_node_ff3  :       STD_LOGIC
270 
         -- synopsys translate_off
271 
          := '0'
272 
         -- synopsys translate_on
273 
         ;
274 
         SIGNAL  sign_node_ff4  :       STD_LOGIC
275 
         -- synopsys translate_off
276 
          := '0'
277 
         -- synopsys translate_on
278 
         ;
279 
         SIGNAL  sign_node_ff5  :       STD_LOGIC
280 
         -- synopsys translate_off
281 
          := '0'
282 
         -- synopsys translate_on
283 
         ;
284 
         SIGNAL  sticky_dffe    :       STD_LOGIC
285 
         -- synopsys translate_off
286 
          := '0'
287 
         -- synopsys translate_on
288 
         ;
289 
         SIGNAL  underflow_ff   :       STD_LOGIC
290 
         -- synopsys translate_off
291 
          := '0'
292 
         -- synopsys translate_on
293 
         ;
294 
         SIGNAL  zero_ff        :       STD_LOGIC
295 
         -- synopsys translate_off
296 
          := '0'
297 
         -- synopsys translate_on
298 
         ;
299 
         SIGNAL  wire_gnd       :       STD_LOGIC;
300 
         SIGNAL  wire_exp_add_adder_dataa       :       STD_LOGIC_VECTOR (8 DOWNTO 0);
301 
         SIGNAL  wire_exp_add_adder_datab       :       STD_LOGIC_VECTOR (8 DOWNTO 0);
302 
         SIGNAL  wire_exp_add_adder_result      :       STD_LOGIC_VECTOR (8 DOWNTO 0);
303 
         SIGNAL  wire_exp_adj_adder_w_lg_w_lg_w_result_range454w455w456w        :       STD_LOGIC_VECTOR (7 DOWNTO 0);
304 
         SIGNAL  wire_exp_adj_adder_w_lg_w_result_range454w455w :       STD_LOGIC_VECTOR (7 DOWNTO 0);
305 
         SIGNAL  wire_exp_adj_adder_w_lg_w_result_range427w452w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
306 
         SIGNAL  wire_exp_adj_adder_result      :       STD_LOGIC_VECTOR (9 DOWNTO 0);
307 
         SIGNAL  wire_exp_adj_adder_w_result_range405w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
308 
         SIGNAL  wire_exp_adj_adder_w_result_range408w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
309 
         SIGNAL  wire_exp_adj_adder_w_result_range411w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
310 
         SIGNAL  wire_exp_adj_adder_w_result_range414w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
311 
         SIGNAL  wire_exp_adj_adder_w_result_range417w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
312 
         SIGNAL  wire_exp_adj_adder_w_result_range420w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
313 
         SIGNAL  wire_exp_adj_adder_w_result_range454w  :       STD_LOGIC_VECTOR (7 DOWNTO 0);
314 
         SIGNAL  wire_exp_adj_adder_w_result_range423w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
315 
         SIGNAL  wire_exp_adj_adder_w_result_range426w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
316 
         SIGNAL  wire_exp_adj_adder_w_result_range427w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
317 
         SIGNAL  wire_exp_bias_subtr_dataa      :       STD_LOGIC_VECTOR (9 DOWNTO 0);
318 
         SIGNAL  wire_exp_bias_subtr_datab      :       STD_LOGIC_VECTOR (9 DOWNTO 0);
319 
         SIGNAL  wire_exp_bias_subtr_result     :       STD_LOGIC_VECTOR (9 DOWNTO 0);
320 
         SIGNAL  wire_man_round_adder_dataa     :       STD_LOGIC_VECTOR (24 DOWNTO 0);
321 
         SIGNAL  wire_man_round_adder_datab     :       STD_LOGIC_VECTOR (24 DOWNTO 0);
322 
         SIGNAL  wire_man_round_adder_result    :       STD_LOGIC_VECTOR (24 DOWNTO 0);
323 
         SIGNAL  wire_man_product2_mult_w_lg_w_result_range302w303w     :       STD_LOGIC_VECTOR (24 DOWNTO 0);
324 
         SIGNAL  wire_man_product2_mult_w_lg_w_result_range299w300w     :       STD_LOGIC_VECTOR (24 DOWNTO 0);
325 
         SIGNAL  wire_man_product2_mult_w_lg_w_result_range298w373w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
326 
         SIGNAL  wire_man_product2_mult_w_lg_w_result_range298w301w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
327 
         SIGNAL  wire_man_product2_mult_dataa   :       STD_LOGIC_VECTOR (23 DOWNTO 0);
328 
         SIGNAL  wire_man_product2_mult_datab   :       STD_LOGIC_VECTOR (23 DOWNTO 0);
329 
         SIGNAL  wire_man_product2_mult_result  :       STD_LOGIC_VECTOR (47 DOWNTO 0);
330 
         SIGNAL  wire_man_product2_mult_w_result_range335w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
331 
         SIGNAL  wire_man_product2_mult_w_result_range338w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
332 
         SIGNAL  wire_man_product2_mult_w_result_range341w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
333 
         SIGNAL  wire_man_product2_mult_w_result_range344w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
334 
         SIGNAL  wire_man_product2_mult_w_result_range347w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
335 
         SIGNAL  wire_man_product2_mult_w_result_range350w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
336 
         SIGNAL  wire_man_product2_mult_w_result_range353w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
337 
         SIGNAL  wire_man_product2_mult_w_result_range356w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
338 
         SIGNAL  wire_man_product2_mult_w_result_range359w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
339 
         SIGNAL  wire_man_product2_mult_w_result_range362w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
340 
         SIGNAL  wire_man_product2_mult_w_result_range308w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
341 
         SIGNAL  wire_man_product2_mult_w_result_range365w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
342 
         SIGNAL  wire_man_product2_mult_w_result_range368w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
343 
         SIGNAL  wire_man_product2_mult_w_result_range371w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
344 
         SIGNAL  wire_man_product2_mult_w_result_range311w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
345 
         SIGNAL  wire_man_product2_mult_w_result_range314w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
346 
         SIGNAL  wire_man_product2_mult_w_result_range302w      :       STD_LOGIC_VECTOR (24 DOWNTO 0);
347 
         SIGNAL  wire_man_product2_mult_w_result_range299w      :       STD_LOGIC_VECTOR (24 DOWNTO 0);
348 
         SIGNAL  wire_man_product2_mult_w_result_range298w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
349 
         SIGNAL  wire_man_product2_mult_w_result_range317w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
350 
         SIGNAL  wire_man_product2_mult_w_result_range320w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
351 
         SIGNAL  wire_man_product2_mult_w_result_range323w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
352 
         SIGNAL  wire_man_product2_mult_w_result_range326w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
353 
         SIGNAL  wire_man_product2_mult_w_result_range329w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
354 
         SIGNAL  wire_man_product2_mult_w_result_range332w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
355 
         SIGNAL  wire_w_lg_w_lg_w478w479w480w   :       STD_LOGIC_VECTOR (21 DOWNTO 0);
356 
         SIGNAL  wire_w_lg_w478w479w    :       STD_LOGIC_VECTOR (21 DOWNTO 0);
357 
         SIGNAL  wire_w_lg_w469w470w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
358 
         SIGNAL  wire_w478w     :       STD_LOGIC_VECTOR (21 DOWNTO 0);
359 
         SIGNAL  wire_w469w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
360 
         SIGNAL  wire_w_lg_w_lg_w_delay_round_wire_range475w476w477w    :       STD_LOGIC_VECTOR (21 DOWNTO 0);
361 
         SIGNAL  wire_w_lg_w_lg_w_delay_round_wire_range461w467w468w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
362 
         SIGNAL  wire_w_lg_inf_num459w  :       STD_LOGIC_VECTOR (7 DOWNTO 0);
363 
         SIGNAL  wire_w_lg_w_dataa_range81w88w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
364 
         SIGNAL  wire_w_lg_w_dataa_range91w98w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
365 
         SIGNAL  wire_w_lg_w_dataa_range101w108w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
366 
         SIGNAL  wire_w_lg_w_dataa_range111w118w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
367 
         SIGNAL  wire_w_lg_w_dataa_range121w128w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
368 
         SIGNAL  wire_w_lg_w_dataa_range131w138w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
369 
         SIGNAL  wire_w_lg_w_dataa_range141w148w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
370 
         SIGNAL  wire_w_lg_w_datab_range84w90w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
371 
         SIGNAL  wire_w_lg_w_datab_range94w100w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
372 
         SIGNAL  wire_w_lg_w_datab_range104w110w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
373 
         SIGNAL  wire_w_lg_w_datab_range114w120w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
374 
         SIGNAL  wire_w_lg_w_datab_range124w130w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
375 
         SIGNAL  wire_w_lg_w_datab_range134w140w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
376 
         SIGNAL  wire_w_lg_w_datab_range144w150w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
377 
         SIGNAL  wire_w_lg_w_delay_round_wire_range475w476w     :       STD_LOGIC_VECTOR (21 DOWNTO 0);
378 
         SIGNAL  wire_w_lg_w_delay_round_wire_range461w467w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
379 
         SIGNAL  wire_w_lg_w_result_exp_all_one_range403w407w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
380 
         SIGNAL  wire_w_lg_w_result_exp_all_one_range406w410w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
381 
         SIGNAL  wire_w_lg_w_result_exp_all_one_range409w413w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
382 
         SIGNAL  wire_w_lg_w_result_exp_all_one_range412w416w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
383 
         SIGNAL  wire_w_lg_w_result_exp_all_one_range415w419w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
384 
         SIGNAL  wire_w_lg_w_result_exp_all_one_range418w422w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
385 
         SIGNAL  wire_w_lg_w_result_exp_all_one_range421w425w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
386 
         SIGNAL  wire_w_lg_exp_is_inf465w       :       STD_LOGIC_VECTOR (0 DOWNTO 0);
387 
         SIGNAL  wire_w_lg_exp_is_zero453w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
388 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range449w451w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
389 
         SIGNAL  wire_w_lg_w_lg_w469w470w471w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
390 
         SIGNAL  wire_w_lg_w_lg_inf_num459w460w :       STD_LOGIC_VECTOR (7 DOWNTO 0);
391 
         SIGNAL  wire_w_lg_w_lg_w_lg_w469w470w471w472w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
392 
         SIGNAL  wire_w_lg_w_lg_exp_is_inf457w458w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
393 
         SIGNAL  wire_w_lg_exp_is_inf457w       :       STD_LOGIC_VECTOR (0 DOWNTO 0);
394 
         SIGNAL  wire_w_lg_exp_is_zero489w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
395 
         SIGNAL  wire_w_lg_w_dataa_range211w213w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
396 
         SIGNAL  wire_w_lg_w_dataa_range221w223w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
397 
         SIGNAL  wire_w_lg_w_dataa_range227w229w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
398 
         SIGNAL  wire_w_lg_w_dataa_range233w235w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
399 
         SIGNAL  wire_w_lg_w_dataa_range239w241w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
400 
         SIGNAL  wire_w_lg_w_dataa_range245w247w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
401 
         SIGNAL  wire_w_lg_w_dataa_range251w253w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
402 
         SIGNAL  wire_w_lg_w_dataa_range257w259w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
403 
         SIGNAL  wire_w_lg_w_dataa_range263w265w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
404 
         SIGNAL  wire_w_lg_w_dataa_range157w159w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
405 
         SIGNAL  wire_w_lg_w_dataa_range269w271w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
406 
         SIGNAL  wire_w_lg_w_dataa_range275w277w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
407 
         SIGNAL  wire_w_lg_w_dataa_range281w283w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
408 
         SIGNAL  wire_w_lg_w_dataa_range81w83w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
409 
         SIGNAL  wire_w_lg_w_dataa_range91w93w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
410 
         SIGNAL  wire_w_lg_w_dataa_range101w103w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
411 
         SIGNAL  wire_w_lg_w_dataa_range111w113w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
412 
         SIGNAL  wire_w_lg_w_dataa_range121w123w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
413 
         SIGNAL  wire_w_lg_w_dataa_range131w133w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
414 
         SIGNAL  wire_w_lg_w_dataa_range163w165w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
415 
         SIGNAL  wire_w_lg_w_dataa_range141w143w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
416 
         SIGNAL  wire_w_lg_w_dataa_range169w171w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
417 
         SIGNAL  wire_w_lg_w_dataa_range175w177w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
418 
         SIGNAL  wire_w_lg_w_dataa_range181w183w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
419 
         SIGNAL  wire_w_lg_w_dataa_range187w189w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
420 
         SIGNAL  wire_w_lg_w_dataa_range193w195w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
421 
         SIGNAL  wire_w_lg_w_dataa_range199w201w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
422 
         SIGNAL  wire_w_lg_w_dataa_range205w207w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
423 
         SIGNAL  wire_w_lg_w_datab_range214w216w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
424 
         SIGNAL  wire_w_lg_w_datab_range224w226w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
425 
         SIGNAL  wire_w_lg_w_datab_range230w232w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
426 
         SIGNAL  wire_w_lg_w_datab_range236w238w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
427 
         SIGNAL  wire_w_lg_w_datab_range242w244w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
428 
         SIGNAL  wire_w_lg_w_datab_range248w250w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
429 
         SIGNAL  wire_w_lg_w_datab_range254w256w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
430 
         SIGNAL  wire_w_lg_w_datab_range260w262w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
431 
         SIGNAL  wire_w_lg_w_datab_range266w268w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
432 
         SIGNAL  wire_w_lg_w_datab_range160w162w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
433 
         SIGNAL  wire_w_lg_w_datab_range272w274w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
434 
         SIGNAL  wire_w_lg_w_datab_range278w280w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
435 
         SIGNAL  wire_w_lg_w_datab_range284w286w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
436 
         SIGNAL  wire_w_lg_w_datab_range84w86w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
437 
         SIGNAL  wire_w_lg_w_datab_range94w96w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
438 
         SIGNAL  wire_w_lg_w_datab_range104w106w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
439 
         SIGNAL  wire_w_lg_w_datab_range114w116w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
440 
         SIGNAL  wire_w_lg_w_datab_range124w126w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
441 
         SIGNAL  wire_w_lg_w_datab_range134w136w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
442 
         SIGNAL  wire_w_lg_w_datab_range166w168w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
443 
         SIGNAL  wire_w_lg_w_datab_range144w146w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
444 
         SIGNAL  wire_w_lg_w_datab_range172w174w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
445 
         SIGNAL  wire_w_lg_w_datab_range178w180w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
446 
         SIGNAL  wire_w_lg_w_datab_range184w186w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
447 
         SIGNAL  wire_w_lg_w_datab_range190w192w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
448 
         SIGNAL  wire_w_lg_w_datab_range196w198w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
449 
         SIGNAL  wire_w_lg_w_datab_range202w204w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
450 
         SIGNAL  wire_w_lg_w_datab_range208w210w        :       STD_LOGIC_VECTOR (0 DOWNTO 0);
451 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range433w436w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
452 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range435w438w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
453 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range437w440w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
454 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range439w442w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
455 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range441w444w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
456 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range443w446w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
457 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range445w448w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
458 
         SIGNAL  wire_w_lg_w_result_exp_not_zero_range447w450w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
459 
         SIGNAL  wire_w_lg_w_sticky_bit_range306w310w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
460 
         SIGNAL  wire_w_lg_w_sticky_bit_range336w340w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
461 
         SIGNAL  wire_w_lg_w_sticky_bit_range339w343w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
462 
         SIGNAL  wire_w_lg_w_sticky_bit_range342w346w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
463 
         SIGNAL  wire_w_lg_w_sticky_bit_range345w349w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
464 
         SIGNAL  wire_w_lg_w_sticky_bit_range348w352w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
465 
         SIGNAL  wire_w_lg_w_sticky_bit_range351w355w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
466 
         SIGNAL  wire_w_lg_w_sticky_bit_range354w358w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
467 
         SIGNAL  wire_w_lg_w_sticky_bit_range357w361w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
468 
         SIGNAL  wire_w_lg_w_sticky_bit_range360w364w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
469 
         SIGNAL  wire_w_lg_w_sticky_bit_range363w367w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
470 
         SIGNAL  wire_w_lg_w_sticky_bit_range309w313w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
471 
         SIGNAL  wire_w_lg_w_sticky_bit_range366w370w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
472 
         SIGNAL  wire_w_lg_w_sticky_bit_range369w374w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
473 
         SIGNAL  wire_w_lg_w_sticky_bit_range312w316w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
474 
         SIGNAL  wire_w_lg_w_sticky_bit_range315w319w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
475 
         SIGNAL  wire_w_lg_w_sticky_bit_range318w322w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
476 
         SIGNAL  wire_w_lg_w_sticky_bit_range321w325w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
477 
         SIGNAL  wire_w_lg_w_sticky_bit_range324w328w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
478 
         SIGNAL  wire_w_lg_w_sticky_bit_range327w331w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
479 
         SIGNAL  wire_w_lg_w_sticky_bit_range330w334w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
480 
         SIGNAL  wire_w_lg_w_sticky_bit_range333w337w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
481 
         SIGNAL  bias : STD_LOGIC_VECTOR (9 DOWNTO 0);
482 
         SIGNAL  dataa_exp_all_one :    STD_LOGIC_VECTOR (7 DOWNTO 0);
483 
         SIGNAL  dataa_exp_not_zero :   STD_LOGIC_VECTOR (7 DOWNTO 0);
484 
         SIGNAL  dataa_man_not_zero :   STD_LOGIC_VECTOR (22 DOWNTO 0);
485 
         SIGNAL  datab_exp_all_one :    STD_LOGIC_VECTOR (7 DOWNTO 0);
486 
         SIGNAL  datab_exp_not_zero :   STD_LOGIC_VECTOR (7 DOWNTO 0);
487 
         SIGNAL  datab_man_not_zero :   STD_LOGIC_VECTOR (22 DOWNTO 0);
488 
         SIGNAL  delay_round_wire :     STD_LOGIC_VECTOR (23 DOWNTO 0);
489 
         SIGNAL  exp_is_inf :   STD_LOGIC;
490 
         SIGNAL  exp_is_zero :  STD_LOGIC;
491 
         SIGNAL  expmod :       STD_LOGIC_VECTOR (9 DOWNTO 0);
492 
         SIGNAL  inf_num :      STD_LOGIC_VECTOR (7 DOWNTO 0);
493 
         SIGNAL  lsb_bit :      STD_LOGIC;
494 
         SIGNAL  man_shift_full :       STD_LOGIC_VECTOR (24 DOWNTO 0);
495 
         SIGNAL  result_exp_all_one :   STD_LOGIC_VECTOR (7 DOWNTO 0);
496 
         SIGNAL  result_exp_not_zero :  STD_LOGIC_VECTOR (8 DOWNTO 0);
497 
         SIGNAL  round_bit :    STD_LOGIC;
498 
         SIGNAL  round_carry :  STD_LOGIC;
499 
         SIGNAL  sticky_bit :   STD_LOGIC_VECTOR (22 DOWNTO 0);
500 
         SIGNAL  wire_w_dataa_range211w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
501 
         SIGNAL  wire_w_dataa_range221w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
502 
         SIGNAL  wire_w_dataa_range227w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
503 
         SIGNAL  wire_w_dataa_range233w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
504 
         SIGNAL  wire_w_dataa_range239w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
505 
         SIGNAL  wire_w_dataa_range245w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
506 
         SIGNAL  wire_w_dataa_range251w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
507 
         SIGNAL  wire_w_dataa_range257w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
508 
         SIGNAL  wire_w_dataa_range263w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
509 
         SIGNAL  wire_w_dataa_range157w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
510 
         SIGNAL  wire_w_dataa_range269w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
511 
         SIGNAL  wire_w_dataa_range275w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
512 
         SIGNAL  wire_w_dataa_range281w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
513 
         SIGNAL  wire_w_dataa_range81w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
514 
         SIGNAL  wire_w_dataa_range91w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
515 
         SIGNAL  wire_w_dataa_range101w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
516 
         SIGNAL  wire_w_dataa_range111w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
517 
         SIGNAL  wire_w_dataa_range121w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
518 
         SIGNAL  wire_w_dataa_range131w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
519 
         SIGNAL  wire_w_dataa_range163w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
520 
         SIGNAL  wire_w_dataa_range141w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
521 
         SIGNAL  wire_w_dataa_range169w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
522 
         SIGNAL  wire_w_dataa_range175w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
523 
         SIGNAL  wire_w_dataa_range181w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
524 
         SIGNAL  wire_w_dataa_range187w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
525 
         SIGNAL  wire_w_dataa_range193w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
526 
         SIGNAL  wire_w_dataa_range199w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
527 
         SIGNAL  wire_w_dataa_range205w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
528 
         SIGNAL  wire_w_dataa_exp_all_one_range77w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
529 
         SIGNAL  wire_w_dataa_exp_all_one_range87w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
530 
         SIGNAL  wire_w_dataa_exp_all_one_range97w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
531 
         SIGNAL  wire_w_dataa_exp_all_one_range107w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
532 
         SIGNAL  wire_w_dataa_exp_all_one_range117w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
533 
         SIGNAL  wire_w_dataa_exp_all_one_range127w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
534 
         SIGNAL  wire_w_dataa_exp_all_one_range137w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
535 
         SIGNAL  wire_w_dataa_exp_not_zero_range72w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
536 
         SIGNAL  wire_w_dataa_exp_not_zero_range82w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
537 
         SIGNAL  wire_w_dataa_exp_not_zero_range92w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
538 
         SIGNAL  wire_w_dataa_exp_not_zero_range102w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
539 
         SIGNAL  wire_w_dataa_exp_not_zero_range112w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
540 
         SIGNAL  wire_w_dataa_exp_not_zero_range122w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
541 
         SIGNAL  wire_w_dataa_exp_not_zero_range132w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
542 
         SIGNAL  wire_w_dataa_man_not_zero_range152w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
543 
         SIGNAL  wire_w_dataa_man_not_zero_range218w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
544 
         SIGNAL  wire_w_dataa_man_not_zero_range222w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
545 
         SIGNAL  wire_w_dataa_man_not_zero_range228w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
546 
         SIGNAL  wire_w_dataa_man_not_zero_range234w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
547 
         SIGNAL  wire_w_dataa_man_not_zero_range240w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
548 
         SIGNAL  wire_w_dataa_man_not_zero_range246w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
549 
         SIGNAL  wire_w_dataa_man_not_zero_range252w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
550 
         SIGNAL  wire_w_dataa_man_not_zero_range258w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
551 
         SIGNAL  wire_w_dataa_man_not_zero_range264w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
552 
         SIGNAL  wire_w_dataa_man_not_zero_range158w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
553 
         SIGNAL  wire_w_dataa_man_not_zero_range270w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
554 
         SIGNAL  wire_w_dataa_man_not_zero_range276w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
555 
         SIGNAL  wire_w_dataa_man_not_zero_range164w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
556 
         SIGNAL  wire_w_dataa_man_not_zero_range170w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
557 
         SIGNAL  wire_w_dataa_man_not_zero_range176w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
558 
         SIGNAL  wire_w_dataa_man_not_zero_range182w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
559 
         SIGNAL  wire_w_dataa_man_not_zero_range188w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
560 
         SIGNAL  wire_w_dataa_man_not_zero_range194w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
561 
         SIGNAL  wire_w_dataa_man_not_zero_range200w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
562 
         SIGNAL  wire_w_dataa_man_not_zero_range206w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
563 
         SIGNAL  wire_w_datab_range214w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
564 
         SIGNAL  wire_w_datab_range224w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
565 
         SIGNAL  wire_w_datab_range230w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
566 
         SIGNAL  wire_w_datab_range236w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
567 
         SIGNAL  wire_w_datab_range242w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
568 
         SIGNAL  wire_w_datab_range248w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
569 
         SIGNAL  wire_w_datab_range254w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
570 
         SIGNAL  wire_w_datab_range260w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
571 
         SIGNAL  wire_w_datab_range266w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
572 
         SIGNAL  wire_w_datab_range160w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
573 
         SIGNAL  wire_w_datab_range272w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
574 
         SIGNAL  wire_w_datab_range278w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
575 
         SIGNAL  wire_w_datab_range284w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
576 
         SIGNAL  wire_w_datab_range84w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
577 
         SIGNAL  wire_w_datab_range94w  :       STD_LOGIC_VECTOR (0 DOWNTO 0);
578 
         SIGNAL  wire_w_datab_range104w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
579 
         SIGNAL  wire_w_datab_range114w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
580 
         SIGNAL  wire_w_datab_range124w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
581 
         SIGNAL  wire_w_datab_range134w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
582 
         SIGNAL  wire_w_datab_range166w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
583 
         SIGNAL  wire_w_datab_range144w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
584 
         SIGNAL  wire_w_datab_range172w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
585 
         SIGNAL  wire_w_datab_range178w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
586 
         SIGNAL  wire_w_datab_range184w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
587 
         SIGNAL  wire_w_datab_range190w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
588 
         SIGNAL  wire_w_datab_range196w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
589 
         SIGNAL  wire_w_datab_range202w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
590 
         SIGNAL  wire_w_datab_range208w :       STD_LOGIC_VECTOR (0 DOWNTO 0);
591 
         SIGNAL  wire_w_datab_exp_all_one_range79w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
592 
         SIGNAL  wire_w_datab_exp_all_one_range89w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
593 
         SIGNAL  wire_w_datab_exp_all_one_range99w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
594 
         SIGNAL  wire_w_datab_exp_all_one_range109w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
595 
         SIGNAL  wire_w_datab_exp_all_one_range119w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
596 
         SIGNAL  wire_w_datab_exp_all_one_range129w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
597 
         SIGNAL  wire_w_datab_exp_all_one_range139w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
598 
         SIGNAL  wire_w_datab_exp_not_zero_range75w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
599 
         SIGNAL  wire_w_datab_exp_not_zero_range85w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
600 
         SIGNAL  wire_w_datab_exp_not_zero_range95w     :       STD_LOGIC_VECTOR (0 DOWNTO 0);
601 
         SIGNAL  wire_w_datab_exp_not_zero_range105w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
602 
         SIGNAL  wire_w_datab_exp_not_zero_range115w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
603 
         SIGNAL  wire_w_datab_exp_not_zero_range125w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
604 
         SIGNAL  wire_w_datab_exp_not_zero_range135w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
605 
         SIGNAL  wire_w_datab_man_not_zero_range155w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
606 
         SIGNAL  wire_w_datab_man_not_zero_range220w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
607 
         SIGNAL  wire_w_datab_man_not_zero_range225w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
608 
         SIGNAL  wire_w_datab_man_not_zero_range231w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
609 
         SIGNAL  wire_w_datab_man_not_zero_range237w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
610 
         SIGNAL  wire_w_datab_man_not_zero_range243w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
611 
         SIGNAL  wire_w_datab_man_not_zero_range249w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
612 
         SIGNAL  wire_w_datab_man_not_zero_range255w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
613 
         SIGNAL  wire_w_datab_man_not_zero_range261w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
614 
         SIGNAL  wire_w_datab_man_not_zero_range267w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
615 
         SIGNAL  wire_w_datab_man_not_zero_range161w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
616 
         SIGNAL  wire_w_datab_man_not_zero_range273w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
617 
         SIGNAL  wire_w_datab_man_not_zero_range279w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
618 
         SIGNAL  wire_w_datab_man_not_zero_range167w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
619 
         SIGNAL  wire_w_datab_man_not_zero_range173w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
620 
         SIGNAL  wire_w_datab_man_not_zero_range179w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
621 
         SIGNAL  wire_w_datab_man_not_zero_range185w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
622 
         SIGNAL  wire_w_datab_man_not_zero_range191w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
623 
         SIGNAL  wire_w_datab_man_not_zero_range197w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
624 
         SIGNAL  wire_w_datab_man_not_zero_range203w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
625 
         SIGNAL  wire_w_datab_man_not_zero_range209w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
626 
         SIGNAL  wire_w_delay_round_wire_range475w      :       STD_LOGIC_VECTOR (21 DOWNTO 0);
627 
         SIGNAL  wire_w_delay_round_wire_range461w      :       STD_LOGIC_VECTOR (0 DOWNTO 0);
628 
         SIGNAL  wire_w_man_shift_full_range379w        :       STD_LOGIC_VECTOR (23 DOWNTO 0);
629 
         SIGNAL  wire_w_result_exp_all_one_range403w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
630 
         SIGNAL  wire_w_result_exp_all_one_range406w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
631 
         SIGNAL  wire_w_result_exp_all_one_range409w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
632 
         SIGNAL  wire_w_result_exp_all_one_range412w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
633 
         SIGNAL  wire_w_result_exp_all_one_range415w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
634 
         SIGNAL  wire_w_result_exp_all_one_range418w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
635 
         SIGNAL  wire_w_result_exp_all_one_range421w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
636 
         SIGNAL  wire_w_result_exp_not_zero_range433w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
637 
         SIGNAL  wire_w_result_exp_not_zero_range435w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
638 
         SIGNAL  wire_w_result_exp_not_zero_range437w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
639 
         SIGNAL  wire_w_result_exp_not_zero_range439w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
640 
         SIGNAL  wire_w_result_exp_not_zero_range441w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
641 
         SIGNAL  wire_w_result_exp_not_zero_range443w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
642 
         SIGNAL  wire_w_result_exp_not_zero_range445w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
643 
         SIGNAL  wire_w_result_exp_not_zero_range447w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
644 
         SIGNAL  wire_w_result_exp_not_zero_range449w   :       STD_LOGIC_VECTOR (0 DOWNTO 0);
645 
         SIGNAL  wire_w_sticky_bit_range306w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
646 
         SIGNAL  wire_w_sticky_bit_range336w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
647 
         SIGNAL  wire_w_sticky_bit_range339w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
648 
         SIGNAL  wire_w_sticky_bit_range342w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
649 
         SIGNAL  wire_w_sticky_bit_range345w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
650 
         SIGNAL  wire_w_sticky_bit_range348w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
651 
         SIGNAL  wire_w_sticky_bit_range351w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
652 
         SIGNAL  wire_w_sticky_bit_range354w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
653 
         SIGNAL  wire_w_sticky_bit_range357w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
654 
         SIGNAL  wire_w_sticky_bit_range360w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
655 
         SIGNAL  wire_w_sticky_bit_range363w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
656 
         SIGNAL  wire_w_sticky_bit_range309w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
657 
         SIGNAL  wire_w_sticky_bit_range366w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
658 
         SIGNAL  wire_w_sticky_bit_range369w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
659 
         SIGNAL  wire_w_sticky_bit_range312w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
660 
         SIGNAL  wire_w_sticky_bit_range315w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
661 
         SIGNAL  wire_w_sticky_bit_range318w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
662 
         SIGNAL  wire_w_sticky_bit_range321w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
663 
         SIGNAL  wire_w_sticky_bit_range324w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
664 
         SIGNAL  wire_w_sticky_bit_range327w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
665 
         SIGNAL  wire_w_sticky_bit_range330w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
666 
         SIGNAL  wire_w_sticky_bit_range333w    :       STD_LOGIC_VECTOR (0 DOWNTO 0);
667 
         COMPONENT  lpm_add_sub
668 
         GENERIC
669 
         (
670 
                LPM_DIRECTION   :       STRING := "DEFAULT";
671 
                LPM_PIPELINE    :       NATURAL := 0;
672 
                LPM_REPRESENTATION      :       STRING := "SIGNED";
673 
                LPM_WIDTH       :       NATURAL;
674 
                lpm_hint        :       STRING := "UNUSED";
675 
                lpm_type        :       STRING := "lpm_add_sub"
676 
         );
677 
         PORT
678 
         (
679 
                aclr    :       IN STD_LOGIC := '0';
680 
                add_sub :       IN STD_LOGIC := '1';
681 
                cin     :       IN STD_LOGIC := 'Z';
682 
                clken   :       IN STD_LOGIC := '1';
683 
                clock   :       IN STD_LOGIC := '0';
684 
                cout    :       OUT STD_LOGIC;
685 
                dataa   :       IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
686 
                datab   :       IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
687 
                overflow        :       OUT STD_LOGIC;
688 
                result  :       OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
689 
         );
690 
         END COMPONENT;
691 
         COMPONENT  lpm_mult
692 
         GENERIC
693 
         (
694 
                LPM_PIPELINE    :       NATURAL := 0;
695 
                LPM_REPRESENTATION      :       STRING := "UNSIGNED";
696 
                LPM_WIDTHA      :       NATURAL;
697 
                LPM_WIDTHB      :       NATURAL;
698 
                LPM_WIDTHP      :       NATURAL;
699 
                LPM_WIDTHS      :       NATURAL := 1;
700 
                lpm_hint        :       STRING := "UNUSED";
701 
                lpm_type        :       STRING := "lpm_mult"
702 
         );
703 
         PORT
704 
         (
705 
                aclr    :       IN STD_LOGIC := '0';
706 
                clken   :       IN STD_LOGIC := '1';
707 
                clock   :       IN STD_LOGIC := '0';
708 
                dataa   :       IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
709 
                datab   :       IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
710 
                result  :       OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
711 
                sum     :       IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
712 
         );
713 
         END COMPONENT;
714 
 BEGIN
715 
 
716 
        wire_gnd <= '0';
717 
        loop0 : FOR i IN 0 TO 21 GENERATE
718 
                wire_w_lg_w_lg_w478w479w480w(i) <= wire_w_lg_w478w479w(i) AND wire_input_is_nan_ff2_w_lg_q474w(0);
719 
        END GENERATE loop0;
720 
        loop1 : FOR i IN 0 TO 21 GENERATE
721 
                wire_w_lg_w478w479w(i) <= wire_w478w(i) AND wire_w_lg_exp_is_zero453w(0);
722 
        END GENERATE loop1;
723 
        wire_w_lg_w469w470w(0) <= wire_w469w(0) AND wire_w_lg_exp_is_zero453w(0);
724 
        loop2 : FOR i IN 0 TO 21 GENERATE
725 
                wire_w478w(i) <= wire_w_lg_w_lg_w_delay_round_wire_range475w476w477w(i) AND wire_w_lg_exp_is_inf465w(0);
726 
        END GENERATE loop2;
727 
        wire_w469w(0) <= wire_w_lg_w_lg_w_delay_round_wire_range461w467w468w(0) AND wire_w_lg_exp_is_inf465w(0);
728 
        loop3 : FOR i IN 0 TO 21 GENERATE
729 
                wire_w_lg_w_lg_w_delay_round_wire_range475w476w477w(i) <= wire_w_lg_w_delay_round_wire_range475w476w(i) AND wire_input_is_infinity_ff2_w_lg_q466w(0);
730 
        END GENERATE loop3;
731 
        wire_w_lg_w_lg_w_delay_round_wire_range461w467w468w(0) <= wire_w_lg_w_delay_round_wire_range461w467w(0) AND wire_input_is_infinity_ff2_w_lg_q466w(0);
732 
        loop4 : FOR i IN 0 TO 7 GENERATE
733 
                wire_w_lg_inf_num459w(i) <= inf_num(i) AND wire_w_lg_w_lg_exp_is_inf457w458w(0);
734 
        END GENERATE loop4;
735 
        wire_w_lg_w_dataa_range81w88w(0) <= wire_w_dataa_range81w(0) AND wire_w_dataa_exp_all_one_range77w(0);
736 
        wire_w_lg_w_dataa_range91w98w(0) <= wire_w_dataa_range91w(0) AND wire_w_dataa_exp_all_one_range87w(0);
737 
        wire_w_lg_w_dataa_range101w108w(0) <= wire_w_dataa_range101w(0) AND wire_w_dataa_exp_all_one_range97w(0);
738 
        wire_w_lg_w_dataa_range111w118w(0) <= wire_w_dataa_range111w(0) AND wire_w_dataa_exp_all_one_range107w(0);
739 
        wire_w_lg_w_dataa_range121w128w(0) <= wire_w_dataa_range121w(0) AND wire_w_dataa_exp_all_one_range117w(0);
740 
        wire_w_lg_w_dataa_range131w138w(0) <= wire_w_dataa_range131w(0) AND wire_w_dataa_exp_all_one_range127w(0);
741 
        wire_w_lg_w_dataa_range141w148w(0) <= wire_w_dataa_range141w(0) AND wire_w_dataa_exp_all_one_range137w(0);
742 
        wire_w_lg_w_datab_range84w90w(0) <= wire_w_datab_range84w(0) AND wire_w_datab_exp_all_one_range79w(0);
743 
        wire_w_lg_w_datab_range94w100w(0) <= wire_w_datab_range94w(0) AND wire_w_datab_exp_all_one_range89w(0);
744 
        wire_w_lg_w_datab_range104w110w(0) <= wire_w_datab_range104w(0) AND wire_w_datab_exp_all_one_range99w(0);
745 
        wire_w_lg_w_datab_range114w120w(0) <= wire_w_datab_range114w(0) AND wire_w_datab_exp_all_one_range109w(0);
746 
        wire_w_lg_w_datab_range124w130w(0) <= wire_w_datab_range124w(0) AND wire_w_datab_exp_all_one_range119w(0);
747 
        wire_w_lg_w_datab_range134w140w(0) <= wire_w_datab_range134w(0) AND wire_w_datab_exp_all_one_range129w(0);
748 
        wire_w_lg_w_datab_range144w150w(0) <= wire_w_datab_range144w(0) AND wire_w_datab_exp_all_one_range139w(0);
749 
        loop5 : FOR i IN 0 TO 21 GENERATE
750 
                wire_w_lg_w_delay_round_wire_range475w476w(i) <= wire_w_delay_round_wire_range475w(i) AND input_not_zero_ff2;
751 
        END GENERATE loop5;
752 
        wire_w_lg_w_delay_round_wire_range461w467w(0) <= wire_w_delay_round_wire_range461w(0) AND input_not_zero_ff2;
753 
        wire_w_lg_w_result_exp_all_one_range403w407w(0) <= wire_w_result_exp_all_one_range403w(0) AND wire_exp_adj_adder_w_result_range405w(0);
754 
        wire_w_lg_w_result_exp_all_one_range406w410w(0) <= wire_w_result_exp_all_one_range406w(0) AND wire_exp_adj_adder_w_result_range408w(0);
755 
        wire_w_lg_w_result_exp_all_one_range409w413w(0) <= wire_w_result_exp_all_one_range409w(0) AND wire_exp_adj_adder_w_result_range411w(0);
756 
        wire_w_lg_w_result_exp_all_one_range412w416w(0) <= wire_w_result_exp_all_one_range412w(0) AND wire_exp_adj_adder_w_result_range414w(0);
757 
        wire_w_lg_w_result_exp_all_one_range415w419w(0) <= wire_w_result_exp_all_one_range415w(0) AND wire_exp_adj_adder_w_result_range417w(0);
758 
        wire_w_lg_w_result_exp_all_one_range418w422w(0) <= wire_w_result_exp_all_one_range418w(0) AND wire_exp_adj_adder_w_result_range420w(0);
759 
        wire_w_lg_w_result_exp_all_one_range421w425w(0) <= wire_w_result_exp_all_one_range421w(0) AND wire_exp_adj_adder_w_result_range423w(0);
760 
        wire_w_lg_exp_is_inf465w(0) <= NOT exp_is_inf;
761 
        wire_w_lg_exp_is_zero453w(0) <= NOT exp_is_zero;
762 
        wire_w_lg_w_result_exp_not_zero_range449w451w(0) <= NOT wire_w_result_exp_not_zero_range449w(0);
763 
        wire_w_lg_w_lg_w469w470w471w(0) <= wire_w_lg_w469w470w(0) OR wire_input_is_infinity_ff2_w_lg_q464w(0);
764 
        loop6 : FOR i IN 0 TO 7 GENERATE
765 
                wire_w_lg_w_lg_inf_num459w460w(i) <= wire_w_lg_inf_num459w(i) OR wire_exp_adj_adder_w_lg_w_lg_w_result_range454w455w456w(i);
766 
        END GENERATE loop6;
767 
        wire_w_lg_w_lg_w_lg_w469w470w471w472w(0) <= wire_w_lg_w_lg_w469w470w471w(0) OR input_is_nan_ff2;
768 
        wire_w_lg_w_lg_exp_is_inf457w458w(0) <= wire_w_lg_exp_is_inf457w(0) OR input_is_nan_ff2;
769 
        wire_w_lg_exp_is_inf457w(0) <= exp_is_inf OR input_is_infinity_ff2;
770 
        wire_w_lg_exp_is_zero489w(0) <= exp_is_zero OR wire_input_not_zero_ff2_w_lg_q463w(0);
771 
        wire_w_lg_w_dataa_range211w213w(0) <= wire_w_dataa_range211w(0) OR wire_w_dataa_man_not_zero_range206w(0);
772 
        wire_w_lg_w_dataa_range221w223w(0) <= wire_w_dataa_range221w(0) OR wire_w_dataa_man_not_zero_range218w(0);
773 
        wire_w_lg_w_dataa_range227w229w(0) <= wire_w_dataa_range227w(0) OR wire_w_dataa_man_not_zero_range222w(0);
774 
        wire_w_lg_w_dataa_range233w235w(0) <= wire_w_dataa_range233w(0) OR wire_w_dataa_man_not_zero_range228w(0);
775 
        wire_w_lg_w_dataa_range239w241w(0) <= wire_w_dataa_range239w(0) OR wire_w_dataa_man_not_zero_range234w(0);
776 
        wire_w_lg_w_dataa_range245w247w(0) <= wire_w_dataa_range245w(0) OR wire_w_dataa_man_not_zero_range240w(0);
777 
        wire_w_lg_w_dataa_range251w253w(0) <= wire_w_dataa_range251w(0) OR wire_w_dataa_man_not_zero_range246w(0);
778 
        wire_w_lg_w_dataa_range257w259w(0) <= wire_w_dataa_range257w(0) OR wire_w_dataa_man_not_zero_range252w(0);
779 
        wire_w_lg_w_dataa_range263w265w(0) <= wire_w_dataa_range263w(0) OR wire_w_dataa_man_not_zero_range258w(0);
780 
        wire_w_lg_w_dataa_range157w159w(0) <= wire_w_dataa_range157w(0) OR wire_w_dataa_man_not_zero_range152w(0);
781 
        wire_w_lg_w_dataa_range269w271w(0) <= wire_w_dataa_range269w(0) OR wire_w_dataa_man_not_zero_range264w(0);
782 
        wire_w_lg_w_dataa_range275w277w(0) <= wire_w_dataa_range275w(0) OR wire_w_dataa_man_not_zero_range270w(0);
783 
        wire_w_lg_w_dataa_range281w283w(0) <= wire_w_dataa_range281w(0) OR wire_w_dataa_man_not_zero_range276w(0);
784 
        wire_w_lg_w_dataa_range81w83w(0) <= wire_w_dataa_range81w(0) OR wire_w_dataa_exp_not_zero_range72w(0);
785 
        wire_w_lg_w_dataa_range91w93w(0) <= wire_w_dataa_range91w(0) OR wire_w_dataa_exp_not_zero_range82w(0);
786 
        wire_w_lg_w_dataa_range101w103w(0) <= wire_w_dataa_range101w(0) OR wire_w_dataa_exp_not_zero_range92w(0);
787 
        wire_w_lg_w_dataa_range111w113w(0) <= wire_w_dataa_range111w(0) OR wire_w_dataa_exp_not_zero_range102w(0);
788 
        wire_w_lg_w_dataa_range121w123w(0) <= wire_w_dataa_range121w(0) OR wire_w_dataa_exp_not_zero_range112w(0);
789 
        wire_w_lg_w_dataa_range131w133w(0) <= wire_w_dataa_range131w(0) OR wire_w_dataa_exp_not_zero_range122w(0);
790 
        wire_w_lg_w_dataa_range163w165w(0) <= wire_w_dataa_range163w(0) OR wire_w_dataa_man_not_zero_range158w(0);
791 
        wire_w_lg_w_dataa_range141w143w(0) <= wire_w_dataa_range141w(0) OR wire_w_dataa_exp_not_zero_range132w(0);
792 
        wire_w_lg_w_dataa_range169w171w(0) <= wire_w_dataa_range169w(0) OR wire_w_dataa_man_not_zero_range164w(0);
793 
        wire_w_lg_w_dataa_range175w177w(0) <= wire_w_dataa_range175w(0) OR wire_w_dataa_man_not_zero_range170w(0);
794 
        wire_w_lg_w_dataa_range181w183w(0) <= wire_w_dataa_range181w(0) OR wire_w_dataa_man_not_zero_range176w(0);
795 
        wire_w_lg_w_dataa_range187w189w(0) <= wire_w_dataa_range187w(0) OR wire_w_dataa_man_not_zero_range182w(0);
796 
        wire_w_lg_w_dataa_range193w195w(0) <= wire_w_dataa_range193w(0) OR wire_w_dataa_man_not_zero_range188w(0);
797 
        wire_w_lg_w_dataa_range199w201w(0) <= wire_w_dataa_range199w(0) OR wire_w_dataa_man_not_zero_range194w(0);
798 
        wire_w_lg_w_dataa_range205w207w(0) <= wire_w_dataa_range205w(0) OR wire_w_dataa_man_not_zero_range200w(0);
799 
        wire_w_lg_w_datab_range214w216w(0) <= wire_w_datab_range214w(0) OR wire_w_datab_man_not_zero_range209w(0);
800 
        wire_w_lg_w_datab_range224w226w(0) <= wire_w_datab_range224w(0) OR wire_w_datab_man_not_zero_range220w(0);
801 
        wire_w_lg_w_datab_range230w232w(0) <= wire_w_datab_range230w(0) OR wire_w_datab_man_not_zero_range225w(0);
802 
        wire_w_lg_w_datab_range236w238w(0) <= wire_w_datab_range236w(0) OR wire_w_datab_man_not_zero_range231w(0);
803 
        wire_w_lg_w_datab_range242w244w(0) <= wire_w_datab_range242w(0) OR wire_w_datab_man_not_zero_range237w(0);
804 
        wire_w_lg_w_datab_range248w250w(0) <= wire_w_datab_range248w(0) OR wire_w_datab_man_not_zero_range243w(0);
805 
        wire_w_lg_w_datab_range254w256w(0) <= wire_w_datab_range254w(0) OR wire_w_datab_man_not_zero_range249w(0);
806 
        wire_w_lg_w_datab_range260w262w(0) <= wire_w_datab_range260w(0) OR wire_w_datab_man_not_zero_range255w(0);
807 
        wire_w_lg_w_datab_range266w268w(0) <= wire_w_datab_range266w(0) OR wire_w_datab_man_not_zero_range261w(0);
808 
        wire_w_lg_w_datab_range160w162w(0) <= wire_w_datab_range160w(0) OR wire_w_datab_man_not_zero_range155w(0);
809 
        wire_w_lg_w_datab_range272w274w(0) <= wire_w_datab_range272w(0) OR wire_w_datab_man_not_zero_range267w(0);
810 
        wire_w_lg_w_datab_range278w280w(0) <= wire_w_datab_range278w(0) OR wire_w_datab_man_not_zero_range273w(0);
811 
        wire_w_lg_w_datab_range284w286w(0) <= wire_w_datab_range284w(0) OR wire_w_datab_man_not_zero_range279w(0);
812 
        wire_w_lg_w_datab_range84w86w(0) <= wire_w_datab_range84w(0) OR wire_w_datab_exp_not_zero_range75w(0);
813 
        wire_w_lg_w_datab_range94w96w(0) <= wire_w_datab_range94w(0) OR wire_w_datab_exp_not_zero_range85w(0);
814 
        wire_w_lg_w_datab_range104w106w(0) <= wire_w_datab_range104w(0) OR wire_w_datab_exp_not_zero_range95w(0);
815 
        wire_w_lg_w_datab_range114w116w(0) <= wire_w_datab_range114w(0) OR wire_w_datab_exp_not_zero_range105w(0);
816 
        wire_w_lg_w_datab_range124w126w(0) <= wire_w_datab_range124w(0) OR wire_w_datab_exp_not_zero_range115w(0);
817 
        wire_w_lg_w_datab_range134w136w(0) <= wire_w_datab_range134w(0) OR wire_w_datab_exp_not_zero_range125w(0);
818 
        wire_w_lg_w_datab_range166w168w(0) <= wire_w_datab_range166w(0) OR wire_w_datab_man_not_zero_range161w(0);
819 
        wire_w_lg_w_datab_range144w146w(0) <= wire_w_datab_range144w(0) OR wire_w_datab_exp_not_zero_range135w(0);
820 
        wire_w_lg_w_datab_range172w174w(0) <= wire_w_datab_range172w(0) OR wire_w_datab_man_not_zero_range167w(0);
821 
        wire_w_lg_w_datab_range178w180w(0) <= wire_w_datab_range178w(0) OR wire_w_datab_man_not_zero_range173w(0);
822 
        wire_w_lg_w_datab_range184w186w(0) <= wire_w_datab_range184w(0) OR wire_w_datab_man_not_zero_range179w(0);
823 
        wire_w_lg_w_datab_range190w192w(0) <= wire_w_datab_range190w(0) OR wire_w_datab_man_not_zero_range185w(0);
824 
        wire_w_lg_w_datab_range196w198w(0) <= wire_w_datab_range196w(0) OR wire_w_datab_man_not_zero_range191w(0);
825 
        wire_w_lg_w_datab_range202w204w(0) <= wire_w_datab_range202w(0) OR wire_w_datab_man_not_zero_range197w(0);
826 
        wire_w_lg_w_datab_range208w210w(0) <= wire_w_datab_range208w(0) OR wire_w_datab_man_not_zero_range203w(0);
827 
        wire_w_lg_w_result_exp_not_zero_range433w436w(0) <= wire_w_result_exp_not_zero_range433w(0) OR wire_exp_adj_adder_w_result_range405w(0);
828 
        wire_w_lg_w_result_exp_not_zero_range435w438w(0) <= wire_w_result_exp_not_zero_range435w(0) OR wire_exp_adj_adder_w_result_range408w(0);
829 
        wire_w_lg_w_result_exp_not_zero_range437w440w(0) <= wire_w_result_exp_not_zero_range437w(0) OR wire_exp_adj_adder_w_result_range411w(0);
830 
        wire_w_lg_w_result_exp_not_zero_range439w442w(0) <= wire_w_result_exp_not_zero_range439w(0) OR wire_exp_adj_adder_w_result_range414w(0);
831 
        wire_w_lg_w_result_exp_not_zero_range441w444w(0) <= wire_w_result_exp_not_zero_range441w(0) OR wire_exp_adj_adder_w_result_range417w(0);
832 
        wire_w_lg_w_result_exp_not_zero_range443w446w(0) <= wire_w_result_exp_not_zero_range443w(0) OR wire_exp_adj_adder_w_result_range420w(0);
833 
        wire_w_lg_w_result_exp_not_zero_range445w448w(0) <= wire_w_result_exp_not_zero_range445w(0) OR wire_exp_adj_adder_w_result_range423w(0);
834 
        wire_w_lg_w_result_exp_not_zero_range447w450w(0) <= wire_w_result_exp_not_zero_range447w(0) OR wire_exp_adj_adder_w_result_range426w(0);
835 
        wire_w_lg_w_sticky_bit_range306w310w(0) <= wire_w_sticky_bit_range306w(0) OR wire_man_product2_mult_w_result_range308w(0);
836 
        wire_w_lg_w_sticky_bit_range336w340w(0) <= wire_w_sticky_bit_range336w(0) OR wire_man_product2_mult_w_result_range338w(0);
837 
        wire_w_lg_w_sticky_bit_range339w343w(0) <= wire_w_sticky_bit_range339w(0) OR wire_man_product2_mult_w_result_range341w(0);
838 
        wire_w_lg_w_sticky_bit_range342w346w(0) <= wire_w_sticky_bit_range342w(0) OR wire_man_product2_mult_w_result_range344w(0);
839 
        wire_w_lg_w_sticky_bit_range345w349w(0) <= wire_w_sticky_bit_range345w(0) OR wire_man_product2_mult_w_result_range347w(0);
840 
        wire_w_lg_w_sticky_bit_range348w352w(0) <= wire_w_sticky_bit_range348w(0) OR wire_man_product2_mult_w_result_range350w(0);
841 
        wire_w_lg_w_sticky_bit_range351w355w(0) <= wire_w_sticky_bit_range351w(0) OR wire_man_product2_mult_w_result_range353w(0);
842 
        wire_w_lg_w_sticky_bit_range354w358w(0) <= wire_w_sticky_bit_range354w(0) OR wire_man_product2_mult_w_result_range356w(0);
843 
        wire_w_lg_w_sticky_bit_range357w361w(0) <= wire_w_sticky_bit_range357w(0) OR wire_man_product2_mult_w_result_range359w(0);
844 
        wire_w_lg_w_sticky_bit_range360w364w(0) <= wire_w_sticky_bit_range360w(0) OR wire_man_product2_mult_w_result_range362w(0);
845 
        wire_w_lg_w_sticky_bit_range363w367w(0) <= wire_w_sticky_bit_range363w(0) OR wire_man_product2_mult_w_result_range365w(0);
846 
        wire_w_lg_w_sticky_bit_range309w313w(0) <= wire_w_sticky_bit_range309w(0) OR wire_man_product2_mult_w_result_range311w(0);
847 
        wire_w_lg_w_sticky_bit_range366w370w(0) <= wire_w_sticky_bit_range366w(0) OR wire_man_product2_mult_w_result_range368w(0);
848 
        wire_w_lg_w_sticky_bit_range369w374w(0) <= wire_w_sticky_bit_range369w(0) OR wire_man_product2_mult_w_lg_w_result_range298w373w(0);
849 
        wire_w_lg_w_sticky_bit_range312w316w(0) <= wire_w_sticky_bit_range312w(0) OR wire_man_product2_mult_w_result_range314w(0);
850 
        wire_w_lg_w_sticky_bit_range315w319w(0) <= wire_w_sticky_bit_range315w(0) OR wire_man_product2_mult_w_result_range317w(0);
851 
        wire_w_lg_w_sticky_bit_range318w322w(0) <= wire_w_sticky_bit_range318w(0) OR wire_man_product2_mult_w_result_range320w(0);
852 
        wire_w_lg_w_sticky_bit_range321w325w(0) <= wire_w_sticky_bit_range321w(0) OR wire_man_product2_mult_w_result_range323w(0);
853 
        wire_w_lg_w_sticky_bit_range324w328w(0) <= wire_w_sticky_bit_range324w(0) OR wire_man_product2_mult_w_result_range326w(0);
854 
        wire_w_lg_w_sticky_bit_range327w331w(0) <= wire_w_sticky_bit_range327w(0) OR wire_man_product2_mult_w_result_range329w(0);
855 
        wire_w_lg_w_sticky_bit_range330w334w(0) <= wire_w_sticky_bit_range330w(0) OR wire_man_product2_mult_w_result_range332w(0);
856 
        wire_w_lg_w_sticky_bit_range333w337w(0) <= wire_w_sticky_bit_range333w(0) OR wire_man_product2_mult_w_result_range335w(0);
857 
        bias <= ( "0" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
858 
        dataa_exp_all_one <= ( wire_w_lg_w_dataa_range141w148w & wire_w_lg_w_dataa_range131w138w & wire_w_lg_w_dataa_range121w128w & wire_w_lg_w_dataa_range111w118w & wire_w_lg_w_dataa_range101w108w & wire_w_lg_w_dataa_range91w98w & wire_w_lg_w_dataa_range81w88w & dataa(23));
859 
        dataa_exp_not_zero <= ( wire_w_lg_w_dataa_range141w143w & wire_w_lg_w_dataa_range131w133w & wire_w_lg_w_dataa_range121w123w & wire_w_lg_w_dataa_range111w113w & wire_w_lg_w_dataa_range101w103w & wire_w_lg_w_dataa_range91w93w & wire_w_lg_w_dataa_range81w83w & dataa(23));
860 
        dataa_man_not_zero <= ( wire_w_lg_w_dataa_range281w283w & wire_w_lg_w_dataa_range275w277w & wire_w_lg_w_dataa_range269w271w & wire_w_lg_w_dataa_range263w265w & wire_w_lg_w_dataa_range257w259w & wire_w_lg_w_dataa_range251w253w & wire_w_lg_w_dataa_range245w247w & wire_w_lg_w_dataa_range239w241w & wire_w_lg_w_dataa_range233w235w & wire_w_lg_w_dataa_range227w229w & wire_w_lg_w_dataa_range221w223w & dataa(11) & wire_w_lg_w_dataa_range211w213w & wire_w_lg_w_dataa_range205w207w & wire_w_lg_w_dataa_range199w201w & wire_w_lg_w_dataa_range193w195w & wire_w_lg_w_dataa_range187w189w & wire_w_lg_w_dataa_range181w183w & wire_w_lg_w_dataa_range175w177w & wire_w_lg_w_dataa_range169w171w & wire_w_lg_w_dataa_range163w165w & wire_w_lg_w_dataa_range157w159w & dataa(0));
861 
        datab_exp_all_one <= ( wire_w_lg_w_datab_range144w150w & wire_w_lg_w_datab_range134w140w & wire_w_lg_w_datab_range124w130w & wire_w_lg_w_datab_range114w120w & wire_w_lg_w_datab_range104w110w & wire_w_lg_w_datab_range94w100w & wire_w_lg_w_datab_range84w90w & datab(23));
862 
        datab_exp_not_zero <= ( wire_w_lg_w_datab_range144w146w & wire_w_lg_w_datab_range134w136w & wire_w_lg_w_datab_range124w126w & wire_w_lg_w_datab_range114w116w & wire_w_lg_w_datab_range104w106w & wire_w_lg_w_datab_range94w96w & wire_w_lg_w_datab_range84w86w & datab(23));
863 
        datab_man_not_zero <= ( wire_w_lg_w_datab_range284w286w & wire_w_lg_w_datab_range278w280w & wire_w_lg_w_datab_range272w274w & wire_w_lg_w_datab_range266w268w & wire_w_lg_w_datab_range260w262w & wire_w_lg_w_datab_range254w256w & wire_w_lg_w_datab_range248w250w & wire_w_lg_w_datab_range242w244w & wire_w_lg_w_datab_range236w238w & wire_w_lg_w_datab_range230w232w & wire_w_lg_w_datab_range224w226w & datab(11) & wire_w_lg_w_datab_range214w216w & wire_w_lg_w_datab_range208w210w & wire_w_lg_w_datab_range202w204w & wire_w_lg_w_datab_range196w198w & wire_w_lg_w_datab_range190w192w & wire_w_lg_w_datab_range184w186w & wire_w_lg_w_datab_range178w180w & wire_w_lg_w_datab_range172w174w & wire_w_lg_w_datab_range166w168w & wire_w_lg_w_datab_range160w162w & datab(0));
864 
        delay_round_wire <= (wire_man_round_p2_w_lg_w_q_range399w400w OR wire_man_round_p2_w_lg_w_q_range396w397w);
865 
        exp_is_inf <= (((NOT wire_exp_adj_adder_result(9)) AND wire_exp_adj_adder_result(8)) OR ((NOT wire_exp_adj_adder_result(8)) AND result_exp_all_one(7)));
866 
        exp_is_zero <= wire_exp_adj_adder_w_lg_w_result_range427w452w(0);
867 
        expmod <= ( "00000000" & wire_delay_man_product_msb_w_lg_q393w & wire_delay_man_product_msb_w_lg_q395w);
868 
        inf_num <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
869 
        lsb_bit <= man_shift_full(1);
870 
        man_shift_full <= (wire_man_product2_mult_w_lg_w_result_range302w303w OR wire_man_product2_mult_w_lg_w_result_range299w300w);
871 
        nan <= nan_ff;
872 
        overflow <= overflow_ff;
873 
        result <= ( sign_node_ff5 & exp_result_ff(7 DOWNTO 0) & man_result_ff(22 DOWNTO 0));
874 
        result_exp_all_one <= ( wire_w_lg_w_result_exp_all_one_range421w425w & wire_w_lg_w_result_exp_all_one_range418w422w & wire_w_lg_w_result_exp_all_one_range415w419w & wire_w_lg_w_result_exp_all_one_range412w416w & wire_w_lg_w_result_exp_all_one_range409w413w & wire_w_lg_w_result_exp_all_one_range406w410w & wire_w_lg_w_result_exp_all_one_range403w407w & wire_exp_adj_adder_result(0));
875 
        result_exp_not_zero <= ( wire_w_lg_w_result_exp_not_zero_range447w450w & wire_w_lg_w_result_exp_not_zero_range445w448w & wire_w_lg_w_result_exp_not_zero_range443w446w & wire_w_lg_w_result_exp_not_zero_range441w444w & wire_w_lg_w_result_exp_not_zero_range439w442w & wire_w_lg_w_result_exp_not_zero_range437w440w & wire_w_lg_w_result_exp_not_zero_range435w438w & wire_w_lg_w_result_exp_not_zero_range433w436w & wire_exp_adj_adder_result(0));
876 
        round_bit <= man_shift_full(0);
877 
        round_carry <= (round_dffe AND (lsb_dffe OR sticky_dffe));
878 
        sticky_bit <= ( wire_w_lg_w_sticky_bit_range369w374w & wire_w_lg_w_sticky_bit_range366w370w & wire_w_lg_w_sticky_bit_range363w367w & wire_w_lg_w_sticky_bit_range360w364w & wire_w_lg_w_sticky_bit_range357w361w & wire_w_lg_w_sticky_bit_range354w358w & wire_w_lg_w_sticky_bit_range351w355w & wire_w_lg_w_sticky_bit_range348w352w & wire_w_lg_w_sticky_bit_range345w349w & wire_w_lg_w_sticky_bit_range342w346w & wire_w_lg_w_sticky_bit_range339w343w & wire_w_lg_w_sticky_bit_range336w340w & wire_w_lg_w_sticky_bit_range333w337w & wire_w_lg_w_sticky_bit_range330w334w & wire_w_lg_w_sticky_bit_range327w331w & wire_w_lg_w_sticky_bit_range324w328w & wire_w_lg_w_sticky_bit_range321w325w & wire_w_lg_w_sticky_bit_range318w322w & wire_w_lg_w_sticky_bit_range315w319w & wire_w_lg_w_sticky_bit_range312w316w & wire_w_lg_w_sticky_bit_range309w313w & wire_w_lg_w_sticky_bit_range306w310w & wire_man_product2_mult_result(0));
879 
        underflow <= underflow_ff;
880 
        zero <= zero_ff;
881 
        wire_w_dataa_range211w(0) <= dataa(10);
882 
        wire_w_dataa_range221w(0) <= dataa(12);
883 
        wire_w_dataa_range227w(0) <= dataa(13);
884 
        wire_w_dataa_range233w(0) <= dataa(14);
885 
        wire_w_dataa_range239w(0) <= dataa(15);
886 
        wire_w_dataa_range245w(0) <= dataa(16);
887 
        wire_w_dataa_range251w(0) <= dataa(17);
888 
        wire_w_dataa_range257w(0) <= dataa(18);
889 
        wire_w_dataa_range263w(0) <= dataa(19);
890 
        wire_w_dataa_range157w(0) <= dataa(1);
891 
        wire_w_dataa_range269w(0) <= dataa(20);
892 
        wire_w_dataa_range275w(0) <= dataa(21);
893 
        wire_w_dataa_range281w(0) <= dataa(22);
894 
        wire_w_dataa_range81w(0) <= dataa(24);
895 
        wire_w_dataa_range91w(0) <= dataa(25);
896 
        wire_w_dataa_range101w(0) <= dataa(26);
897 
        wire_w_dataa_range111w(0) <= dataa(27);
898 
        wire_w_dataa_range121w(0) <= dataa(28);
899 
        wire_w_dataa_range131w(0) <= dataa(29);
900 
        wire_w_dataa_range163w(0) <= dataa(2);
901 
        wire_w_dataa_range141w(0) <= dataa(30);
902 
        wire_w_dataa_range169w(0) <= dataa(3);
903 
        wire_w_dataa_range175w(0) <= dataa(4);
904 
        wire_w_dataa_range181w(0) <= dataa(5);
905 
        wire_w_dataa_range187w(0) <= dataa(6);
906 
        wire_w_dataa_range193w(0) <= dataa(7);
907 
        wire_w_dataa_range199w(0) <= dataa(8);
908 
        wire_w_dataa_range205w(0) <= dataa(9);
909 
        wire_w_dataa_exp_all_one_range77w(0) <= dataa_exp_all_one(0);
910 
        wire_w_dataa_exp_all_one_range87w(0) <= dataa_exp_all_one(1);
911 
        wire_w_dataa_exp_all_one_range97w(0) <= dataa_exp_all_one(2);
912 
        wire_w_dataa_exp_all_one_range107w(0) <= dataa_exp_all_one(3);
913 
        wire_w_dataa_exp_all_one_range117w(0) <= dataa_exp_all_one(4);
914 
        wire_w_dataa_exp_all_one_range127w(0) <= dataa_exp_all_one(5);
915 
        wire_w_dataa_exp_all_one_range137w(0) <= dataa_exp_all_one(6);
916 
        wire_w_dataa_exp_not_zero_range72w(0) <= dataa_exp_not_zero(0);
917 
        wire_w_dataa_exp_not_zero_range82w(0) <= dataa_exp_not_zero(1);
918 
        wire_w_dataa_exp_not_zero_range92w(0) <= dataa_exp_not_zero(2);
919 
        wire_w_dataa_exp_not_zero_range102w(0) <= dataa_exp_not_zero(3);
920 
        wire_w_dataa_exp_not_zero_range112w(0) <= dataa_exp_not_zero(4);
921 
        wire_w_dataa_exp_not_zero_range122w(0) <= dataa_exp_not_zero(5);
922 
        wire_w_dataa_exp_not_zero_range132w(0) <= dataa_exp_not_zero(6);
923 
        wire_w_dataa_man_not_zero_range152w(0) <= dataa_man_not_zero(0);
924 
        wire_w_dataa_man_not_zero_range218w(0) <= dataa_man_not_zero(11);
925 
        wire_w_dataa_man_not_zero_range222w(0) <= dataa_man_not_zero(12);
926 
        wire_w_dataa_man_not_zero_range228w(0) <= dataa_man_not_zero(13);
927 
        wire_w_dataa_man_not_zero_range234w(0) <= dataa_man_not_zero(14);
928 
        wire_w_dataa_man_not_zero_range240w(0) <= dataa_man_not_zero(15);
929 
        wire_w_dataa_man_not_zero_range246w(0) <= dataa_man_not_zero(16);
930 
        wire_w_dataa_man_not_zero_range252w(0) <= dataa_man_not_zero(17);
931 
        wire_w_dataa_man_not_zero_range258w(0) <= dataa_man_not_zero(18);
932 
        wire_w_dataa_man_not_zero_range264w(0) <= dataa_man_not_zero(19);
933 
        wire_w_dataa_man_not_zero_range158w(0) <= dataa_man_not_zero(1);
934 
        wire_w_dataa_man_not_zero_range270w(0) <= dataa_man_not_zero(20);
935 
        wire_w_dataa_man_not_zero_range276w(0) <= dataa_man_not_zero(21);
936 
        wire_w_dataa_man_not_zero_range164w(0) <= dataa_man_not_zero(2);
937 
        wire_w_dataa_man_not_zero_range170w(0) <= dataa_man_not_zero(3);
938 
        wire_w_dataa_man_not_zero_range176w(0) <= dataa_man_not_zero(4);
939 
        wire_w_dataa_man_not_zero_range182w(0) <= dataa_man_not_zero(5);
940 
        wire_w_dataa_man_not_zero_range188w(0) <= dataa_man_not_zero(6);
941 
        wire_w_dataa_man_not_zero_range194w(0) <= dataa_man_not_zero(7);
942 
        wire_w_dataa_man_not_zero_range200w(0) <= dataa_man_not_zero(8);
943 
        wire_w_dataa_man_not_zero_range206w(0) <= dataa_man_not_zero(9);
944 
        wire_w_datab_range214w(0) <= datab(10);
945 
        wire_w_datab_range224w(0) <= datab(12);
946 
        wire_w_datab_range230w(0) <= datab(13);
947 
        wire_w_datab_range236w(0) <= datab(14);
948 
        wire_w_datab_range242w(0) <= datab(15);
949 
        wire_w_datab_range248w(0) <= datab(16);
950 
        wire_w_datab_range254w(0) <= datab(17);
951 
        wire_w_datab_range260w(0) <= datab(18);
952 
        wire_w_datab_range266w(0) <= datab(19);
953 
        wire_w_datab_range160w(0) <= datab(1);
954 
        wire_w_datab_range272w(0) <= datab(20);
955 
        wire_w_datab_range278w(0) <= datab(21);
956 
        wire_w_datab_range284w(0) <= datab(22);
957 
        wire_w_datab_range84w(0) <= datab(24);
958 
        wire_w_datab_range94w(0) <= datab(25);
959 
        wire_w_datab_range104w(0) <= datab(26);
960 
        wire_w_datab_range114w(0) <= datab(27);
961 
        wire_w_datab_range124w(0) <= datab(28);
962 
        wire_w_datab_range134w(0) <= datab(29);
963 
        wire_w_datab_range166w(0) <= datab(2);
964 
        wire_w_datab_range144w(0) <= datab(30);
965 
        wire_w_datab_range172w(0) <= datab(3);
966 
        wire_w_datab_range178w(0) <= datab(4);
967 
        wire_w_datab_range184w(0) <= datab(5);
968 
        wire_w_datab_range190w(0) <= datab(6);
969 
        wire_w_datab_range196w(0) <= datab(7);
970 
        wire_w_datab_range202w(0) <= datab(8);
971 
        wire_w_datab_range208w(0) <= datab(9);
972 
        wire_w_datab_exp_all_one_range79w(0) <= datab_exp_all_one(0);
973 
        wire_w_datab_exp_all_one_range89w(0) <= datab_exp_all_one(1);
974 
        wire_w_datab_exp_all_one_range99w(0) <= datab_exp_all_one(2);
975 
        wire_w_datab_exp_all_one_range109w(0) <= datab_exp_all_one(3);
976 
        wire_w_datab_exp_all_one_range119w(0) <= datab_exp_all_one(4);
977 
        wire_w_datab_exp_all_one_range129w(0) <= datab_exp_all_one(5);
978 
        wire_w_datab_exp_all_one_range139w(0) <= datab_exp_all_one(6);
979 
        wire_w_datab_exp_not_zero_range75w(0) <= datab_exp_not_zero(0);
980 
        wire_w_datab_exp_not_zero_range85w(0) <= datab_exp_not_zero(1);
981 
        wire_w_datab_exp_not_zero_range95w(0) <= datab_exp_not_zero(2);
982 
        wire_w_datab_exp_not_zero_range105w(0) <= datab_exp_not_zero(3);
983 
        wire_w_datab_exp_not_zero_range115w(0) <= datab_exp_not_zero(4);
984 
        wire_w_datab_exp_not_zero_range125w(0) <= datab_exp_not_zero(5);
985 
        wire_w_datab_exp_not_zero_range135w(0) <= datab_exp_not_zero(6);
986 
        wire_w_datab_man_not_zero_range155w(0) <= datab_man_not_zero(0);
987 
        wire_w_datab_man_not_zero_range220w(0) <= datab_man_not_zero(11);
988 
        wire_w_datab_man_not_zero_range225w(0) <= datab_man_not_zero(12);
989 
        wire_w_datab_man_not_zero_range231w(0) <= datab_man_not_zero(13);
990 
        wire_w_datab_man_not_zero_range237w(0) <= datab_man_not_zero(14);
991 
        wire_w_datab_man_not_zero_range243w(0) <= datab_man_not_zero(15);
992 
        wire_w_datab_man_not_zero_range249w(0) <= datab_man_not_zero(16);
993 
        wire_w_datab_man_not_zero_range255w(0) <= datab_man_not_zero(17);
994 
        wire_w_datab_man_not_zero_range261w(0) <= datab_man_not_zero(18);
995 
        wire_w_datab_man_not_zero_range267w(0) <= datab_man_not_zero(19);
996 
        wire_w_datab_man_not_zero_range161w(0) <= datab_man_not_zero(1);
997 
        wire_w_datab_man_not_zero_range273w(0) <= datab_man_not_zero(20);
998 
        wire_w_datab_man_not_zero_range279w(0) <= datab_man_not_zero(21);
999 
        wire_w_datab_man_not_zero_range167w(0) <= datab_man_not_zero(2);
1000 
        wire_w_datab_man_not_zero_range173w(0) <= datab_man_not_zero(3);
1001 
        wire_w_datab_man_not_zero_range179w(0) <= datab_man_not_zero(4);
1002 
        wire_w_datab_man_not_zero_range185w(0) <= datab_man_not_zero(5);
1003 
        wire_w_datab_man_not_zero_range191w(0) <= datab_man_not_zero(6);
1004 
        wire_w_datab_man_not_zero_range197w(0) <= datab_man_not_zero(7);
1005 
        wire_w_datab_man_not_zero_range203w(0) <= datab_man_not_zero(8);
1006 
        wire_w_datab_man_not_zero_range209w(0) <= datab_man_not_zero(9);
1007 
        wire_w_delay_round_wire_range475w <= delay_round_wire(21 DOWNTO 0);
1008 
        wire_w_delay_round_wire_range461w(0) <= delay_round_wire(22);
1009 
        wire_w_man_shift_full_range379w <= man_shift_full(24 DOWNTO 1);
1010 
        wire_w_result_exp_all_one_range403w(0) <= result_exp_all_one(0);
1011 
        wire_w_result_exp_all_one_range406w(0) <= result_exp_all_one(1);
1012 
        wire_w_result_exp_all_one_range409w(0) <= result_exp_all_one(2);
1013 
        wire_w_result_exp_all_one_range412w(0) <= result_exp_all_one(3);
1014 
        wire_w_result_exp_all_one_range415w(0) <= result_exp_all_one(4);
1015 
        wire_w_result_exp_all_one_range418w(0) <= result_exp_all_one(5);
1016 
        wire_w_result_exp_all_one_range421w(0) <= result_exp_all_one(6);
1017 
        wire_w_result_exp_not_zero_range433w(0) <= result_exp_not_zero(0);
1018 
        wire_w_result_exp_not_zero_range435w(0) <= result_exp_not_zero(1);
1019 
        wire_w_result_exp_not_zero_range437w(0) <= result_exp_not_zero(2);
1020 
        wire_w_result_exp_not_zero_range439w(0) <= result_exp_not_zero(3);
1021 
        wire_w_result_exp_not_zero_range441w(0) <= result_exp_not_zero(4);
1022 
        wire_w_result_exp_not_zero_range443w(0) <= result_exp_not_zero(5);
1023 
        wire_w_result_exp_not_zero_range445w(0) <= result_exp_not_zero(6);
1024 
        wire_w_result_exp_not_zero_range447w(0) <= result_exp_not_zero(7);
1025 
        wire_w_result_exp_not_zero_range449w(0) <= result_exp_not_zero(8);
1026 
        wire_w_sticky_bit_range306w(0) <= sticky_bit(0);
1027 
        wire_w_sticky_bit_range336w(0) <= sticky_bit(10);
1028 
        wire_w_sticky_bit_range339w(0) <= sticky_bit(11);
1029 
        wire_w_sticky_bit_range342w(0) <= sticky_bit(12);
1030 
        wire_w_sticky_bit_range345w(0) <= sticky_bit(13);
1031 
        wire_w_sticky_bit_range348w(0) <= sticky_bit(14);
1032 
        wire_w_sticky_bit_range351w(0) <= sticky_bit(15);
1033 
        wire_w_sticky_bit_range354w(0) <= sticky_bit(16);
1034 
        wire_w_sticky_bit_range357w(0) <= sticky_bit(17);
1035 
        wire_w_sticky_bit_range360w(0) <= sticky_bit(18);
1036 
        wire_w_sticky_bit_range363w(0) <= sticky_bit(19);
1037 
        wire_w_sticky_bit_range309w(0) <= sticky_bit(1);
1038 
        wire_w_sticky_bit_range366w(0) <= sticky_bit(20);
1039 
        wire_w_sticky_bit_range369w(0) <= sticky_bit(21);
1040 
        wire_w_sticky_bit_range312w(0) <= sticky_bit(2);
1041 
        wire_w_sticky_bit_range315w(0) <= sticky_bit(3);
1042 
        wire_w_sticky_bit_range318w(0) <= sticky_bit(4);
1043 
        wire_w_sticky_bit_range321w(0) <= sticky_bit(5);
1044 
        wire_w_sticky_bit_range324w(0) <= sticky_bit(6);
1045 
        wire_w_sticky_bit_range327w(0) <= sticky_bit(7);
1046 
        wire_w_sticky_bit_range330w(0) <= sticky_bit(8);
1047 
        wire_w_sticky_bit_range333w(0) <= sticky_bit(9);
1048 
        PROCESS (clock, aclr)
1049 
        BEGIN
1050 
                IF (aclr = '1') THEN dataa_exp_all_one_ff_p1 <= '0';
1051 
                ELSIF (clock = '1' AND clock'event) THEN
1052 
                        IF (clk_en = '1') THEN dataa_exp_all_one_ff_p1 <= dataa_exp_all_one(7);
1053 
                        END IF;
1054 
                END IF;
1055 
        END PROCESS;
1056 
        wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0);
1057 
        wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
1058 
        PROCESS (clock, aclr)
1059 
        BEGIN
1060 
                IF (aclr = '1') THEN dataa_exp_not_zero_ff_p1 <= '0';
1061 
                ELSIF (clock = '1' AND clock'event) THEN
1062 
                        IF (clk_en = '1') THEN dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero(7);
1063 
                        END IF;
1064 
                END IF;
1065 
        END PROCESS;
1066 
        PROCESS (clock, aclr)
1067 
        BEGIN
1068 
                IF (aclr = '1') THEN dataa_man_not_zero_ff_p1 <= '0';
1069 
                ELSIF (clock = '1' AND clock'event) THEN
1070 
                        IF (clk_en = '1') THEN dataa_man_not_zero_ff_p1 <= dataa_man_not_zero(10);
1071 
                        END IF;
1072 
                END IF;
1073 
        END PROCESS;
1074 
        wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0) <= NOT wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
1075 
        wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0) <= dataa_man_not_zero_ff_p1 OR dataa_man_not_zero_ff_p2;
1076 
        PROCESS (clock, aclr)
1077 
        BEGIN
1078 
                IF (aclr = '1') THEN dataa_man_not_zero_ff_p2 <= '0';
1079 
                ELSIF (clock = '1' AND clock'event) THEN
1080 
                        IF (clk_en = '1') THEN dataa_man_not_zero_ff_p2 <= dataa_man_not_zero(22);
1081 
                        END IF;
1082 
                END IF;
1083 
        END PROCESS;
1084 
        PROCESS (clock, aclr)
1085 
        BEGIN
1086 
                IF (aclr = '1') THEN datab_exp_all_one_ff_p1 <= '0';
1087 
                ELSIF (clock = '1' AND clock'event) THEN
1088 
                        IF (clk_en = '1') THEN datab_exp_all_one_ff_p1 <= datab_exp_all_one(7);
1089 
                        END IF;
1090 
                END IF;
1091 
        END PROCESS;
1092 
        wire_datab_exp_all_one_ff_p1_w_lg_q294w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0);
1093 
        wire_datab_exp_all_one_ff_p1_w_lg_q289w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
1094 
        PROCESS (clock, aclr)
1095 
        BEGIN
1096 
                IF (aclr = '1') THEN datab_exp_not_zero_ff_p1 <= '0';
1097 
                ELSIF (clock = '1' AND clock'event) THEN
1098 
                        IF (clk_en = '1') THEN datab_exp_not_zero_ff_p1 <= datab_exp_not_zero(7);
1099 
                        END IF;
1100 
                END IF;
1101 
        END PROCESS;
1102 
        PROCESS (clock, aclr)
1103 
        BEGIN
1104 
                IF (aclr = '1') THEN datab_man_not_zero_ff_p1 <= '0';
1105 
                ELSIF (clock = '1' AND clock'event) THEN
1106 
                        IF (clk_en = '1') THEN datab_man_not_zero_ff_p1 <= datab_man_not_zero(10);
1107 
                        END IF;
1108 
                END IF;
1109 
        END PROCESS;
1110 
        wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0) <= NOT wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
1111 
        wire_datab_man_not_zero_ff_p1_w_lg_q288w(0) <= datab_man_not_zero_ff_p1 OR datab_man_not_zero_ff_p2;
1112 
        PROCESS (clock, aclr)
1113 
        BEGIN
1114 
                IF (aclr = '1') THEN datab_man_not_zero_ff_p2 <= '0';
1115 
                ELSIF (clock = '1' AND clock'event) THEN
1116 
                        IF (clk_en = '1') THEN datab_man_not_zero_ff_p2 <= datab_man_not_zero(22);
1117 
                        END IF;
1118 
                END IF;
1119 
        END PROCESS;
1120 
        PROCESS (clock, aclr)
1121 
        BEGIN
1122 
                IF (aclr = '1') THEN delay_exp2_bias <= (OTHERS => '0');
1123 
                ELSIF (clock = '1' AND clock'event) THEN
1124 
                        IF (clk_en = '1') THEN delay_exp2_bias <= delay_exp_bias;
1125 
                        END IF;
1126 
                END IF;
1127 
        END PROCESS;
1128 
        PROCESS (clock, aclr)
1129 
        BEGIN
1130 
                IF (aclr = '1') THEN delay_exp3_bias <= (OTHERS => '0');
1131 
                ELSIF (clock = '1' AND clock'event) THEN
1132 
                        IF (clk_en = '1') THEN delay_exp3_bias <= delay_exp2_bias;
1133 
                        END IF;
1134 
                END IF;
1135 
        END PROCESS;
1136 
        PROCESS (clock, aclr)
1137 
        BEGIN
1138 
                IF (aclr = '1') THEN delay_exp_bias <= (OTHERS => '0');
1139 
                ELSIF (clock = '1' AND clock'event) THEN
1140 
                        IF (clk_en = '1') THEN delay_exp_bias <= wire_exp_bias_subtr_result;
1141 
                        END IF;
1142 
                END IF;
1143 
        END PROCESS;
1144 
        PROCESS (clock, aclr)
1145 
        BEGIN
1146 
                IF (aclr = '1') THEN delay_man_product_msb <= '0';
1147 
                ELSIF (clock = '1' AND clock'event) THEN
1148 
                        IF (clk_en = '1') THEN delay_man_product_msb <= delay_man_product_msb_p0;
1149 
                        END IF;
1150 
                END IF;
1151 
        END PROCESS;
1152 
        wire_delay_man_product_msb_w_lg_q393w(0) <= delay_man_product_msb AND wire_man_round_p2_w_q_range391w(0);
1153 
        wire_delay_man_product_msb_w_lg_q395w(0) <= delay_man_product_msb XOR wire_man_round_p2_w_q_range391w(0);
1154 
        PROCESS (clock, aclr)
1155 
        BEGIN
1156 
                IF (aclr = '1') THEN delay_man_product_msb_p0 <= '0';
1157 
                ELSIF (clock = '1' AND clock'event) THEN
1158 
                        IF (clk_en = '1') THEN delay_man_product_msb_p0 <= wire_man_product2_mult_w_result_range298w(0);
1159 
                        END IF;
1160 
                END IF;
1161 
        END PROCESS;
1162 
        PROCESS (clock, aclr)
1163 
        BEGIN
1164 
                IF (aclr = '1') THEN exp_add_p1 <= (OTHERS => '0');
1165 
                ELSIF (clock = '1' AND clock'event) THEN
1166 
                        IF (clk_en = '1') THEN exp_add_p1 <= wire_exp_add_adder_result;
1167 
                        END IF;
1168 
                END IF;
1169 
        END PROCESS;
1170 
        PROCESS (clock, aclr)
1171 
        BEGIN
1172 
                IF (aclr = '1') THEN exp_result_ff <= (OTHERS => '0');
1173 
                ELSIF (clock = '1' AND clock'event) THEN
1174 
                        IF (clk_en = '1') THEN exp_result_ff <= wire_w_lg_w_lg_inf_num459w460w;
1175 
                        END IF;
1176 
                END IF;
1177 
        END PROCESS;
1178 
        PROCESS (clock, aclr)
1179 
        BEGIN
1180 
                IF (aclr = '1') THEN input_is_infinity_dffe_0 <= '0';
1181 
                ELSIF (clock = '1' AND clock'event) THEN
1182 
                        IF (clk_en = '1') THEN input_is_infinity_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q294w(0));
1183 
                        END IF;
1184 
                END IF;
1185 
        END PROCESS;
1186 
        PROCESS (clock, aclr)
1187 
        BEGIN
1188 
                IF (aclr = '1') THEN input_is_infinity_dffe_1 <= '0';
1189 
                ELSIF (clock = '1' AND clock'event) THEN
1190 
                        IF (clk_en = '1') THEN input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
1191 
                        END IF;
1192 
                END IF;
1193 
        END PROCESS;
1194 
        PROCESS (clock, aclr)
1195 
        BEGIN
1196 
                IF (aclr = '1') THEN input_is_infinity_ff1 <= '0';
1197 
                ELSIF (clock = '1' AND clock'event) THEN
1198 
                        IF (clk_en = '1') THEN input_is_infinity_ff1 <= input_is_infinity_dffe_1;
1199 
                        END IF;
1200 
                END IF;
1201 
        END PROCESS;
1202 
        PROCESS (clock, aclr)
1203 
        BEGIN
1204 
                IF (aclr = '1') THEN input_is_infinity_ff2 <= '0';
1205 
                ELSIF (clock = '1' AND clock'event) THEN
1206 
                        IF (clk_en = '1') THEN input_is_infinity_ff2 <= input_is_infinity_ff1;
1207 
                        END IF;
1208 
                END IF;
1209 
        END PROCESS;
1210 
        wire_input_is_infinity_ff2_w_lg_q464w(0) <= input_is_infinity_ff2 AND wire_input_not_zero_ff2_w_lg_q463w(0);
1211 
        wire_input_is_infinity_ff2_w_lg_q466w(0) <= NOT input_is_infinity_ff2;
1212 
        PROCESS (clock, aclr)
1213 
        BEGIN
1214 
                IF (aclr = '1') THEN input_is_nan_dffe_0 <= '0';
1215 
                ELSIF (clock = '1' AND clock'event) THEN
1216 
                        IF (clk_en = '1') THEN input_is_nan_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q289w(0));
1217 
                        END IF;
1218 
                END IF;
1219 
        END PROCESS;
1220 
        PROCESS (clock, aclr)
1221 
        BEGIN
1222 
                IF (aclr = '1') THEN input_is_nan_dffe_1 <= '0';
1223 
                ELSIF (clock = '1' AND clock'event) THEN
1224 
                        IF (clk_en = '1') THEN input_is_nan_dffe_1 <= input_is_nan_dffe_0;
1225 
                        END IF;
1226 
                END IF;
1227 
        END PROCESS;
1228 
        PROCESS (clock, aclr)
1229 
        BEGIN
1230 
                IF (aclr = '1') THEN input_is_nan_ff1 <= '0';
1231 
                ELSIF (clock = '1' AND clock'event) THEN
1232 
                        IF (clk_en = '1') THEN input_is_nan_ff1 <= input_is_nan_dffe_1;
1233 
                        END IF;
1234 
                END IF;
1235 
        END PROCESS;
1236 
        PROCESS (clock, aclr)
1237 
        BEGIN
1238 
                IF (aclr = '1') THEN input_is_nan_ff2 <= '0';
1239 
                ELSIF (clock = '1' AND clock'event) THEN
1240 
                        IF (clk_en = '1') THEN input_is_nan_ff2 <= input_is_nan_ff1;
1241 
                        END IF;
1242 
                END IF;
1243 
        END PROCESS;
1244 
        wire_input_is_nan_ff2_w_lg_q474w(0) <= NOT input_is_nan_ff2;
1245 
        PROCESS (clock, aclr)
1246 
        BEGIN
1247 
                IF (aclr = '1') THEN input_not_zero_dffe_0 <= '0';
1248 
                ELSIF (clock = '1' AND clock'event) THEN
1249 
                        IF (clk_en = '1') THEN input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 AND datab_exp_not_zero_ff_p1);
1250 
                        END IF;
1251 
                END IF;
1252 
        END PROCESS;
1253 
        PROCESS (clock, aclr)
1254 
        BEGIN
1255 
                IF (aclr = '1') THEN input_not_zero_dffe_1 <= '0';
1256 
                ELSIF (clock = '1' AND clock'event) THEN
1257 
                        IF (clk_en = '1') THEN input_not_zero_dffe_1 <= input_not_zero_dffe_0;
1258 
                        END IF;
1259 
                END IF;
1260 
        END PROCESS;
1261 
        PROCESS (clock, aclr)
1262 
        BEGIN
1263 
                IF (aclr = '1') THEN input_not_zero_ff1 <= '0';
1264 
                ELSIF (clock = '1' AND clock'event) THEN
1265 
                        IF (clk_en = '1') THEN input_not_zero_ff1 <= input_not_zero_dffe_1;
1266 
                        END IF;
1267 
                END IF;
1268 
        END PROCESS;
1269 
        PROCESS (clock, aclr)
1270 
        BEGIN
1271 
                IF (aclr = '1') THEN input_not_zero_ff2 <= '0';
1272 
                ELSIF (clock = '1' AND clock'event) THEN
1273 
                        IF (clk_en = '1') THEN input_not_zero_ff2 <= input_not_zero_ff1;
1274 
                        END IF;
1275 
                END IF;
1276 
        END PROCESS;
1277 
        wire_input_not_zero_ff2_w_lg_q463w(0) <= NOT input_not_zero_ff2;
1278 
        PROCESS (clock, aclr)
1279 
        BEGIN
1280 
                IF (aclr = '1') THEN lsb_dffe <= '0';
1281 
                ELSIF (clock = '1' AND clock'event) THEN
1282 
                        IF (clk_en = '1') THEN lsb_dffe <= lsb_bit;
1283 
                        END IF;
1284 
                END IF;
1285 
        END PROCESS;
1286 
        PROCESS (clock, aclr)
1287 
        BEGIN
1288 
                IF (aclr = '1') THEN man_result_ff <= (OTHERS => '0');
1289 
                ELSIF (clock = '1' AND clock'event) THEN
1290 
                        IF (clk_en = '1') THEN man_result_ff <= ( wire_w_lg_w_lg_w_lg_w469w470w471w472w & wire_w_lg_w_lg_w478w479w480w);
1291 
                        END IF;
1292 
                END IF;
1293 
        END PROCESS;
1294 
        PROCESS (clock, aclr)
1295 
        BEGIN
1296 
                IF (aclr = '1') THEN man_round_p <= (OTHERS => '0');
1297 
                ELSIF (clock = '1' AND clock'event) THEN
1298 
                        IF (clk_en = '1') THEN man_round_p <= wire_w_man_shift_full_range379w;
1299 
                        END IF;
1300 
                END IF;
1301 
        END PROCESS;
1302 
        PROCESS (clock, aclr)
1303 
        BEGIN
1304 
                IF (aclr = '1') THEN man_round_p2 <= (OTHERS => '0');
1305 
                ELSIF (clock = '1' AND clock'event) THEN
1306 
                        IF (clk_en = '1') THEN man_round_p2 <= wire_man_round_adder_result;
1307 
                        END IF;
1308 
                END IF;
1309 
        END PROCESS;
1310 
        loop7 : FOR i IN 0 TO 23 GENERATE
1311 
                wire_man_round_p2_w_lg_w_q_range399w400w(i) <= wire_man_round_p2_w_q_range399w(i) AND wire_man_round_p2_w_lg_w_q_range391w398w(0);
1312 
        END GENERATE loop7;
1313 
        loop8 : FOR i IN 0 TO 23 GENERATE
1314 
                wire_man_round_p2_w_lg_w_q_range396w397w(i) <= wire_man_round_p2_w_q_range396w(i) AND wire_man_round_p2_w_q_range391w(0);
1315 
        END GENERATE loop8;
1316 
        wire_man_round_p2_w_lg_w_q_range391w398w(0) <= NOT wire_man_round_p2_w_q_range391w(0);
1317 
        wire_man_round_p2_w_q_range399w <= man_round_p2(23 DOWNTO 0);
1318 
        wire_man_round_p2_w_q_range396w <= man_round_p2(24 DOWNTO 1);
1319 
        wire_man_round_p2_w_q_range391w(0) <= man_round_p2(24);
1320 
        PROCESS (clock, aclr)
1321 
        BEGIN
1322 
                IF (aclr = '1') THEN nan_ff <= '0';
1323 
                ELSIF (clock = '1' AND clock'event) THEN
1324 
                        IF (clk_en = '1') THEN nan_ff <= (input_is_nan_ff2 OR wire_input_is_infinity_ff2_w_lg_q464w(0));
1325 
                        END IF;
1326 
                END IF;
1327 
        END PROCESS;
1328 
        PROCESS (clock, aclr)
1329 
        BEGIN
1330 
                IF (aclr = '1') THEN overflow_ff <= '0';
1331 
                ELSIF (clock = '1' AND clock'event) THEN
1332 
                        IF (clk_en = '1') THEN overflow_ff <= ((wire_w_lg_exp_is_inf457w(0) AND wire_input_is_nan_ff2_w_lg_q474w(0)) AND (NOT wire_input_is_infinity_ff2_w_lg_q464w(0)));
1333 
                        END IF;
1334 
                END IF;
1335 
        END PROCESS;
1336 
        PROCESS (clock, aclr)
1337 
        BEGIN
1338 
                IF (aclr = '1') THEN round_dffe <= '0';
1339 
                ELSIF (clock = '1' AND clock'event) THEN
1340 
                        IF (clk_en = '1') THEN round_dffe <= round_bit;
1341 
                        END IF;
1342 
                END IF;
1343 
        END PROCESS;
1344 
        PROCESS (clock, aclr)
1345 
        BEGIN
1346 
                IF (aclr = '1') THEN sign_node_ff0 <= '0';
1347 
                ELSIF (clock = '1' AND clock'event) THEN
1348 
                        IF (clk_en = '1') THEN sign_node_ff0 <= (dataa(31) XOR datab(31));
1349 
                        END IF;
1350 
                END IF;
1351 
        END PROCESS;
1352 
        PROCESS (clock, aclr)
1353 
        BEGIN
1354 
                IF (aclr = '1') THEN sign_node_ff1 <= '0';
1355 
                ELSIF (clock = '1' AND clock'event) THEN
1356 
                        IF (clk_en = '1') THEN sign_node_ff1 <= sign_node_ff0;
1357 
                        END IF;
1358 
                END IF;
1359 
        END PROCESS;
1360 
        PROCESS (clock, aclr)
1361 
        BEGIN
1362 
                IF (aclr = '1') THEN sign_node_ff2 <= '0';
1363 
                ELSIF (clock = '1' AND clock'event) THEN
1364 
                        IF (clk_en = '1') THEN sign_node_ff2 <= sign_node_ff1;
1365 
                        END IF;
1366 
                END IF;
1367 
        END PROCESS;
1368 
        PROCESS (clock, aclr)
1369 
        BEGIN
1370 
                IF (aclr = '1') THEN sign_node_ff3 <= '0';
1371 
                ELSIF (clock = '1' AND clock'event) THEN
1372 
                        IF (clk_en = '1') THEN sign_node_ff3 <= sign_node_ff2;
1373 
                        END IF;
1374 
                END IF;
1375 
        END PROCESS;
1376 
        PROCESS (clock, aclr)
1377 
        BEGIN
1378 
                IF (aclr = '1') THEN sign_node_ff4 <= '0';
1379 
                ELSIF (clock = '1' AND clock'event) THEN
1380 
                        IF (clk_en = '1') THEN sign_node_ff4 <= sign_node_ff3;
1381 
                        END IF;
1382 
                END IF;
1383 
        END PROCESS;
1384 
        PROCESS (clock, aclr)
1385 
        BEGIN
1386 
                IF (aclr = '1') THEN sign_node_ff5 <= '0';
1387 
                ELSIF (clock = '1' AND clock'event) THEN
1388 
                        IF (clk_en = '1') THEN sign_node_ff5 <= sign_node_ff4;
1389 
                        END IF;
1390 
                END IF;
1391 
        END PROCESS;
1392 
        PROCESS (clock, aclr)
1393 
        BEGIN
1394 
                IF (aclr = '1') THEN sticky_dffe <= '0';
1395 
                ELSIF (clock = '1' AND clock'event) THEN
1396 
                        IF (clk_en = '1') THEN sticky_dffe <= sticky_bit(22);
1397 
                        END IF;
1398 
                END IF;
1399 
        END PROCESS;
1400 
        PROCESS (clock, aclr)
1401 
        BEGIN
1402 
                IF (aclr = '1') THEN underflow_ff <= '0';
1403 
                ELSIF (clock = '1' AND clock'event) THEN
1404 
                        IF (clk_en = '1') THEN underflow_ff <= (((exp_is_zero AND input_not_zero_ff2) AND wire_input_is_nan_ff2_w_lg_q474w(0)) AND (NOT wire_input_is_infinity_ff2_w_lg_q464w(0)));
1405 
                        END IF;
1406 
                END IF;
1407 
        END PROCESS;
1408 
        PROCESS (clock, aclr)
1409 
        BEGIN
1410 
                IF (aclr = '1') THEN zero_ff <= '0';
1411 
                ELSIF (clock = '1' AND clock'event) THEN
1412 
                        IF (clk_en = '1') THEN zero_ff <= ((wire_w_lg_exp_is_zero489w(0) AND wire_input_is_nan_ff2_w_lg_q474w(0)) AND wire_input_is_infinity_ff2_w_lg_q466w(0));
1413 
                        END IF;
1414 
                END IF;
1415 
        END PROCESS;
1416 
        wire_exp_add_adder_dataa <= ( "0" & dataa(30 DOWNTO 23));
1417 
        wire_exp_add_adder_datab <= ( "0" & datab(30 DOWNTO 23));
1418 
        exp_add_adder :  lpm_add_sub
1419 
          GENERIC MAP (
1420 
                LPM_PIPELINE => 1,
1421 
                LPM_WIDTH => 9
1422 
          )
1423 
          PORT MAP (
1424 
                aclr => aclr,
1425 
                cin => wire_gnd,
1426 
                clken => clk_en,
1427 
                clock => clock,
1428 
                dataa => wire_exp_add_adder_dataa,
1429 
                datab => wire_exp_add_adder_datab,
1430 
                result => wire_exp_add_adder_result
1431 
          );
1432 
        loop9 : FOR i IN 0 TO 7 GENERATE
1433 
                wire_exp_adj_adder_w_lg_w_lg_w_result_range454w455w456w(i) <= wire_exp_adj_adder_w_lg_w_result_range454w455w(i) AND input_not_zero_ff2;
1434 
        END GENERATE loop9;
1435 
        loop10 : FOR i IN 0 TO 7 GENERATE
1436 
                wire_exp_adj_adder_w_lg_w_result_range454w455w(i) <= wire_exp_adj_adder_w_result_range454w(i) AND wire_w_lg_exp_is_zero453w(0);
1437 
        END GENERATE loop10;
1438 
        wire_exp_adj_adder_w_lg_w_result_range427w452w(0) <= wire_exp_adj_adder_w_result_range427w(0) OR wire_w_lg_w_result_exp_not_zero_range449w451w(0);
1439 
        wire_exp_adj_adder_w_result_range405w(0) <= wire_exp_adj_adder_result(1);
1440 
        wire_exp_adj_adder_w_result_range408w(0) <= wire_exp_adj_adder_result(2);
1441 
        wire_exp_adj_adder_w_result_range411w(0) <= wire_exp_adj_adder_result(3);
1442 
        wire_exp_adj_adder_w_result_range414w(0) <= wire_exp_adj_adder_result(4);
1443 
        wire_exp_adj_adder_w_result_range417w(0) <= wire_exp_adj_adder_result(5);
1444 
        wire_exp_adj_adder_w_result_range420w(0) <= wire_exp_adj_adder_result(6);
1445 
        wire_exp_adj_adder_w_result_range454w <= wire_exp_adj_adder_result(7 DOWNTO 0);
1446 
        wire_exp_adj_adder_w_result_range423w(0) <= wire_exp_adj_adder_result(7);
1447 
        wire_exp_adj_adder_w_result_range426w(0) <= wire_exp_adj_adder_result(8);
1448 
        wire_exp_adj_adder_w_result_range427w(0) <= wire_exp_adj_adder_result(9);
1449 
        exp_adj_adder :  lpm_add_sub
1450 
          GENERIC MAP (
1451 
                LPM_PIPELINE => 0,
1452 
                LPM_WIDTH => 10
1453 
          )
1454 
          PORT MAP (
1455 
                cin => wire_gnd,
1456 
                dataa => delay_exp3_bias,
1457 
                datab => expmod,
1458 
                result => wire_exp_adj_adder_result
1459 
          );
1460 
        wire_exp_bias_subtr_dataa <= ( "0" & exp_add_p1(8 DOWNTO 0));
1461 
        wire_exp_bias_subtr_datab <= ( bias(9 DOWNTO 0));
1462 
        exp_bias_subtr :  lpm_add_sub
1463 
          GENERIC MAP (
1464 
                LPM_DIRECTION => "SUB",
1465 
                LPM_PIPELINE => 0,
1466 
                LPM_REPRESENTATION => "UNSIGNED",
1467 
                LPM_WIDTH => 10
1468 
          )
1469 
          PORT MAP (
1470 
                dataa => wire_exp_bias_subtr_dataa,
1471 
                datab => wire_exp_bias_subtr_datab,
1472 
                result => wire_exp_bias_subtr_result
1473 
          );
1474 
        wire_man_round_adder_dataa <= ( "0" & man_round_p);
1475 
        wire_man_round_adder_datab <= ( "000000000000000000000000" & round_carry);
1476 
        man_round_adder :  lpm_add_sub
1477 
          GENERIC MAP (
1478 
                LPM_PIPELINE => 0,
1479 
                LPM_WIDTH => 25
1480 
          )
1481 
          PORT MAP (
1482 
                dataa => wire_man_round_adder_dataa,
1483 
                datab => wire_man_round_adder_datab,
1484 
                result => wire_man_round_adder_result
1485 
          );
1486 
        loop11 : FOR i IN 0 TO 24 GENERATE
1487 
                wire_man_product2_mult_w_lg_w_result_range302w303w(i) <= wire_man_product2_mult_w_result_range302w(i) AND wire_man_product2_mult_w_lg_w_result_range298w301w(0);
1488 
        END GENERATE loop11;
1489 
        loop12 : FOR i IN 0 TO 24 GENERATE
1490 
                wire_man_product2_mult_w_lg_w_result_range299w300w(i) <= wire_man_product2_mult_w_result_range299w(i) AND wire_man_product2_mult_w_result_range298w(0);
1491 
        END GENERATE loop12;
1492 
        wire_man_product2_mult_w_lg_w_result_range298w373w(0) <= wire_man_product2_mult_w_result_range298w(0) AND wire_man_product2_mult_w_result_range371w(0);
1493 
        wire_man_product2_mult_w_lg_w_result_range298w301w(0) <= NOT wire_man_product2_mult_w_result_range298w(0);
1494 
        wire_man_product2_mult_dataa <= ( "1" & dataa(22 DOWNTO 0));
1495 
        wire_man_product2_mult_datab <= ( "1" & datab(22 DOWNTO 0));
1496 
        wire_man_product2_mult_w_result_range335w(0) <= wire_man_product2_mult_result(10);
1497 
        wire_man_product2_mult_w_result_range338w(0) <= wire_man_product2_mult_result(11);
1498 
        wire_man_product2_mult_w_result_range341w(0) <= wire_man_product2_mult_result(12);
1499 
        wire_man_product2_mult_w_result_range344w(0) <= wire_man_product2_mult_result(13);
1500 
        wire_man_product2_mult_w_result_range347w(0) <= wire_man_product2_mult_result(14);
1501 
        wire_man_product2_mult_w_result_range350w(0) <= wire_man_product2_mult_result(15);
1502 
        wire_man_product2_mult_w_result_range353w(0) <= wire_man_product2_mult_result(16);
1503 
        wire_man_product2_mult_w_result_range356w(0) <= wire_man_product2_mult_result(17);
1504 
        wire_man_product2_mult_w_result_range359w(0) <= wire_man_product2_mult_result(18);
1505 
        wire_man_product2_mult_w_result_range362w(0) <= wire_man_product2_mult_result(19);
1506 
        wire_man_product2_mult_w_result_range308w(0) <= wire_man_product2_mult_result(1);
1507 
        wire_man_product2_mult_w_result_range365w(0) <= wire_man_product2_mult_result(20);
1508 
        wire_man_product2_mult_w_result_range368w(0) <= wire_man_product2_mult_result(21);
1509 
        wire_man_product2_mult_w_result_range371w(0) <= wire_man_product2_mult_result(22);
1510 
        wire_man_product2_mult_w_result_range311w(0) <= wire_man_product2_mult_result(2);
1511 
        wire_man_product2_mult_w_result_range314w(0) <= wire_man_product2_mult_result(3);
1512 
        wire_man_product2_mult_w_result_range302w <= wire_man_product2_mult_result(46 DOWNTO 22);
1513 
        wire_man_product2_mult_w_result_range299w <= wire_man_product2_mult_result(47 DOWNTO 23);
1514 
        wire_man_product2_mult_w_result_range298w(0) <= wire_man_product2_mult_result(47);
1515 
        wire_man_product2_mult_w_result_range317w(0) <= wire_man_product2_mult_result(4);
1516 
        wire_man_product2_mult_w_result_range320w(0) <= wire_man_product2_mult_result(5);
1517 
        wire_man_product2_mult_w_result_range323w(0) <= wire_man_product2_mult_result(6);
1518 
        wire_man_product2_mult_w_result_range326w(0) <= wire_man_product2_mult_result(7);
1519 
        wire_man_product2_mult_w_result_range329w(0) <= wire_man_product2_mult_result(8);
1520 
        wire_man_product2_mult_w_result_range332w(0) <= wire_man_product2_mult_result(9);
1521 
        man_product2_mult :  lpm_mult
1522 
          GENERIC MAP (
1523 
                LPM_PIPELINE => 3,
1524 
                LPM_REPRESENTATION => "UNSIGNED",
1525 
                LPM_WIDTHA => 24,
1526 
                LPM_WIDTHB => 24,
1527 
                LPM_WIDTHP => 48,
1528 
                LPM_WIDTHS => 1,
1529 
                lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
1530 
          )
1531 
          PORT MAP (
1532 
                aclr => aclr,
1533 
                clken => clk_en,
1534 
                clock => clock,
1535 
                dataa => wire_man_product2_mult_dataa,
1536 
                datab => wire_man_product2_mult_datab,
1537 
                result => wire_man_product2_mult_result
1538 
          );
1539 
 
1540 
 END RTL; --CI_ALTFP_MULT_altfp_mult_50n
1541 
--VALID FILE
1542 
 
1543 
 
1544 
LIBRARY ieee;
1545 
USE ieee.std_logic_1164.all;
1546 
 
1547 
ENTITY CI_ALTFP_MULT IS
1548 
        PORT
1549 
        (
1550 
                aclr            : IN STD_LOGIC ;
1551 
                clk_en          : IN STD_LOGIC ;
1552 
                clock           : IN STD_LOGIC ;
1553 
                dataa           : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
1554 
                datab           : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
1555 
                nan             : OUT STD_LOGIC ;
1556 
                overflow                : OUT STD_LOGIC ;
1557 
                result          : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
1558 
                underflow               : OUT STD_LOGIC ;
1559 
                zero            : OUT STD_LOGIC
1560 
        );
1561 
END CI_ALTFP_MULT;
1562 
 
1563 
 
1564 
ARCHITECTURE RTL OF ci_altfp_mult IS
1565 
 
1566 
        SIGNAL sub_wire0        : STD_LOGIC ;
1567 
        SIGNAL sub_wire1        : STD_LOGIC ;
1568 
        SIGNAL sub_wire2        : STD_LOGIC ;
1569 
        SIGNAL sub_wire3        : STD_LOGIC ;
1570 
        SIGNAL sub_wire4        : STD_LOGIC_VECTOR (31 DOWNTO 0);
1571 
 
1572 
 
1573 
 
1574 
        COMPONENT CI_ALTFP_MULT_altfp_mult_50n
1575 
        PORT (
1576 
                        dataa   : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
1577 
                        datab   : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
1578 
                        overflow        : OUT STD_LOGIC ;
1579 
                        nan     : OUT STD_LOGIC ;
1580 
                        underflow       : OUT STD_LOGIC ;
1581 
                        clk_en  : IN STD_LOGIC ;
1582 
                        aclr    : IN STD_LOGIC ;
1583 
                        clock   : IN STD_LOGIC ;
1584 
                        zero    : OUT STD_LOGIC ;
1585 
                        result  : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
1586 
        );
1587 
        END COMPONENT;
1588 
 
1589 
BEGIN
1590 
        overflow    <= sub_wire0;
1591 
        nan    <= sub_wire1;
1592 
        underflow    <= sub_wire2;
1593 
        zero    <= sub_wire3;
1594 
        result    <= sub_wire4(31 DOWNTO 0);
1595 
 
1596 
        CI_ALTFP_MULT_altfp_mult_50n_component : CI_ALTFP_MULT_altfp_mult_50n
1597 
        PORT MAP (
1598 
                dataa => dataa,
1599 
                datab => datab,
1600 
                clk_en => clk_en,
1601 
                aclr => aclr,
1602 
                clock => clock,
1603 
                overflow => sub_wire0,
1604 
                nan => sub_wire1,
1605 
                underflow => sub_wire2,
1606 
                zero => sub_wire3,
1607 
                result => sub_wire4
1608 
        );
1609 
 
1610 
 
1611 
 
1612 
END RTL;
1613 
 
1614 
-- ============================================================
1615 
-- CNX file retrieval info
1616 
-- ============================================================
1617 
-- Retrieval info: PRIVATE: FPM_FORMAT STRING "Single"
1618 
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
1619 
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1620 
-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
1621 
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
1622 
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
1623 
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
1624 
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "6"
1625 
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
1626 
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
1627 
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
1628 
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1629 
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL clk_en
1630 
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1631 
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
1632 
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
1633 
-- Retrieval info: USED_PORT: nan 0 0 0 0 OUTPUT NODEFVAL nan
1634 
-- Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL overflow
1635 
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
1636 
-- Retrieval info: USED_PORT: underflow 0 0 0 0 OUTPUT NODEFVAL underflow
1637 
-- Retrieval info: USED_PORT: zero 0 0 0 0 OUTPUT NODEFVAL zero
1638 
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
1639 
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
1640 
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1641 
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
1642 
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1643 
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
1644 
-- Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
1645 
-- Retrieval info: CONNECT: underflow 0 0 0 0 @underflow 0 0 0 0
1646 
-- Retrieval info: CONNECT: nan 0 0 0 0 @nan 0 0 0 0
1647 
-- Retrieval info: CONNECT: zero 0 0 0 0 @zero 0 0 0 0
1648 
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
1649 
-- Retrieval info: GEN_FILE: TYPE_NORMAL CI_ALTFP_MULT.vhd TRUE
1650 
-- Retrieval info: GEN_FILE: TYPE_NORMAL CI_ALTFP_MULT.inc FALSE
1651 
-- Retrieval info: GEN_FILE: TYPE_NORMAL CI_ALTFP_MULT.cmp TRUE
1652 
-- Retrieval info: GEN_FILE: TYPE_NORMAL CI_ALTFP_MULT.bsf TRUE FALSE
1653 
-- Retrieval info: GEN_FILE: TYPE_NORMAL CI_ALTFP_MULT_inst.vhd TRUE
1654 
-- Retrieval info: LIB_FILE: lpm

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.