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[/] [complexise/] [trunk/] [lpm_mux0.vhd] - Blame information for rev 2

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1 2 iloveliora
-- megafunction wizard: %LPM_MUX%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: lpm_mux 
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-- ============================================================
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-- File Name: lpm_mux0.vhd
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-- Megafunction Name(s):
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--                      lpm_mux
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--
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-- Simulation Library Files(s):
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--                      lpm
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2009 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions 
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--and other software and tools, and its AMPP partner logic 
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--functions, and any output files from any of the foregoing 
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--(including device programming or simulation files), and any 
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--associated documentation or information are expressly subject 
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--to the terms and conditions of the Altera Program License 
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--Subscription Agreement, Altera MegaCore Function License 
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--Agreement, or other applicable license agreement, including, 
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--without limitation, that your use is for the sole purpose of 
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--programming logic devices manufactured by Altera and sold by 
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--Altera or its authorized distributors.  Please refer to the 
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY lpm;
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USE lpm.lpm_components.all;
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ENTITY lpm_mux0 IS
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        PORT
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        (
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                data0x          : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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                data1x          : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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                data2x          : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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                sel             : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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                result          : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
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        );
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END lpm_mux0;
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ARCHITECTURE SYN OF lpm_mux0 IS
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--      type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
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        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (31 DOWNTO 0);
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        SIGNAL sub_wire1        : STD_LOGIC_VECTOR (31 DOWNTO 0);
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        SIGNAL sub_wire2        : STD_LOGIC_2D (2 DOWNTO 0, 31 DOWNTO 0);
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        SIGNAL sub_wire3        : STD_LOGIC_VECTOR (31 DOWNTO 0);
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        SIGNAL sub_wire4        : STD_LOGIC_VECTOR (31 DOWNTO 0);
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BEGIN
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        sub_wire4    <= data0x(31 DOWNTO 0);
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        sub_wire3    <= data1x(31 DOWNTO 0);
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        result    <= sub_wire0(31 DOWNTO 0);
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        sub_wire1    <= data2x(31 DOWNTO 0);
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        sub_wire2(2, 0)    <= sub_wire1(0);
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        sub_wire2(2, 1)    <= sub_wire1(1);
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        sub_wire2(2, 2)    <= sub_wire1(2);
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        sub_wire2(2, 3)    <= sub_wire1(3);
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        sub_wire2(2, 4)    <= sub_wire1(4);
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        sub_wire2(2, 5)    <= sub_wire1(5);
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        sub_wire2(2, 6)    <= sub_wire1(6);
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        sub_wire2(2, 7)    <= sub_wire1(7);
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        sub_wire2(2, 8)    <= sub_wire1(8);
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        sub_wire2(2, 9)    <= sub_wire1(9);
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        sub_wire2(2, 10)    <= sub_wire1(10);
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        sub_wire2(2, 11)    <= sub_wire1(11);
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        sub_wire2(2, 12)    <= sub_wire1(12);
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        sub_wire2(2, 13)    <= sub_wire1(13);
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        sub_wire2(2, 14)    <= sub_wire1(14);
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        sub_wire2(2, 15)    <= sub_wire1(15);
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        sub_wire2(2, 16)    <= sub_wire1(16);
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        sub_wire2(2, 17)    <= sub_wire1(17);
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        sub_wire2(2, 18)    <= sub_wire1(18);
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        sub_wire2(2, 19)    <= sub_wire1(19);
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        sub_wire2(2, 20)    <= sub_wire1(20);
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        sub_wire2(2, 21)    <= sub_wire1(21);
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        sub_wire2(2, 22)    <= sub_wire1(22);
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        sub_wire2(2, 23)    <= sub_wire1(23);
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        sub_wire2(2, 24)    <= sub_wire1(24);
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        sub_wire2(2, 25)    <= sub_wire1(25);
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        sub_wire2(2, 26)    <= sub_wire1(26);
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        sub_wire2(2, 27)    <= sub_wire1(27);
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        sub_wire2(2, 28)    <= sub_wire1(28);
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        sub_wire2(2, 29)    <= sub_wire1(29);
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        sub_wire2(2, 30)    <= sub_wire1(30);
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        sub_wire2(2, 31)    <= sub_wire1(31);
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        sub_wire2(1, 0)    <= sub_wire3(0);
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        sub_wire2(1, 1)    <= sub_wire3(1);
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        sub_wire2(1, 2)    <= sub_wire3(2);
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        sub_wire2(1, 3)    <= sub_wire3(3);
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        sub_wire2(1, 4)    <= sub_wire3(4);
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        sub_wire2(1, 5)    <= sub_wire3(5);
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        sub_wire2(1, 6)    <= sub_wire3(6);
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        sub_wire2(1, 7)    <= sub_wire3(7);
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        sub_wire2(1, 8)    <= sub_wire3(8);
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        sub_wire2(1, 9)    <= sub_wire3(9);
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        sub_wire2(1, 10)    <= sub_wire3(10);
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        sub_wire2(1, 11)    <= sub_wire3(11);
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        sub_wire2(1, 12)    <= sub_wire3(12);
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        sub_wire2(1, 13)    <= sub_wire3(13);
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        sub_wire2(1, 14)    <= sub_wire3(14);
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        sub_wire2(1, 15)    <= sub_wire3(15);
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        sub_wire2(1, 16)    <= sub_wire3(16);
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        sub_wire2(1, 17)    <= sub_wire3(17);
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        sub_wire2(1, 18)    <= sub_wire3(18);
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        sub_wire2(1, 19)    <= sub_wire3(19);
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        sub_wire2(1, 20)    <= sub_wire3(20);
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        sub_wire2(1, 21)    <= sub_wire3(21);
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        sub_wire2(1, 22)    <= sub_wire3(22);
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        sub_wire2(1, 23)    <= sub_wire3(23);
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        sub_wire2(1, 24)    <= sub_wire3(24);
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        sub_wire2(1, 25)    <= sub_wire3(25);
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        sub_wire2(1, 26)    <= sub_wire3(26);
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        sub_wire2(1, 27)    <= sub_wire3(27);
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        sub_wire2(1, 28)    <= sub_wire3(28);
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        sub_wire2(1, 29)    <= sub_wire3(29);
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        sub_wire2(1, 30)    <= sub_wire3(30);
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        sub_wire2(1, 31)    <= sub_wire3(31);
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        sub_wire2(0, 0)    <= sub_wire4(0);
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        sub_wire2(0, 1)    <= sub_wire4(1);
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        sub_wire2(0, 2)    <= sub_wire4(2);
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        sub_wire2(0, 3)    <= sub_wire4(3);
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        sub_wire2(0, 4)    <= sub_wire4(4);
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        sub_wire2(0, 5)    <= sub_wire4(5);
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        sub_wire2(0, 6)    <= sub_wire4(6);
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        sub_wire2(0, 7)    <= sub_wire4(7);
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        sub_wire2(0, 8)    <= sub_wire4(8);
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        sub_wire2(0, 9)    <= sub_wire4(9);
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        sub_wire2(0, 10)    <= sub_wire4(10);
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        sub_wire2(0, 11)    <= sub_wire4(11);
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        sub_wire2(0, 12)    <= sub_wire4(12);
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        sub_wire2(0, 13)    <= sub_wire4(13);
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        sub_wire2(0, 14)    <= sub_wire4(14);
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        sub_wire2(0, 15)    <= sub_wire4(15);
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        sub_wire2(0, 16)    <= sub_wire4(16);
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        sub_wire2(0, 17)    <= sub_wire4(17);
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        sub_wire2(0, 18)    <= sub_wire4(18);
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        sub_wire2(0, 19)    <= sub_wire4(19);
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        sub_wire2(0, 20)    <= sub_wire4(20);
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        sub_wire2(0, 21)    <= sub_wire4(21);
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        sub_wire2(0, 22)    <= sub_wire4(22);
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        sub_wire2(0, 23)    <= sub_wire4(23);
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        sub_wire2(0, 24)    <= sub_wire4(24);
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        sub_wire2(0, 25)    <= sub_wire4(25);
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        sub_wire2(0, 26)    <= sub_wire4(26);
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        sub_wire2(0, 27)    <= sub_wire4(27);
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        sub_wire2(0, 28)    <= sub_wire4(28);
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        sub_wire2(0, 29)    <= sub_wire4(29);
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        sub_wire2(0, 30)    <= sub_wire4(30);
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        sub_wire2(0, 31)    <= sub_wire4(31);
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        lpm_mux_component : lpm_mux
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        GENERIC MAP (
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                lpm_size => 3,
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                lpm_type => "LPM_MUX",
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                lpm_width => 32,
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                lpm_widths => 2
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        )
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        PORT MAP (
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                sel => sel,
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                data => sub_wire2,
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                result => sub_wire0
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        );
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "3"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
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-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
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-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
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-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0]
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-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0]
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-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0]
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-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
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-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
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-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
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-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
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-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
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-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
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-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
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-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: lpm

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