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[/] [configurator/] [trunk/] [test/] [versatile_mem_ctrl_defines.v] - Blame information for rev 12

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Line No. Rev Author Line
1 9 unneback 
//=tab Main
2 
 
3 12 unneback 
//=comment Select number of <b>WB Groups</b>
4 10 linus 
 
5 9 unneback 
// Number of WB groups
6 
//=select
7 
//`define WB_GRPS_1 // 1
8 
//`define WB_GRPS_2 // 2
9 
`define WB_GRPS_3 // 3
10 
//`define WB_GRPS_4 // 4
11 
//`define WB_GRPS_5 // 5
12 
//`define WB_GRPS_6 // 6
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//`define WB_GRPS_7 // 7
14 
//`define WB_GRPS_8 // 8
15 
//=end
16 
 
17 
`ifdef WB_GRPS_2
18 
    `define WB_GRPS_1
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    `define NR_OF_WB_GRPS 2
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    `define NR_OF_PORTS 2
21 
`endif
22 
`ifdef WB_GRPS_3
23 
    `define WB_GRPS_1
24 
    `define WB_GRPS_2
25 
    `define NR_OF_WB_GRPS 3
26 
    `define NR_OF_PORTS 3
27 
`endif
28 
`ifdef WB_GRPS_4
29 
    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define WB_GRPS_3
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    `define NR_OF_WB_GRPS 4
33 
    `define NR_OF_PORTS 4
34 
`endif
35 
`ifdef WB_GRPS_5
36 
    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define WB_GRPS_3
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    `define WB_GRPS_4
40 
    `define NR_OF_WB_GRPS 5
41 
    `define NR_OF_PORTS 5
42 
`endif
43 
`ifdef WB_GRPS_6
44 
    `define WB_GRPS_1
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    `define WB_GRPS_2
46 
    `define WB_GRPS_3
47 
    `define WB_GRPS_4
48 
    `define WB_GRPS_5
49 
    `define NR_OF_WB_GRPS 6
50 
    `define NR_OF_PORTS 6
51 
`endif
52 
`ifdef WB_GRPS_7
53 
    `define WB_GRPS_1
54 
    `define WB_GRPS_2
55 
    `define WB_GRPS_3
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    `define WB_GRPS_4
57 
    `define WB_GRPS_5
58 
    `define WB_GRPS_6
59 
    `define NR_OF_WB_GRPS 7
60 
    `define NR_OF_PORTS 7
61 
`endif
62 
`ifdef WB_GRPS_8
63 
    `define WB_GRPS_1
64 
    `define WB_GRPS_2
65 
    `define WB_GRPS_3
66 
    `define WB_GRPS_4
67 
    `define WB_GRPS_5
68 
    `define WB_GRPS_6
69 
    `define WB_GRPS_7
70 
    `define NR_OF_WB_GRPS 8
71 
    `define NR_OF_PORTS 8
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`endif
73 
 
74 10 linus 
//=comment Clock domain settings
75 
 
76 9 unneback 
// Clock domain crossing WB1
77 
//=select
78 
//`define WB1_MEM_CLK // mem clk domain
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`define WB1_CLK // wb1 clk domain
80 
//=end
81 
// Clock domain crossing WB1
82 
//=select
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//`define WB2_MEM_CLK // mem clk domain
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`define WB2_CLK // wb2 clk domain
85 
//=end
86 
// Clock domain crossing WB1
87 
//=select
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`define WB3_MEM_CLK // mem clk domain
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//`define WB3_CLK // wb3 clk domain
90 
//=end
91 
// Clock domain crossing WB1
92 
//=select
93 
//`define WB4_MEM_CLK // mem clk domain
94 
`define WB4_CLK // wb4 clk domain
95 
//=end
96 
// Clock domain crossing WB1
97 
//=select
98 
//`define WB5_MEM_CLK // mem clk domain
99 
`define WB5_CLK // wb5 clk domain
100 
//=end
101 
// Clock domain crossing WB1
102 
//=select
103 
//`define WB6_MEM_CLK // mem clk domain
104 
`define WB6_CLK // wb6 clk domain
105 
//=end
106 
// Clock domain crossing WB1
107 
//=select
108 
//`define WB7_MEM_CLK // mem clk domain
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`define WB7_CLK // wb7 clk domain
110 
//=end
111 
// Clock domain crossing WB1
112 
//=select
113 
//`define WB8_MEM_CLK // mem clk domain
114 
`define WB8_CLK // wb8 clk domain
115 
//=end
116 
 
117 10 linus 
//=comment Misc. settings
118 
 
119 9 unneback 
// Module base name
120 
`define BASE versatile_mem_ctrl_
121 
 
122 
// Memory type
123 
//=select
124 
//`define RAM // RAM
125 
//`define SDR // SDR
126 
//`define DDR2 // DDR2
127 
`define DDR3 // DDR3
128 
//=end
129 
 
130 
// Shadow RAM
131 
`define SHADOW_RAM
132 
 
133 
//=tab RAM
134 
// Number of bits in address
135 
`define RAM_ADR_SIZE 16
136 
// Capacity in KBytes
137 
`define RAM_MEM_SIZE_KB 48
138 
`ifdef RAM_MEM_SIZE_KB
139 
`define RAM_MEM_SIZE `RAM_MEM_SIZE_KB*1024
140 
`endif
141 
 
142 
// Memory init
143 
`define RAM_MEM_INIT_DUMMY
144 
`ifndef RAM_MEM_INIT_DUMMY
145 
    `define RAM_MEM_INIT 0
146 
`else
147 
    `define RAM_MEM_INIT 1
148 
`endif
149 
 
150 
// Memory init file
151 
`define RAM_MEM_INIT_FILE "ram_init.v"
152 
 
153 
`ifdef RAM
154 
`define WB_ADR_SIZE `RAM_ADR_SIZE
155 
`endif
156 
`ifdef SHADOW_RAM
157 
`define WB_RAM_ADR_SIZE `RAM_ADR_SIZE
158 
`endif
159 
//=tab SDR SDRAM
160 
 
161 
// External data bus size
162 
`define SDR_EXT_DAT_SIZE 16
163 
 
164 
// Memory part
165 
//=select Memory part
166 
//`define MT48LC4M16 // Micron 4M16, 8MB
167 
`define MT48LC16M16 // Micron 16M16, 32MB
168 
//`define MT48LC32M16 // Micron 32M16, 64MB
169 
//=end
170 
 
171 
// SDRAM clock frequency
172 
// set refresh counter timeout
173 
// all rows should be refreshed every 64 ms
174 
// SDRAM CLK frequency
175 
//=select SDRAM CLK
176 
`define SDR_SDRAM_CLK_64 // SDRAM_CLK_64
177 
//`define SDR_SDRAM_CLK_75 // SDRAM_CLK_75
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//`define SDR_SDRAM_CLK_125 // SDRAM_CLK_125
179 
//`define SDR_SDRAM_CLK_133 // SDRAM_CLK_133
180 
//`define SDR_SDRAM_CLK_154 // SDRAM_CLK_154
181 
//=end
182 
 
183 
`ifdef MT48LC4M16
184 
// using 1 of MT48LC4M16
185 
// SDRAM data width is 16
186 
`define SDR_SDRAM_DATA_WIDTH 16
187 
`define SDR_SDRAM_DATA_WIDTH_16
188 
`define SDR_COL_SIZE 8
189 
`define SDR_ROW_SIZE 12
190 
`define SDR_ROW_SIZE_12
191 
`define SDR_BA_SIZE 2
192 
`endif //  `ifdef MT48LC4M16
193 
 
194 
`ifdef MT48LC16M16
195 
// using 1 of MT48LC16M16
196 
// SDRAM data width is 16
197 
`define SDR_SDRAM_DATA_WIDTH 16
198 
`define SDR_SDRAM_DATA_WIDTH_16
199 
`define SDR_COL_SIZE 9
200 
`define SDR_ROW_SIZE 13
201 
`define SDR_ROW_SIZE_13
202 
`define SDR_BA_SIZE 2
203 
`endif //  `ifdef MT48LC16M16
204 
 
205 
`ifdef MT48LC32M16
206 
// using 1 of MT48LC32M16
207 
// SDRAM data width is 16
208 
`define SDR_SDRAM_DATA_WIDTH 16
209 
`define SDR_SDRAM_DATA_WIDTH_16
210 
`define SDR_COL_SIZE 10
211 
`define SDR_ROW_SIZE 13
212 
`define SDR_ROW_SIZE_13
213 
`define SDR_BA_SIZE 2
214 
`endif //  `ifdef MT48LC16M16
215 
 
216 
// Refresh whole memory every 64 ms
217 
// Refresh each row every 64 ms
218 
// refresh timeout = 64 ms / Tperiod / number_of_rows
219 
 
220 
// 64 MHz, row_size=12
221 
// 64ms / (1/64MHz) / 2^12 = 1000
222 
// ./VersatileCounter.php 10 1000
223 
// 0101100100
224 
 
225 
`ifdef SDR_SDRAM_CLK_64
226 
    `ifdef SDR_ROW_SIZE_12
227 
        `define SDR_RFR_LENGTH 10
228 
        `define SDR_RFR_WRAP_VALUE 0101100100
229 
    `endif
230 
    `ifdef SDR_ROW_SIZE_13
231 
        `define SDR_RFR_LENGTH 9
232 
        `define SDR_RFR_WRAP_VALUE 001000011
233 
    `endif
234 
`endif
235 
`ifdef SDR_SDRAM_CLK_75
236 
    `ifdef SDR_ROW_SIZE_12
237 
        `define SDR_RFR_LENGTH 11
238 
        `define SDR_RFR_WRAP_VALUE 00110001101
239 
    `endif
240 
    `ifdef SDR_ROW_SIZE_13
241 
        `define SDR_RFR_LENGTH 10
242 
        `define SDR_RFR_WRAP_VALUE 0110111101
243 
    `endif
244 
`endif
245 
`ifdef SDR_SDRAM_CLK_125
246 
    `ifdef SDR_ROW_SIZE_12
247 
        `define SDR_RFR_LENGTH 11
248 
        `define SDR_RFR_WRAP_VALUE 10001000001
249 
    `endif
250 
    `ifdef SDR_ROW_SIZE_13
251 
        `define SDR_RFR_LENGTH 10
252 
        `define SDR_RFR_WRAP_VALUE 1010000111
253 
    `endif
254 
`endif
255 
`ifdef SDR_SDRAM_CLK_133
256 
    `ifdef SDR_ROW_SIZE_12
257 
        `define SDR_RFR_LENGTH 12
258 
        `define SDR_RFR_WRAP_VALUE 101100000111
259 
    `endif
260 
    `ifdef SDR_ROW_SIZE_13
261 
        `define SDR_RFR_LENGTH 11
262 
        `define SDR_RFR_WRAP_VALUE 11111111010
263 
    `endif
264 
`endif
265 
`ifdef SDR_SDRAM_CLK_154
266 
    `ifdef SDR_ROW_SIZE_12
267 
        `define SDR_RFR_LENGTH 12
268 
        `define SDR_RFR_WRAP_VALUE 000101011110
269 
    `endif
270 
    `ifdef SDR_ROW_SIZE_13
271 
        `define SDR_RFR_LENGTH 11
272 
        `define SDR_RFR_WRAP_VALUE 00111101010
273 
    `endif
274 
`endif
275 
 
276 
 
277 
// Disable burst
278 
//`define SDR_NO_BURST
279 
// Enable 4 beat wishbone busrt
280 
`define SDR_BEAT4
281 
// Enable 8 beat wishbone busrt
282 
`define SDR_BEAT8
283 
// Enable 16 beat wishbone busrt
284 
`define SDR_BEAT16
285 
 
286 
// tRFC
287 
`define SDR_TRFC 9
288 
// tRP
289 
`define SDR_TRP 2
290 
// tRCD
291 
`define SDR_TRCD 2
292 
// tMRD
293 
`define SDR_TMRD 2
294 
 
295 
// LMR
296 
// [12:10] reserved
297 
// [9]     WB, write burst; 0 - programmed burst length, 1 - single location
298 
// [8:7]   OP Mode, 2'b00
299 
// [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
300 
// [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
301 
// [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
302 
// LMR: Write burst
303 
`define SDR_INIT_WB 1'b0
304 
// LMR: CAS latency
305 
`define SDR_INIT_CL 3'b010
306 
// LMR: Burst type
307 
`define SDR_INIT_BT 1'b0
308 
// LMR: Burst length
309 
`define SDR_INIT_BL 3'b001
310 
 
311 
`ifdef SDR
312 
    `ifdef SDR_SDRAM_DATA_WIDTH_16
313 
        `define WB_ADR_SIZE `SDR_BA_SIZE+`SDR_COL_SIZE+`SDR_ROW_SIZE+1
314 
    `endif
315 
`endif
316 
 
317 
//=tab DDR2 SDRAM
318 
 
319 
// Use existing Avalon compatible IP
320 
`define DDR2_AVALON
321 
// IP module name
322 
`define DDR2_IP_NAME ALTERA_DDR2
323 
 
324 
`ifdef DDR2
325 
`define WB_ADR_SIZE 24
326 
`endif
327 
 
328 
//=tab DDR3 SDRAM
329 
 
330 
// Board
331 
//=select
332 
`define DDR3_BOARD_2AGX125N // ARRIAII BOARD 2AGX125N
333 
//=end
334 
`ifdef DDR3
335 
`ifdef DDR3_BOARD_2AGX125N
336 
`define WB_ADR_SIZE 30
337 
`endif
338 
`endif

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