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[/] [connect-6/] [trunk/] [BUILD_SCC/] [DE2/] [Reset_Delay.v] - Blame information for rev 18

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module  Reset_Delay(iCLK,oRESET);
input           iCLK;
output reg      oRESET;
reg     [15:0]   Cont;
 
always@(posedge iCLK)
begin
        if(Cont!=16'hFFFF)
        begin
                Cont    <=      Cont+1;
                oRESET  <=      1'b0;
        end
        else
        oRESET  <=      1'b1;
end
 
endmodule

Line No.	Rev	Author	Line
1	4	sumanta.ch	`module Reset_Delay(iCLK,oRESET);`
2			`input iCLK;`
3			`output reg oRESET;`
4			`reg [15:0] Cont;`
5
6			`always@(posedge iCLK)`
7			`begin`
8			`if(Cont!=16'hFFFF)`
9			`begin`
10			`Cont <= Cont+1;`
11			`oRESET <= 1'b0;`
12			`end`
13			`else`
14			`oRESET <= 1'b1;`
15			`end`
16
17			`endmodule`

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[/] [connect-6/] [trunk/] [BUILD_SCC/] [DE2/] [Reset_Delay.v] - Blame information for rev 18