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[/] [connect-6/] [trunk/] [BUILD_SCC/] [DE2/] [async_transmitter_altera.v] - Blame information for rev 13

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1 4 sumanta.ch
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
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input clk, TxD_start;
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input [7:0] TxD_data;
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output TxD, TxD_busy;
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6 8 sumanta.ch
//parameter ClkFrequency = 62500000; // 60MHz
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parameter ClkFrequency = 50000000; // 50MHz
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//parameter ClkFrequency = 27000000; // 27MHz
9 4 sumanta.ch
parameter Baud = 115200;
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// Baud generator
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parameter BaudGeneratorAccWidth = 16;
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parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
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reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
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wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
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wire TxD_busy;
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always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
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// Transmitter state machine
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reg [3:0] state;
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assign TxD_busy = (state!=0);
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always @(posedge clk)
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case(state)
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  4'b0000: if(TxD_start) state <= 4'b0100;
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  4'b0100: if(BaudTick) state <= 4'b1000;  // start
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  4'b1000: if(BaudTick) state <= 4'b1001;  // bit 0
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  4'b1001: if(BaudTick) state <= 4'b1010;  // bit 1
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  4'b1010: if(BaudTick) state <= 4'b1011;  // bit 2
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  4'b1011: if(BaudTick) state <= 4'b1100;  // bit 3
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  4'b1100: if(BaudTick) state <= 4'b1101;  // bit 4
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  4'b1101: if(BaudTick) state <= 4'b1110;  // bit 5
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  4'b1110: if(BaudTick) state <= 4'b1111;  // bit 6
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  4'b1111: if(BaudTick) state <= 4'b0001;  // bit 7
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  4'b0001: if(BaudTick) state <= 4'b0010;  // stop1
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  4'b0010: if(BaudTick) state <= 4'b0000;  // stop2
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  default: if(BaudTick) state <= 4'b0000;
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endcase
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// Output mux
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reg muxbit;
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always @(state[2:0] or TxD_data)
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case(state[2:0])
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  0: muxbit <= TxD_data[0];
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  1: muxbit <= TxD_data[1];
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  2: muxbit <= TxD_data[2];
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  3: muxbit <= TxD_data[3];
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  4: muxbit <= TxD_data[4];
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  5: muxbit <= TxD_data[5];
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  6: muxbit <= TxD_data[6];
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  7: muxbit <= TxD_data[7];
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endcase
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// Put together the start, data and stop bits
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reg TxD;
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always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit);  // register the output to make it glitch free
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endmodule

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