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sumanta.ch |
set SYNTH_SRC "synth_src"
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set_project_params -directory ./
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set_project_params -results myboard.txt
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set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
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set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
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if [file exists imp_threat_flat] { delete_implementation imp_threat_flat }
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create_implementation imp_threat_flat
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set_implementation_params -systemc_source no
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set_implementation_params -memory_return_path_external_delay 0%
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set_implementation_params -memory_forward_path_external_delay 0%
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set_implementation_params -instream_forward_path_external_delay 0%
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#set_implementation_params -import_tcab "imp_line"
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#imp_line"
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set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
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set_implementation_params -outstream_return_path_external_delay 0%
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set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
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set_implementation_params -proc ai_threats
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set_implementation_params -memory_forward_boundary_register infer
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set_implementation_params -techlib altera-cyclone3
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set_implementation_params -memory_return_boundary_register infer
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set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
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set_implementation_params -host_memory_access never
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set_implementation_params -device ep3c25-ea144-7
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set_implementation_params -force_independent_stalldomain_tcab yes
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set_implementation_params -init_data_registers yes
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set_implementation_params -outstream_forward_path_external_delay 0%
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set_implementation_params -build_tcab yes
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set_implementation_params -reset_data_registers yes
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set_implementation_params -instream_return_path_external_delay 0%
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set_implementation_params -clock_freq 100
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set_implementation_params -allow_latency_violation no
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#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
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#set_implementation_params -internal_blockram_memory_read_write_ports separate
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csim -golden -cexec_args "-port /dev/ttyS0 -player L"
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preprocess
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csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
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schedule
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csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
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synthesize
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#csim -synthesize -dump_memory_access_trace
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#csim -synthesize with -dump_memory_access_trace -sim_after_synth_phase 5
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create_rtl_package
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#csim -synthesize
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#set_implementation_params -simulator modelsim
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#vlogsim -offline -dotasks 1-30
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