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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC/] [SP6/] [LCD_Controller_safe.v] - Blame information for rev 17

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module LCD_Controller ( //      Host Side
                                                iDATA,iRS,
                                                iStart,oDone,
                                                iCLK,iRST_N,
                                                //      LCD Interface
                                                LCD_DATA,
                                                LCD_RW,
                                                LCD_EN,
                                                LCD_RS  );
//      CLK
parameter       CLK_Divide      =       16;
 
//      Host Side
input   [7:0]    iDATA;
input   iRS,iStart;
input   iCLK,iRST_N;
output  reg             oDone;
//      LCD Interface
output  [7:0]    LCD_DATA;
output  reg             LCD_EN;
output                  LCD_RW;
output                  LCD_RS;
//      Internal Register
reg             [4:0]    Cont;
reg             [1:0]    ST;
reg             preStart,mStart;
 
/////////////////////////////////////////////
//      Only write to LCD, bypass iRS to LCD_RS
assign  LCD_DATA        =       iDATA;
assign  LCD_RW          =       1'b0;
assign  LCD_RS          =       iRS;
/////////////////////////////////////////////
 
always@(posedge iCLK or negedge iRST_N)
begin
        if(!iRST_N)
        begin
                oDone   <=      1'b0;
                LCD_EN  <=      1'b0;
                preStart<=      1'b0;
                mStart  <=      1'b0;
                Cont    <=      0;
                ST              <=      0;
        end
        else
        begin
                //////  Input Start Detect ///////
                preStart<=      iStart;
                if({preStart,iStart}==2'b01)
                begin
                        mStart  <=      1'b1;
                        oDone   <=      1'b0;
                end
                //////////////////////////////////
                if(mStart)
                begin
                        case(ST)
                        0:       ST      <=      1;      //      Wait Setup
                        1:      begin
                                        LCD_EN  <=      1'b1;
                                        ST              <=      2;
                                end
                        2:      begin
                                        if(Cont<CLK_Divide)
                                        Cont    <=      Cont+1;
                                        else
                                        ST              <=      3;
                                end
                        3:      begin
                                        LCD_EN  <=      1'b0;
                                        mStart  <=      1'b0;
                                        oDone   <=      1'b1;
                                        Cont    <=      0;
                                        ST              <=      0;
                                end
                        endcase
                end
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	17	sumanta.ch	`module LCD_Controller ( // Host Side`
2			`iDATA,iRS,`
3			`iStart,oDone,`
4			`iCLK,iRST_N,`
5			`// LCD Interface`
6			`LCD_DATA,`
7			`LCD_RW,`
8			`LCD_EN,`
9			`LCD_RS );`
10			`// CLK`
11			`parameter CLK_Divide = 16;`
12
13			`// Host Side`
14			`input [7:0] iDATA;`
15			`input iRS,iStart;`
16			`input iCLK,iRST_N;`
17			`output reg oDone;`
18			`// LCD Interface`
19			`output [7:0] LCD_DATA;`
20			`output reg LCD_EN;`
21			`output LCD_RW;`
22			`output LCD_RS;`
23			`// Internal Register`
24			`reg [4:0] Cont;`
25			`reg [1:0] ST;`
26			`reg preStart,mStart;`
27
28			`/////////////////////////////////////////////`
29			`// Only write to LCD, bypass iRS to LCD_RS`
30			`assign LCD_DATA = iDATA;`
31			`assign LCD_RW = 1'b0;`
32			`assign LCD_RS = iRS;`
33			`/////////////////////////////////////////////`
34
35			`always@(posedge iCLK or negedge iRST_N)`
36			`begin`
37			`if(!iRST_N)`
38			`begin`
39			`oDone <= 1'b0;`
40			`LCD_EN <= 1'b0;`
41			`preStart<= 1'b0;`
42			`mStart <= 1'b0;`
43			`Cont <= 0;`
44			`ST <= 0;`
45			`end`
46			`else`
47			`begin`
48			`////// Input Start Detect ///////`
49			`preStart<= iStart;`
50			`if({preStart,iStart}==2'b01)`
51			`begin`
52			`mStart <= 1'b1;`
53			`oDone <= 1'b0;`
54			`end`
55			`//////////////////////////////////`
56			`if(mStart)`
57			`begin`
58			`case(ST)`
59			`0: ST <= 1; // Wait Setup`
60			`1: begin`
61			`LCD_EN <= 1'b1;`
62			`ST <= 2;`
63			`end`
64			`2: begin`
65			`if(Cont<CLK_Divide)`
66			`Cont <= Cont+1;`
67			`else`
68			`ST <= 3;`
69			`end`
70			`3: begin`
71			`LCD_EN <= 1'b0;`
72			`mStart <= 1'b0;`
73			`oDone <= 1'b1;`
74			`Cont <= 0;`
75			`ST <= 0;`
76			`end`
77			`endcase`
78			`end`
79			`end`
80			`end`
81
82			`endmodule`

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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC/] [SP6/] [LCD_Controller_safe.v] - Blame information for rev 17