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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC/] [SP6/] [RS232_Controller.v] - Blame information for rev 17

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1 17 sumanta.ch
module RS232_Controller(oDATA,iDATA,oTxD,oTxD_Busy,iTxD_Start,
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                                                iRxD,oRxD_Ready,oRxD_ERROR,oRxD_idle,iCLK,RST_n);
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input [7:0] iDATA;
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input iTxD_Start,iRxD,iCLK,RST_n;
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output [7:0] oDATA;
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output oTxD,oTxD_Busy,oRxD_Ready,oRxD_ERROR,oRxD_idle;
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async_receiver          u0      (       /*.RST_n(RST_n),*/.clk(iCLK), .RxD(iRxD),
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                                                        .RxD_data_ready(oRxD_Ready),/*.RxD_data_error(oRxD_ERROR),*/
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                                                        .RxD_data(oDATA),.RxD_idle(oRxD_idle));
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//serie                                 u0      (       .n_reset(RST_n),.clk(iCLK), .rx_in(iRxD),
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//                                                      .d_rdy(oRxD_Ready),.d_err(oRxD_ERROR),
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//                                                      .rx_data(oDATA));
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async_transmitter       u1      (       /*.RST_n(RST_n),*/.clk(iCLK), .TxD_start(iTxD_Start),
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                                                        .TxD_data(iDATA), .TxD(oTxD),
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                                                        .TxD_busy(oTxD_Busy));
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endmodule

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