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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC/] [SP6/] [SP6.tcl] - Blame information for rev 17

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1 17 sumanta.ch
# 
2
# Project automation script for DE2 
3
# 
4
# Created for ISE version 13.4
5
# 
6
# This file contains several Tcl procedures (procs) that you can use to automate
7
# your project by running from xtclsh or the Project Navigator Tcl console.
8
# If you load this file (using the Tcl command: source DE2.tcl), then you can
9
# run any of the procs included here.
10
# 
11
# This script is generated assuming your project has HDL sources.
12
# Several of the defined procs won't apply to an EDIF or NGC based project.
13
# If that is the case, simply remove them from this script.
14
# 
15
# You may also edit any of these procs to customize them. See comments in each
16
# proc for more instructions.
17
# 
18
# This file contains the following procedures:
19
# 
20
# Top Level procs (meant to be called directly by the user):
21
#    run_process: you can use this top-level procedure to run any processes
22
#        that you choose to by adding and removing comments, or by
23
#        adding new entries.
24
#    rebuild_project: you can alternatively use this top-level procedure
25
#        to recreate your entire project, and the run selected processes.
26
# 
27
# Lower Level (helper) procs (called under in various cases by the top level procs):
28
#    show_help: print some basic information describing how this script works
29
#    add_source_files: adds the listed source files to your project.
30
#    set_project_props: sets the project properties that were in effect when this
31
#        script was generated.
32
#    create_libraries: creates and adds file to VHDL libraries that were defined when
33
#        this script was generated.
34
#    set_process_props: set the process properties as they were set for your project
35
#        when this script was generated.
36
# 
37
 
38
set myProject "DE2"
39
set myScript "DE2.tcl"
40
 
41
# 
42
# Main (top-level) routines
43
# 
44
# run_process
45
# This procedure is used to run processes on an existing project. You may comment or
46
# uncomment lines to control which processes are run. This routine is set up to run
47
# the Implement Design and Generate Programming File processes by default. This proc
48
# also sets process properties as specified in the "set_process_props" proc. Only
49
# those properties which have values different from their current settings in the project
50
# file will be modified in the project.
51
# 
52
proc run_process {} {
53
 
54
   global myScript
55
   global myProject
56
 
57
   ## put out a 'heartbeat' - so we know something's happening.
58
   puts "\n$myScript: running ($myProject)...\n"
59
 
60
   if { ! [ open_project ] } {
61
      return false
62
   }
63
 
64
   set_process_props
65
   #
66
   # Remove the comment characters (#'s) to enable the following commands 
67
   # process run "Synthesize"
68
   # process run "Translate"
69
   # process run "Map"
70
   # process run "Place & Route"
71
   #
72
   set task "Implement Design"
73
   if { ! [run_task $task] } {
74
      puts "$myScript: $task run failed, check run output for details."
75
      project close
76
      return
77
   }
78
 
79
   set task "Generate Programming File"
80
   if { ! [run_task $task] } {
81
      puts "$myScript: $task run failed, check run output for details."
82
      project close
83
      return
84
   }
85
 
86
   puts "Run completed (successfully)."
87
   project close
88
 
89
}
90
 
91
# 
92
# rebuild_project
93
# 
94
# This procedure renames the project file (if it exists) and recreates the project.
95
# It then sets project properties and adds project sources as specified by the
96
# set_project_props and add_source_files support procs. It recreates VHDL Libraries
97
# as they existed at the time this script was generated.
98
# 
99
# It then calls run_process to set process properties and run selected processes.
100
# 
101
proc rebuild_project {} {
102
 
103
   global myScript
104
   global myProject
105
 
106
   project close
107
   ## put out a 'heartbeat' - so we know something's happening.
108
   puts "\n$myScript: Rebuilding ($myProject)...\n"
109
 
110
   set proj_exts [ list ise xise gise ]
111
   foreach ext $proj_exts {
112
      set proj_name "${myProject}.$ext"
113
      if { [ file exists $proj_name ] } {
114
         file delete $proj_name
115
      }
116
   }
117
 
118
   project new $myProject
119
   set_project_props
120
   add_source_files
121
   create_libraries
122
   puts "$myScript: project rebuild completed."
123
 
124
   run_process
125
 
126
}
127
 
128
# 
129
# Support Routines
130
# 
131
 
132
# 
133
proc run_task { task } {
134
 
135
   # helper proc for run_process
136
 
137
   puts "Running '$task'"
138
   set result [ process run "$task" ]
139
   #
140
   # check process status (and result)
141
   set status [ process get $task status ]
142
   if { ( ( $status != "up_to_date" ) && \
143
            ( $status != "warnings" ) ) || \
144
         ! $result } {
145
      return false
146
   }
147
   return true
148
}
149
 
150
# 
151
# show_help: print information to help users understand the options available when
152
#            running this script.
153
# 
154
proc show_help {} {
155
 
156
   global myScript
157
 
158
   puts ""
159
   puts "usage: xtclsh $myScript <options>"
160
   puts "       or you can run xtclsh and then enter 'source $myScript'."
161
   puts ""
162
   puts "options:"
163
   puts "   run_process       - set properties and run processes."
164
   puts "   rebuild_project   - rebuild the project from scratch and run processes."
165
   puts "   set_project_props - set project properties (device, speed, etc.)"
166
   puts "   add_source_files  - add source files"
167
   puts "   create_libraries  - create vhdl libraries"
168
   puts "   set_process_props - set process property values"
169
   puts "   show_help         - print this message"
170
   puts ""
171
}
172
 
173
proc open_project {} {
174
 
175
   global myScript
176
   global myProject
177
 
178
   if { ! [ file exists ${myProject}.xise ] } {
179
      ## project file isn't there, rebuild it.
180
      puts "Project $myProject not found. Use project_rebuild to recreate it."
181
      return false
182
   }
183
 
184
   project open $myProject
185
 
186
   return true
187
 
188
}
189
# 
190
# set_project_props
191
# 
192
# This procedure sets the project properties as they were set in the project
193
# at the time this script was generated.
194
# 
195
proc set_project_props {} {
196
 
197
   global myScript
198
 
199
   if { ! [ open_project ] } {
200
      return false
201
   }
202
 
203
   puts "$myScript: Setting project properties..."
204
 
205
   project set family "Spartan6"
206
   project set device "xc6slx45t"
207
   project set package "fgg484"
208
   project set speed "-3"
209
   project set top_level_module_type "HDL"
210
   project set synthesis_tool "XST (VHDL/Verilog)"
211
   project set simulator "ISim (VHDL/Verilog)"
212
   project set "Preferred Language" "Verilog"
213
   project set "Enable Message Filtering" "false"
214
 
215
}
216
 
217
 
218
# 
219
# add_source_files
220
# 
221
# This procedure add the source files that were known to the project at the
222
# time this script was generated.
223
# 
224
proc add_source_files {} {
225
 
226
   global myScript
227
 
228
   if { ! [ open_project ] } {
229
      return false
230
   }
231
 
232
   puts "$myScript: Adding sources to project..."
233
 
234
   xfile add "../../../../../../SP6/AI.vhd"
235
   xfile add "../../../../../../SP6/CMD_Decode_simple.v"
236
   xfile add "../../../../../../SP6/DE2.v"
237
   xfile add "../../../../../../SP6/LCD_Controller_safe.v"
238
   xfile add "../../../../../../SP6/LCD_TEST_SAFE.v"
239
   xfile add "../../../../../../SP6/RS232_Command.h"
240
   xfile add "../../../../../../SP6/RS232_Controller.v"
241
   xfile add "../../../../../../SP6/Reset_Delay.v"
242
   xfile add "../../../../../../SP6/SEG7_LUT.v"
243
   xfile add "../../../../../../SP6/SEG7_LUT_8.v"
244
   xfile add "../../../../../../SP6/async_receiver_altera.v"
245
   xfile add "../../../../../../SP6/async_transmitter_altera.v"
246
   xfile add "../../../../../../SP6/bram_based_stream_buffer.v"
247
   xfile add "../../../../../../SP6/safe_test.vhd"
248
   xfile add "../../../../macrocells/RA1SH.v"
249
   xfile add "../../../../macrocells/RA2SH.v"
250
   xfile add "../../../../macrocells/SRAM_4.v"
251
   xfile add "../../../../macrocells/addsubw.v"
252
   xfile add "../../../../macrocells/addw.v"
253
   xfile add "../../../../macrocells/andw.v"
254
   xfile add "../../../../macrocells/brf.v"
255
   xfile add "../../../../macrocells/cmpp_eq_1_4.v"
256
   xfile add "../../../../macrocells/cmpp_eq_2_4.v"
257
   xfile add "../../../../macrocells/cmpp_ineq_13_40.v"
258
   xfile add "../../../../macrocells/cmpp_ineq_21_40.v"
259
   xfile add "../../../../macrocells/cmpp_ineq_29_40.v"
260
   xfile add "../../../../macrocells/cmpp_ineq_37_40.v"
261
   xfile add "../../../../macrocells/cmpp_neq_1_4.v"
262
   xfile add "../../../../macrocells/cmpp_neq_2_4.v"
263
   xfile add "../../../../macrocells/cmpr_eq.v"
264
   xfile add "../../../../macrocells/cmpr_ineq_3.v"
265
   xfile add "../../../../macrocells/cmpr_ineq_4.v"
266
   xfile add "../../../../macrocells/cmpr_ineq_5.v"
267
   xfile add "../../../../macrocells/cmpr_ineq_7.v"
268
   xfile add "../../../../macrocells/cmpr_ineq_8.v"
269
   xfile add "../../../../macrocells/cmpr_ineq_9.v"
270
   xfile add "../../../../macrocells/cmpr_neq.v"
271
   xfile add "../../../../macrocells/combine12_wn.v"
272
   xfile add "../../../../macrocells/combine26_wn.v"
273
   xfile add "../../../../macrocells/combine2_wn.v"
274
   xfile add "../../../../macrocells/combine32_wn.v"
275
   xfile add "../../../../macrocells/combine3_wn.v"
276
   xfile add "../../../../macrocells/counter.v"
277
   xfile add "../../../../macrocells/decode.v"
278
   xfile add "../../../../macrocells/delayn.v"
279
   xfile add "../../../../macrocells/equal.v"
280
   xfile add "../../../../macrocells/fifo.v"
281
   xfile add "../../../../macrocells/ldlm_lx.v"
282
   xfile add "../../../../macrocells/ldlmff_raw_lx.v"
283
   xfile add "../../../../macrocells/ldstlm_lx.v"
284
   xfile add "../../../../macrocells/ldstlmff_lx.v"
285
   xfile add "../../../../macrocells/ldstr_sx.v"
286
   xfile add "../../../../macrocells/lshiftw.v"
287
   xfile add "../../../../macrocells/minmaxw_0.v"
288
   xfile add "../../../../macrocells/minmaxw_1.v"
289
   xfile add "../../../../macrocells/mpyw_1_stage.v"
290
   xfile add "../../../../macrocells/mpyw_multi_stage.v"
291
   xfile add "../../../../macrocells/orw.v"
292
   xfile add "../../../../macrocells/rsflipflop_noinit.v"
293
   xfile add "../../../../macrocells/select_11_1_wn.v"
294
   xfile add "../../../../macrocells/select_12_1_wn.v"
295
   xfile add "../../../../macrocells/select_17_1_wn.v"
296
   xfile add "../../../../macrocells/select_1_1_wn.v"
297
   xfile add "../../../../macrocells/select_2_1_wn.v"
298
   xfile add "../../../../macrocells/select_3_1_wn.v"
299
   xfile add "../../../../macrocells/select_4_1_wn.v"
300
   xfile add "../../../../macrocells/select_5_1_wn.v"
301
   xfile add "../../../../macrocells/select_6_1_wn.v"
302
   xfile add "../../../../macrocells/select_7_1_wn.v"
303
   xfile add "../../../../macrocells/select_8_1_wn.v"
304
   xfile add "../../../../macrocells/select_9_1_wn.v"
305
   xfile add "../../../../macrocells/sext.v"
306
   xfile add "../../../../macrocells/shlkw.v"
307
   xfile add "../../../../macrocells/shrkw.v"
308
   xfile add "../../../../macrocells/sramff_raw_1.v"
309
   xfile add "../../../../macrocells/sramff_raw_2.v"
310
   xfile add "../../../../macrocells/sramff_raw_4.v"
311
   xfile add "../../../../macrocells/sregn_noinit.v"
312
   xfile add "../../../../macrocells/staller.v"
313
   xfile add "../../../../macrocells/stlm_lx.v"
314
   xfile add "../../../../macrocells/stlmff_raw_lx.v"
315
   xfile add "../../../../macrocells/ststr_sx.v"
316
   xfile add "../../../../macrocells/xorw.v"
317
   xfile add "../../../../rtl/ai_adjacent_pa_0.v"
318
   xfile add "../../../../rtl/ai_adjacent_paw_0.v"
319
   xfile add "../../../../rtl/ai_adjacent_pe_0.v"
320
   xfile add "../../../../rtl/ai_adjacent_tcab.v"
321
   xfile add "../../../../rtl/ai_adjacent_tcab_assertions.v"
322
   xfile add "../../../../rtl/ai_threats_pa_0.v"
323
   xfile add "../../../../rtl/ai_threats_paw_0.v"
324
   xfile add "../../../../rtl/ai_threats_pe_0.v"
325
   xfile add "../../../../rtl/ai_threats_tcab.v"
326
   xfile add "../../../../rtl/ai_threats_tcab_assertions.v"
327
   xfile add "../../../../rtl/ai_threats_wide_ldstream0_0.v"
328
   xfile add "../../../../rtl/ai_threats_wide_ststream0_0.v"
329
   xfile add "../../../../rtl/connect6ai_synth_pa_0.v"
330
   xfile add "../../../../rtl/connect6ai_synth_paw_0.v"
331
   xfile add "../../../../rtl/connect6ai_synth_pe_0.v"
332
   xfile add "../../../../rtl/connect6ai_synth_tcab.v"
333
   xfile add "../../../../rtl/connect6ai_synth_tcab_assertions.v"
334
   xfile add "../../../../rtl/threat_line_pa_0.v"
335
   xfile add "../../../../rtl/threat_line_paw_0.v"
336
   xfile add "../../../../rtl/threat_line_pe_0.v"
337
   xfile add "../../../../rtl/threat_line_tcab.v"
338
   xfile add "../../../../rtl/threat_line_tcab_assertions.v"
339
   xfile add "../../../../rtl/threat_window_pa_0.v"
340
   xfile add "../../../../rtl/threat_window_paw_0.v"
341
   xfile add "../../../../rtl/threat_window_pe_0.v"
342
   xfile add "../../../../rtl/threat_window_tcab.v"
343
   xfile add "../../../../rtl/threat_window_tcab_assertions.v"
344
 
345
   # Set the Top Module as well...
346
   project set top "DE2"
347
 
348
   puts "$myScript: project sources reloaded."
349
 
350
} ; # end add_source_files
351
 
352
# 
353
# create_libraries
354
# 
355
# This procedure defines VHDL libraries and associates files with those libraries.
356
# It is expected to be used when recreating the project. Any libraries defined
357
# when this script was generated are recreated by this procedure.
358
# 
359
proc create_libraries {} {
360
 
361
   global myScript
362
 
363
   if { ! [ open_project ] } {
364
      return false
365
   }
366
 
367
   puts "$myScript: Creating libraries..."
368
 
369
 
370
   # must close the project or library definitions aren't saved.
371
   project save
372
 
373
} ; # end create_libraries
374
 
375
# 
376
# set_process_props
377
# 
378
# This procedure sets properties as requested during script generation (either
379
# all of the properties, or only those modified from their defaults).
380
# 
381
proc set_process_props {} {
382
 
383
   global myScript
384
 
385
   if { ! [ open_project ] } {
386
      return false
387
   }
388
 
389
   puts "$myScript: setting process properties..."
390
 
391
   #project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
392
   ##project set "Global Optimization" "Off" -process "Map"
393
   #project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
394
   #project set "Place And Route Mode" "Route Only" -process "Place & Route"
395
   #project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
396
   #project set "Filter Files From Compile Order" "true"
397
   #project set "Last Applied Goal" "Balanced"
398
   #project set "Last Applied Strategy" "Xilinx Default (unlocked)"
399
   #project set "Last Unlock Status" "false"
400
   #project set "Manual Compile Order" "false"
401
   #project set "Placer Effort Level" "High" -process "Map"
402
   #project set "Extra Cost Tables" "0" -process "Map"
403
   #project set "LUT Combining" "Off" -process "Map"
404
   #project set "Combinatorial Logic Optimization" "false" -process "Map"
405
   #project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
406
   #project set "Power Reduction" "Off" -process "Map"
407
   #project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
408
   #project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
409
   #project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
410
   #project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
411
   #project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
412
   #project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
413
   #project set "Project Description" ""
414
   #project set "Property Specification in Project File" "Store all values"
415
   #project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
416
   #project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
417
   #project set "Case Implementation Style" "None" -process "Synthesize - XST"
418
   #project set "RAM Extraction" "true" -process "Synthesize - XST"
419
   #project set "ROM Extraction" "true" -process "Synthesize - XST"
420
   #project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
421
   #project set "Optimization Goal" "Speed" -process "Synthesize - XST"
422
   #project set "Optimization Effort" "Normal" -process "Synthesize - XST"
423
   #project set "Resource Sharing" "true" -process "Synthesize - XST"
424
   #project set "Shift Register Extraction" "true" -process "Synthesize - XST"
425
   #project set "User Browsed Strategy Files" "/opt/Xilinx/13.4/ISE_DS/ISE/data/default.xds"
426
   #project set "VHDL Source Analysis Standard" "VHDL-93"
427
   ##project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
428
   ##project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
429
   #project set "Input TCL Command Script" "" -process "Generate Text Power Report"
430
   #project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
431
   #project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
432
   #project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
433
   #project set "Load Simulation File" "Default" -process "Generate Text Power Report"
434
   #project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
435
   #project set "Load Setting File" "" -process "Generate Text Power Report"
436
   #project set "Setting Output File" "" -process "Generate Text Power Report"
437
   #project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
438
   #project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
439
   ##project set "Essential Bits" "false" -process "Generate Programming File"
440
   #project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
441
   #project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
442
   #project set "Show All Models" "false" -process "Generate IBIS Model"
443
   ##project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
444
   #project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
445
   #project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
446
   #project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
447
   #project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
448
   #project set "Ignore User Timing Constraints" "false" -process "Map"
449
   #project set "Register Ordering" "4" -process "Map"
450
   #project set "Use RLOC Constraints" "Yes" -process "Map"
451
   #project set "Other Map Command Line Options" "" -process "Map"
452
   #project set "Use LOC Constraints" "true" -process "Translate"
453
   #project set "Other Ngdbuild Command Line Options" "" -process "Translate"
454
   #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
455
   #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
456
   #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
457
   #project set "Ignore User Timing Constraints" "false" -process "Place & Route"
458
   #project set "Other Place & Route Command Line Options" "" -process "Place & Route"
459
   #project set "Use DSP Block" "Auto" -process "Synthesize - XST"
460
   #project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
461
   #project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
462
   ##project set "Enable External Master Clock" "false" -process "Generate Programming File"
463
   #project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
464
   #project set "Create Bit File" "true" -process "Generate Programming File"
465
   #project set "Enable BitStream Compression" "false" -process "Generate Programming File"
466
   #project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
467
   #project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
468
   #project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
469
   #project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
470
   #project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
471
   #project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
472
   #project set "Configuration Rate" "2" -process "Generate Programming File"
473
   #project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
474
   #project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
475
   #project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
476
   #project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
477
   #project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
478
   #project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
479
   #project set "Watchdog Timer Value" "0xFFFF" -process "Generate Programming File"
480
   #project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
481
   #project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
482
   #project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
483
   #project set "Drive Done Pin High" "false" -process "Generate Programming File"
484
   #project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
485
   #project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
486
   #project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
487
   #project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
488
   #project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
489
   #project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
490
   #project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
491
   #project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
492
   #project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
493
   #project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
494
   #project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
495
   #project set "Maximum Compression" "false" -process "Map"
496
   #project set "Generate Detailed MAP Report" "false" -process "Map"
497
   #project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
498
   #project set "Perform Timing-Driven Packing and Placement" "false"
499
   #project set "Trim Unconnected Signals" "true" -process "Map"
500
   #project set "Create I/O Pads from Ports" "false" -process "Translate"
501
   #project set "Macro Search Path" "" -process "Translate"
502
   #project set "Netlist Translation Type" "Timestamp" -process "Translate"
503
   #project set "User Rules File for Netlister Launcher" "" -process "Translate"
504
   #project set "Allow Unexpanded Blocks" "false" -process "Translate"
505
   #project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
506
   #project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
507
   #project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing"
508
   #project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
509
   #project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
510
   #project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
511
   #project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
512
   #project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
513
   #project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing"
514
   #project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
515
   #project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
516
   #project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
517
   #project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
518
   #project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
519
   #project set "Add I/O Buffers" "true" -process "Synthesize - XST"
520
   #project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
521
   #project set "Keep Hierarchy" "No" -process "Synthesize - XST"
522
   #project set "Max Fanout" "100000" -process "Synthesize - XST"
523
   #project set "Register Balancing" "No" -process "Synthesize - XST"
524
   #project set "Register Duplication" "true" -process "Synthesize - XST"
525
   #project set "Library for Verilog Sources" "" -process "Synthesize - XST"
526
   #project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report"
527
   #project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
528
   #project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
529
   #project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
530
   #project set "Bus Delimiter" "<>" -process "Synthesize - XST"
531
   #project set "Case" "Maintain" -process "Synthesize - XST"
532
   #project set "Cores Search Directories" "" -process "Synthesize - XST"
533
   #project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
534
   #project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
535
   #project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
536
   #project set "FSM Style" "LUT" -process "Synthesize - XST"
537
   #project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
538
   #project set "Generics, Parameters" "" -process "Synthesize - XST"
539
   #project set "Hierarchy Separator" "/" -process "Synthesize - XST"
540
   #project set "HDL INI File" "" -process "Synthesize - XST"
541
   #project set "LUT Combining" "Auto" -process "Synthesize - XST"
542
   #project set "Library Search Order" "" -process "Synthesize - XST"
543
   #project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
544
   #project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
545
   #project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
546
   #project set "Power Reduction" "false" -process "Synthesize - XST"
547
   #project set "Read Cores" "true" -process "Synthesize - XST"
548
   #project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
549
   #project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
550
   #project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
551
   #project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
552
   #project set "Verilog Include Directories" "" -process "Synthesize - XST"
553
   #project set "Verilog Macros" "" -process "Synthesize - XST"
554
   #project set "Work Directory" "/tmp/BUILD_SCC/imp_connect/rtl_package/synth/synplify_fpga/run_2012.05.04_15.04.58/DE2/xst" -process "Synthesize - XST"
555
   #project set "Write Timing Constraints" "false" -process "Synthesize - XST"
556
   #project set "Other XST Command Line Options" "" -process "Synthesize - XST"
557
   #project set "Timing Mode" "Performance Evaluation" -process "Map"
558
   #project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
559
   #project set "Generate Clock Region Report" "false" -process "Place & Route"
560
   #project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
561
   #project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
562
   #project set "Power Reduction" "false" -process "Place & Route"
563
   #project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
564
   #project set "Auto Implementation Compile Order" "true"
565
   #project set "Equivalent Register Removal" "true" -process "Map"
566
   #project set "Placer Extra Effort" "None" -process "Map"
567
   #project set "Power Activity File" "" -process "Map"
568
   #project set "Register Duplication" "Off" -process "Map"
569
   #project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
570
   #project set "Synthesis Constraints File" "" -process "Synthesize - XST"
571
   #project set "RAM Style" "Auto" -process "Synthesize - XST"
572
   #project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
573
   #project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
574
   #project set "Output File Name" "ai_adjacent_tcab" -process "Generate IBIS Model"
575
   #project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
576
   #project set "Create Binary Configuration File" "false" -process "Generate Programming File"
577
   #project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
578
   #project set "Create Logic Allocation File" "false" -process "Generate Programming File"
579
   #project set "Create Mask File" "false" -process "Generate Programming File"
580
   #project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File"
581
   #project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File"
582
   #project set "MultiBoot: Starting Address for Golden Configuration" "0x00000000" -process "Generate Programming File"
583
   #project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
584
   #project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
585
   #project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
586
   #project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
587
   #project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
588
   #project set "Enable Multi-Threading" "Off" -process "Map"
589
   #project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
590
   #project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
591
   #project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
592
   #project set "ROM Style" "Auto" -process "Synthesize - XST"
593
   #project set "Safe Implementation" "No" -process "Synthesize - XST"
594
   #project set "Power Activity File" "" -process "Place & Route"
595
   #project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
596
   #project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
597
   #project set "Encrypt Bitstream" "false" -process "Generate Programming File"
598
   #project set "Enable Multi-Threading" "Off" -process "Place & Route"
599
   #project set "AES Initial Vector" "" -process "Generate Programming File"
600
   #project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
601
   #project set "AES Key (Hex String)" "" -process "Generate Programming File"
602
   #project set "Input Encryption Key File" "" -process "Generate Programming File"
603
   #project set "Functional Model Target Language" "Verilog" -process "View HDL Source"
604
   #project set "Change Device Speed To" "-3" -process "Generate Post-Place & Route Static Timing"
605
   #project set "Change Device Speed To" "-3" -process "Generate Post-Map Static Timing"
606
 
607
   puts "$myScript: project property values set."
608
 
609
} ; # end set_process_props
610
 
611
proc main {} {
612
 
613
   if { [llength $::argv] == 0 } {
614
      show_help
615
      return true
616
   }
617
 
618
   foreach option $::argv {
619
      switch $option {
620
         "show_help"           { show_help }
621
         "run_process"         { run_process }
622
         "rebuild_project"     { rebuild_project }
623
         "set_project_props"   { set_project_props }
624
         "add_source_files"    { add_source_files }
625
         "create_libraries"    { create_libraries }
626
         "set_process_props"   { set_process_props }
627
         default               { puts "unrecognized option: $option"; show_help }
628
      }
629
   }
630
}
631
 
632
if { $tcl_interactive } {
633
   show_help
634
} else {
635
   if {[catch {main} result]} {
636
      puts "$myScript failed: $result."
637
   }
638
}
639
 

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