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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC/] [SP6/] [async_receiver_altera.v] - Blame information for rev 17

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1 17 sumanta.ch
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
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input clk, RxD;
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output RxD_data_ready;  // onc clock pulse when RxD_data is valid
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output [7:0] RxD_data;
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//parameter ClkFrequency = 62500000; // 50MHz
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parameter ClkFrequency = 20000000; // 50MHz
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//parameter ClkFrequency = 27000000; // 27MHz
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parameter Baud = 115200;
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// We also detect if a gap occurs in the received stream of characters
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// That can be useful if multiple characters are sent in burst
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//  so that multiple characters can be treated as a "packet"
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output RxD_endofpacket;  // one clock pulse, when no more data is received (RxD_idle is going high)
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output RxD_idle;  // no data is being received
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// Baud generator (we use 8 times oversampling)
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parameter Baud8 = Baud*8;
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parameter Baud8GeneratorAccWidth = 16;
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parameter Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
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reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
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always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
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wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
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////////////////////////////
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reg [1:0] RxD_sync_inv;
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always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
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// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
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reg [1:0] RxD_cnt_inv;
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reg RxD_bit_inv;
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always @(posedge clk)
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if(Baud8Tick)
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begin
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  if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 1;
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  else
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  if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 1;
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  if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 0;
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  else
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  if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1;
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end
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reg [3:0] state;
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reg [3:0] bit_spacing;
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// "next_bit" controls when the data sampling occurs
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// depending on how noisy the RxD is, different values might work better
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// with a clean connection, values from 8 to 11 work
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wire next_bit = (bit_spacing==10);
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always @(posedge clk)
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if(state==0)
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  bit_spacing <= 0;
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else
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if(Baud8Tick)
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  bit_spacing <= {bit_spacing[2:0] + 1} | {bit_spacing[3], 3'b000};
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always @(posedge clk)
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if(Baud8Tick)
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case(state)
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  4'b0000: if(RxD_bit_inv) state <= 4'b1000;  // start bit found?
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  4'b1000: if(next_bit) state <= 4'b1001;  // bit 0
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  4'b1001: if(next_bit) state <= 4'b1010;  // bit 1
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  4'b1010: if(next_bit) state <= 4'b1011;  // bit 2
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  4'b1011: if(next_bit) state <= 4'b1100;  // bit 3
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  4'b1100: if(next_bit) state <= 4'b1101;  // bit 4
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  4'b1101: if(next_bit) state <= 4'b1110;  // bit 5
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  4'b1110: if(next_bit) state <= 4'b1111;  // bit 6
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  4'b1111: if(next_bit) state <= 4'b0001;  // bit 7
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  4'b0001: if(next_bit) state <= 4'b0000;  // stop bit
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  default: state <= 4'b0000;
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endcase
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reg [7:0] RxD_data;
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always @(posedge clk)
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if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
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reg RxD_data_ready, RxD_data_error;
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always @(posedge clk)
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begin
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  RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv);  // ready only if the stop bit is received
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  RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 &&  RxD_bit_inv);  // error if the stop bit is not received
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end
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reg [4:0] gap_count;
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always @(posedge clk) if (state!=0) gap_count<=0; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 1;
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assign RxD_idle = gap_count[4];
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reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==15);
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endmodule

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