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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC/] [SP6/] [do_synth] - Blame information for rev 17

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Line No. Rev Author Line
1 17 sumanta.ch
 
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#!/bin/sh
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run_logic_synthesis_only=0 ;
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while getopts ":s i" options; do
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    case $options in
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        i ) run_logic_synthesis_only=0;;
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        s ) run_logic_synthesis_only=1;;
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        ? ) echo $usage
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            exit 1;;
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    esac
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done
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################################
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# set up the verilog filelists:
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################################
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export date_of_run=`date +%Y.%m.%d_%H.%M.%S`
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mkdir run_$date_of_run
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rm -f run
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ln -s run_$date_of_run run
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cd run
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if [ $run_logic_synthesis_only -eq 1 ]; then
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    touch .LOGIC_SYNTHESIS_ONLY
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fi
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quartus_sh -t ../quartus.tcl
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if [[ $? != 0 ]]; then exit 1; fi
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quartus_map DE2
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if [[ $? != 0 ]]; then exit 1; fi
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if [ $run_logic_synthesis_only -eq 1 ]; then
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    quartus_fit --early_timing_estimate=realistic DE2
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    if [[ $? != 0 ]]; then exit 1; fi
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else
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    quartus_fit DE2
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    if [[ $? != 0 ]]; then exit 1; fi
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fi
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quartus_sta --do_report_timing DE2
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if [[ $? != 0 ]]; then exit 1; fi
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quartus_asm DE2
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quartus_pgm -c USB-Blaster -m jtag  -o "p;DE2.sof"
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cd -
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exit 0
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