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sumanta.ch |
#
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# Constraints generated by Synplify Pro map500rc, Build 036R
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#
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# Period Constraints
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NET "SYSCLK_P" TNM_NET = "SYSCLK_P";
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TIMESPEC "TS_SYSCLK_P" = PERIOD "SYSCLK_P" 5 ns HIGH 50 %;
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#Begin clock constraints
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NET "clocks/clk20_bufg_in" TNM_NET = "clocks_clk20_bufg_in";
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TIMESPEC "TS_clocks_clk20_bufg_in" = PERIOD "clocks_clk20_bufg_in" 50.000 ns HIGH 50.00%;
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#NET "clocks/clkfbout_clkfbin_125" TNM_NET = "clocks_clkfbout_clkfbin_125";
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#TIMESPEC "TS_clocks_clkfbout_clkfbin_125" = PERIOD "clocks_clkfbout_clkfbin_125" 50.000 ns HIGH 50.00%;
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#NET "clocks/osc_clk_ibufg" TNM_NET = "clocks_osc_clk_ibufg";
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#TIMESPEC "TS_clocks_osc_clk_ibufg" = PERIOD "clocks_osc_clk_ibufg" 50.000 ns HIGH 50.00%;
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#End clock constraints
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# Unconstrained Outputs
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NET "HEX0[*]" TIG; # port HEX0[6:0]
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NET "HEX1[*]" TIG; # port HEX1[6:0]
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NET "HEX2[*]" TIG; # port HEX2[6:0]
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NET "HEX3[*]" TIG; # port HEX3[6:0]
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NET "HEX4[*]" TIG; # port HEX4[6:0]
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NET "HEX5[*]" TIG; # port HEX5[6:0]
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NET "HEX6[*]" TIG; # port HEX6[6:0]
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NET "HEX7[*]" TIG; # port HEX7[6:0]
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#NET "LED_GREEN[*]" TIG; # port LED_GREEN[8:0]
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#NET "LED_RED[*]" TIG; # port LED_RED[17:0]
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#NET "UART_TXD" TIG;
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NET "TD_RESET" TIG;
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# Location Constraints
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#PIN "clocks/clk20_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
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## Clock inputs
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NET "SYSCLK_P" LOC = "K21" |IOSTANDARD=LVDS_25;
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NET "SYSCLK_N" LOC = "K22" |IOSTANDARD=LVDS_25;
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NET "LED_RED[9]" LOC = "D17"; ## 2 on DS3 LED
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NET "LED_RED[10]" LOC = "AB4"; ## 2 on DS4 LED
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NET "LED_RED[11]" LOC = "D21"; ## 2 on DS5 LED
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NET "LED_RED[12]" LOC = "W15"; ## 2 on DS6 LED
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NET "KEY[0]" LOC = "F3"; ## 2 on SW4 pushbutton (active-high)
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NET "UART_TXD" LOC = "B21"; ##
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NET "UART_RXD" LOC = "H17"; ##
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# End of generated constraints
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